Hal8188EPhyReg.h 41 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. *
  19. ******************************************************************************/
  20. #ifndef __INC_HAL8188EPHYREG_H__
  21. #define __INC_HAL8188EPHYREG_H__
  22. /*--------------------------Define Parameters-------------------------------*/
  23. //
  24. // BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
  25. // 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
  26. // 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
  27. // 3. RF register 0x00-2E
  28. // 4. Bit Mask for BB/RF register
  29. // 5. Other defintion for BB/RF R/W
  30. //
  31. //
  32. // 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
  33. // 1. Page1(0x100)
  34. //
  35. #define rPMAC_Reset 0x100
  36. #define rPMAC_TxStart 0x104
  37. #define rPMAC_TxLegacySIG 0x108
  38. #define rPMAC_TxHTSIG1 0x10c
  39. #define rPMAC_TxHTSIG2 0x110
  40. #define rPMAC_PHYDebug 0x114
  41. #define rPMAC_TxPacketNum 0x118
  42. #define rPMAC_TxIdle 0x11c
  43. #define rPMAC_TxMACHeader0 0x120
  44. #define rPMAC_TxMACHeader1 0x124
  45. #define rPMAC_TxMACHeader2 0x128
  46. #define rPMAC_TxMACHeader3 0x12c
  47. #define rPMAC_TxMACHeader4 0x130
  48. #define rPMAC_TxMACHeader5 0x134
  49. #define rPMAC_TxDataType 0x138
  50. #define rPMAC_TxRandomSeed 0x13c
  51. #define rPMAC_CCKPLCPPreamble 0x140
  52. #define rPMAC_CCKPLCPHeader 0x144
  53. #define rPMAC_CCKCRC16 0x148
  54. #define rPMAC_OFDMRxCRC32OK 0x170
  55. #define rPMAC_OFDMRxCRC32Er 0x174
  56. #define rPMAC_OFDMRxParityEr 0x178
  57. #define rPMAC_OFDMRxCRC8Er 0x17c
  58. #define rPMAC_CCKCRxRC16Er 0x180
  59. #define rPMAC_CCKCRxRC32Er 0x184
  60. #define rPMAC_CCKCRxRC32OK 0x188
  61. #define rPMAC_TxStatus 0x18c
  62. //
  63. // 2. Page2(0x200)
  64. //
  65. // The following two definition are only used for USB interface.
  66. #define RF_BB_CMD_ADDR 0x02c0 // RF/BB read/write command address.
  67. #define RF_BB_CMD_DATA 0x02c4 // RF/BB read/write command data.
  68. //
  69. // 3. Page8(0x800)
  70. //
  71. #define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting??
  72. #define rFPGA0_TxInfo 0x804 // Status report??
  73. #define rFPGA0_PSDFunction 0x808
  74. #define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain?
  75. #define rFPGA0_RFTiming1 0x810 // Useless now
  76. #define rFPGA0_RFTiming2 0x814
  77. #define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register
  78. #define rFPGA0_XA_HSSIParameter2 0x824
  79. #define rFPGA0_XB_HSSIParameter1 0x828
  80. #define rFPGA0_XB_HSSIParameter2 0x82c
  81. #define rFPGA0_XA_LSSIParameter 0x840
  82. #define rFPGA0_XB_LSSIParameter 0x844
  83. #define rFPGA0_RFWakeUpParameter 0x850 // Useless now
  84. #define rFPGA0_RFSleepUpParameter 0x854
  85. #define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch
  86. #define rFPGA0_XCD_SwitchControl 0x85c
  87. #define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch
  88. #define rFPGA0_XB_RFInterfaceOE 0x864
  89. #define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control
  90. #define rFPGA0_XCD_RFInterfaceSW 0x874
  91. #define rFPGA0_XAB_RFParameter 0x878 // RF Parameter
  92. #define rFPGA0_XCD_RFParameter 0x87c
  93. #define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4??
  94. #define rFPGA0_AnalogParameter2 0x884
  95. #define rFPGA0_AnalogParameter3 0x888
  96. #define rFPGA0_AdDaClockEn 0x888 // enable ad/da clock1 for dual-phy
  97. #define rFPGA0_AnalogParameter4 0x88c
  98. #define rFPGA0_XA_LSSIReadBack 0x8a0 // Tranceiver LSSI Readback
  99. #define rFPGA0_XB_LSSIReadBack 0x8a4
  100. #define rFPGA0_XC_LSSIReadBack 0x8a8
  101. #define rFPGA0_XD_LSSIReadBack 0x8ac
  102. #define rFPGA0_PSDReport 0x8b4 // Useless now
  103. #define TransceiverA_HSPI_Readback 0x8b8 // Transceiver A HSPI Readback
  104. #define TransceiverB_HSPI_Readback 0x8bc // Transceiver B HSPI Readback
  105. #define rFPGA0_XAB_RFInterfaceRB 0x8e0 // Useless now // RF Interface Readback Value
  106. #define rFPGA0_XCD_RFInterfaceRB 0x8e4 // Useless now
  107. //
  108. // 4. Page9(0x900)
  109. //
  110. #define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting??
  111. #define rFPGA1_TxBlock 0x904 // Useless now
  112. #define rFPGA1_DebugSelect 0x908 // Useless now
  113. #define rFPGA1_TxInfo 0x90c // Useless now // Status report??
  114. //
  115. // 5. PageA(0xA00)
  116. //
  117. // Set Control channel to upper or lower. These settings are required only for 40MHz
  118. #define rCCK0_System 0xa00
  119. #define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI
  120. #define rCCK0_CCA 0xa08 // Disable init gain now // Init gain
  121. #define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series
  122. #define rCCK0_RxAGC2 0xa10 //AGC & DAGC
  123. #define rCCK0_RxHP 0xa14
  124. #define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold
  125. #define rCCK0_DSPParameter2 0xa1c //SQ threshold
  126. #define rCCK0_TxFilter1 0xa20
  127. #define rCCK0_TxFilter2 0xa24
  128. #define rCCK0_DebugPort 0xa28 //debug port and Tx filter3
  129. #define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report
  130. #define rCCK0_TRSSIReport 0xa50
  131. #define rCCK0_RxReport 0xa54 //0xa57
  132. #define rCCK0_FACounterLower 0xa5c //0xa5b
  133. #define rCCK0_FACounterUpper 0xa58 //0xa5c
  134. //
  135. // PageB(0xB00)
  136. //
  137. #define rPdp_AntA 0xb00
  138. #define rPdp_AntA_4 0xb04
  139. #define rConfig_Pmpd_AntA 0xb28
  140. #define rConfig_ram64x16 0xb2c
  141. #define rConfig_AntA 0xb68
  142. #define rConfig_AntB 0xb6c
  143. #define rPdp_AntB 0xb70
  144. #define rPdp_AntB_4 0xb74
  145. #define rConfig_Pmpd_AntB 0xb98
  146. #define rAPK 0xbd8
  147. //
  148. // 6. PageC(0xC00)
  149. //
  150. #define rOFDM0_LSTF 0xc00
  151. #define rOFDM0_TRxPathEnable 0xc04
  152. #define rOFDM0_TRMuxPar 0xc08
  153. #define rOFDM0_TRSWIsolation 0xc0c
  154. #define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter
  155. #define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix
  156. #define rOFDM0_XBRxAFE 0xc18
  157. #define rOFDM0_XBRxIQImbalance 0xc1c
  158. #define rOFDM0_XCRxAFE 0xc20
  159. #define rOFDM0_XCRxIQImbalance 0xc24
  160. #define rOFDM0_XDRxAFE 0xc28
  161. #define rOFDM0_XDRxIQImbalance 0xc2c
  162. #define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain
  163. #define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync.
  164. #define rOFDM0_RxDetector3 0xc38 //Frame Sync.
  165. #define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI
  166. #define rOFDM0_RxDSP 0xc40 //Rx Sync Path
  167. #define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC
  168. #define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold
  169. #define rOFDM0_ECCAThreshold 0xc4c // energy CCA
  170. #define rOFDM0_XAAGCCore1 0xc50 // DIG
  171. #define rOFDM0_XAAGCCore2 0xc54
  172. #define rOFDM0_XBAGCCore1 0xc58
  173. #define rOFDM0_XBAGCCore2 0xc5c
  174. #define rOFDM0_XCAGCCore1 0xc60
  175. #define rOFDM0_XCAGCCore2 0xc64
  176. #define rOFDM0_XDAGCCore1 0xc68
  177. #define rOFDM0_XDAGCCore2 0xc6c
  178. #define rOFDM0_AGCParameter1 0xc70
  179. #define rOFDM0_AGCParameter2 0xc74
  180. #define rOFDM0_AGCRSSITable 0xc78
  181. #define rOFDM0_HTSTFAGC 0xc7c
  182. #define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG
  183. #define rOFDM0_XATxAFE 0xc84
  184. #define rOFDM0_XBTxIQImbalance 0xc88
  185. #define rOFDM0_XBTxAFE 0xc8c
  186. #define rOFDM0_XCTxIQImbalance 0xc90
  187. #define rOFDM0_XCTxAFE 0xc94
  188. #define rOFDM0_XDTxIQImbalance 0xc98
  189. #define rOFDM0_XDTxAFE 0xc9c
  190. #define rOFDM0_RxIQExtAnta 0xca0
  191. #define rOFDM0_TxCoeff1 0xca4
  192. #define rOFDM0_TxCoeff2 0xca8
  193. #define rOFDM0_TxCoeff3 0xcac
  194. #define rOFDM0_TxCoeff4 0xcb0
  195. #define rOFDM0_TxCoeff5 0xcb4
  196. #define rOFDM0_TxCoeff6 0xcb8
  197. #define rOFDM0_RxHPParameter 0xce0
  198. #define rOFDM0_TxPseudoNoiseWgt 0xce4
  199. #define rOFDM0_FrameSync 0xcf0
  200. #define rOFDM0_DFSReport 0xcf4
  201. //
  202. // 7. PageD(0xD00)
  203. //
  204. #define rOFDM1_LSTF 0xd00
  205. #define rOFDM1_TRxPathEnable 0xd04
  206. #define rOFDM1_CFO 0xd08 // No setting now
  207. #define rOFDM1_CSI1 0xd10
  208. #define rOFDM1_SBD 0xd14
  209. #define rOFDM1_CSI2 0xd18
  210. #define rOFDM1_CFOTracking 0xd2c
  211. #define rOFDM1_TRxMesaure1 0xd34
  212. #define rOFDM1_IntfDet 0xd3c
  213. #define rOFDM1_PseudoNoiseStateAB 0xd50
  214. #define rOFDM1_PseudoNoiseStateCD 0xd54
  215. #define rOFDM1_RxPseudoNoiseWgt 0xd58
  216. #define rOFDM_PHYCounter1 0xda0 //cca, parity fail
  217. #define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail
  218. #define rOFDM_PHYCounter3 0xda8 //MCS not support
  219. #define rOFDM_ShortCFOAB 0xdac // No setting now
  220. #define rOFDM_ShortCFOCD 0xdb0
  221. #define rOFDM_LongCFOAB 0xdb4
  222. #define rOFDM_LongCFOCD 0xdb8
  223. #define rOFDM_TailCFOAB 0xdbc
  224. #define rOFDM_TailCFOCD 0xdc0
  225. #define rOFDM_PWMeasure1 0xdc4
  226. #define rOFDM_PWMeasure2 0xdc8
  227. #define rOFDM_BWReport 0xdcc
  228. #define rOFDM_AGCReport 0xdd0
  229. #define rOFDM_RxSNR 0xdd4
  230. #define rOFDM_RxEVMCSI 0xdd8
  231. #define rOFDM_SIGReport 0xddc
  232. //
  233. // 8. PageE(0xE00)
  234. //
  235. #define rTxAGC_A_Rate18_06 0xe00
  236. #define rTxAGC_A_Rate54_24 0xe04
  237. #define rTxAGC_A_CCK1_Mcs32 0xe08
  238. #define rTxAGC_A_Mcs03_Mcs00 0xe10
  239. #define rTxAGC_A_Mcs07_Mcs04 0xe14
  240. #define rTxAGC_A_Mcs11_Mcs08 0xe18
  241. #define rTxAGC_A_Mcs15_Mcs12 0xe1c
  242. #define rTxAGC_B_Rate18_06 0x830
  243. #define rTxAGC_B_Rate54_24 0x834
  244. #define rTxAGC_B_CCK1_55_Mcs32 0x838
  245. #define rTxAGC_B_Mcs03_Mcs00 0x83c
  246. #define rTxAGC_B_Mcs07_Mcs04 0x848
  247. #define rTxAGC_B_Mcs11_Mcs08 0x84c
  248. #define rTxAGC_B_Mcs15_Mcs12 0x868
  249. #define rTxAGC_B_CCK11_A_CCK2_11 0x86c
  250. #define rFPGA0_IQK 0xe28
  251. #define rTx_IQK_Tone_A 0xe30
  252. #define rRx_IQK_Tone_A 0xe34
  253. #define rTx_IQK_PI_A 0xe38
  254. #define rRx_IQK_PI_A 0xe3c
  255. #define rTx_IQK 0xe40
  256. #define rRx_IQK 0xe44
  257. #define rIQK_AGC_Pts 0xe48
  258. #define rIQK_AGC_Rsp 0xe4c
  259. #define rTx_IQK_Tone_B 0xe50
  260. #define rRx_IQK_Tone_B 0xe54
  261. #define rTx_IQK_PI_B 0xe58
  262. #define rRx_IQK_PI_B 0xe5c
  263. #define rIQK_AGC_Cont 0xe60
  264. #define rBlue_Tooth 0xe6c
  265. #define rRx_Wait_CCA 0xe70
  266. #define rTx_CCK_RFON 0xe74
  267. #define rTx_CCK_BBON 0xe78
  268. #define rTx_OFDM_RFON 0xe7c
  269. #define rTx_OFDM_BBON 0xe80
  270. #define rTx_To_Rx 0xe84
  271. #define rTx_To_Tx 0xe88
  272. #define rRx_CCK 0xe8c
  273. #define rTx_Power_Before_IQK_A 0xe94
  274. #define rTx_Power_After_IQK_A 0xe9c
  275. #define rRx_Power_Before_IQK_A 0xea0
  276. #define rRx_Power_Before_IQK_A_2 0xea4
  277. #define rRx_Power_After_IQK_A 0xea8
  278. #define rRx_Power_After_IQK_A_2 0xeac
  279. #define rTx_Power_Before_IQK_B 0xeb4
  280. #define rTx_Power_After_IQK_B 0xebc
  281. #define rRx_Power_Before_IQK_B 0xec0
  282. #define rRx_Power_Before_IQK_B_2 0xec4
  283. #define rRx_Power_After_IQK_B 0xec8
  284. #define rRx_Power_After_IQK_B_2 0xecc
  285. #define rRx_OFDM 0xed0
  286. #define rRx_Wait_RIFS 0xed4
  287. #define rRx_TO_Rx 0xed8
  288. #define rStandby 0xedc
  289. #define rSleep 0xee0
  290. #define rPMPD_ANAEN 0xeec
  291. //
  292. // 7. RF Register 0x00-0x2E (RF 8256)
  293. // RF-0222D 0x00-3F
  294. //
  295. //Zebra1
  296. #define rZebra1_HSSIEnable 0x0 // Useless now
  297. #define rZebra1_TRxEnable1 0x1
  298. #define rZebra1_TRxEnable2 0x2
  299. #define rZebra1_AGC 0x4
  300. #define rZebra1_ChargePump 0x5
  301. #define rZebra1_Channel 0x7 // RF channel switch
  302. //#endif
  303. #define rZebra1_TxGain 0x8 // Useless now
  304. #define rZebra1_TxLPF 0x9
  305. #define rZebra1_RxLPF 0xb
  306. #define rZebra1_RxHPFCorner 0xc
  307. //Zebra4
  308. #define rGlobalCtrl 0 // Useless now
  309. #define rRTL8256_TxLPF 19
  310. #define rRTL8256_RxLPF 11
  311. //RTL8258
  312. #define rRTL8258_TxLPF 0x11 // Useless now
  313. #define rRTL8258_RxLPF 0x13
  314. #define rRTL8258_RSSILPF 0xa
  315. //
  316. // RL6052 Register definition
  317. //
  318. #define RF_AC 0x00 //
  319. #define RF_IQADJ_G1 0x01 //
  320. #define RF_IQADJ_G2 0x02 //
  321. #define RF_POW_TRSW 0x05 //
  322. #define RF_GAIN_RX 0x06 //
  323. #define RF_GAIN_TX 0x07 //
  324. #define RF_TXM_IDAC 0x08 //
  325. #define RF_IPA_G 0x09 //
  326. #define RF_TXBIAS_G 0x0A
  327. #define RF_TXPA_AG 0x0B
  328. #define RF_IPA_A 0x0C //
  329. #define RF_TXBIAS_A 0x0D
  330. #define RF_BS_PA_APSET_G9_G11 0x0E
  331. #define RF_BS_IQGEN 0x0F //
  332. #define RF_MODE1 0x10 //
  333. #define RF_MODE2 0x11 //
  334. #define RF_RX_AGC_HP 0x12 //
  335. #define RF_TX_AGC 0x13 //
  336. #define RF_BIAS 0x14 //
  337. #define RF_IPA 0x15 //
  338. #define RF_TXBIAS 0x16
  339. #define RF_POW_ABILITY 0x17 //
  340. #define RF_CHNLBW 0x18 // RF channel and BW switch
  341. #define RF_TOP 0x19 //
  342. #define RF_RX_G1 0x1A //
  343. #define RF_RX_G2 0x1B //
  344. #define RF_RX_BB2 0x1C //
  345. #define RF_RX_BB1 0x1D //
  346. #define RF_RCK1 0x1E //
  347. #define RF_RCK2 0x1F //
  348. #define RF_TX_G1 0x20 //
  349. #define RF_TX_G2 0x21 //
  350. #define RF_TX_G3 0x22 //
  351. #define RF_TX_BB1 0x23 //
  352. //#if HARDWARE_TYPE_IS_RTL8192D == 1
  353. #define RF_T_METER_92D 0x42 //
  354. //#else
  355. #define RF_T_METER_88E 0x42 //
  356. #define RF_T_METER 0x24 //
  357. //#endif
  358. #define RF_SYN_G1 0x25 // RF TX Power control
  359. #define RF_SYN_G2 0x26 // RF TX Power control
  360. #define RF_SYN_G3 0x27 // RF TX Power control
  361. #define RF_SYN_G4 0x28 // RF TX Power control
  362. #define RF_SYN_G5 0x29 // RF TX Power control
  363. #define RF_SYN_G6 0x2A // RF TX Power control
  364. #define RF_SYN_G7 0x2B // RF TX Power control
  365. #define RF_SYN_G8 0x2C // RF TX Power control
  366. #define RF_RCK_OS 0x30 // RF TX PA control
  367. #define RF_TXPA_G1 0x31 // RF TX PA control
  368. #define RF_TXPA_G2 0x32 // RF TX PA control
  369. #define RF_TXPA_G3 0x33 // RF TX PA control
  370. #define RF_TX_BIAS_A 0x35
  371. #define RF_TX_BIAS_D 0x36
  372. #define RF_LOBF_9 0x38
  373. #define RF_RXRF_A3 0x3C //
  374. #define RF_TRSW 0x3F
  375. #define RF_TXRF_A2 0x41
  376. #define RF_TXPA_G4 0x46
  377. #define RF_TXPA_A4 0x4B
  378. #define RF_0x52 0x52
  379. #define RF_WE_LUT 0xEF
  380. //
  381. //Bit Mask
  382. //
  383. // 1. Page1(0x100)
  384. #define bBBResetB 0x100 // Useless now?
  385. #define bGlobalResetB 0x200
  386. #define bOFDMTxStart 0x4
  387. #define bCCKTxStart 0x8
  388. #define bCRC32Debug 0x100
  389. #define bPMACLoopback 0x10
  390. #define bTxLSIG 0xffffff
  391. #define bOFDMTxRate 0xf
  392. #define bOFDMTxReserved 0x10
  393. #define bOFDMTxLength 0x1ffe0
  394. #define bOFDMTxParity 0x20000
  395. #define bTxHTSIG1 0xffffff
  396. #define bTxHTMCSRate 0x7f
  397. #define bTxHTBW 0x80
  398. #define bTxHTLength 0xffff00
  399. #define bTxHTSIG2 0xffffff
  400. #define bTxHTSmoothing 0x1
  401. #define bTxHTSounding 0x2
  402. #define bTxHTReserved 0x4
  403. #define bTxHTAggreation 0x8
  404. #define bTxHTSTBC 0x30
  405. #define bTxHTAdvanceCoding 0x40
  406. #define bTxHTShortGI 0x80
  407. #define bTxHTNumberHT_LTF 0x300
  408. #define bTxHTCRC8 0x3fc00
  409. #define bCounterReset 0x10000
  410. #define bNumOfOFDMTx 0xffff
  411. #define bNumOfCCKTx 0xffff0000
  412. #define bTxIdleInterval 0xffff
  413. #define bOFDMService 0xffff0000
  414. #define bTxMACHeader 0xffffffff
  415. #define bTxDataInit 0xff
  416. #define bTxHTMode 0x100
  417. #define bTxDataType 0x30000
  418. #define bTxRandomSeed 0xffffffff
  419. #define bCCKTxPreamble 0x1
  420. #define bCCKTxSFD 0xffff0000
  421. #define bCCKTxSIG 0xff
  422. #define bCCKTxService 0xff00
  423. #define bCCKLengthExt 0x8000
  424. #define bCCKTxLength 0xffff0000
  425. #define bCCKTxCRC16 0xffff
  426. #define bCCKTxStatus 0x1
  427. #define bOFDMTxStatus 0x2
  428. #define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff))
  429. // 2. Page8(0x800)
  430. #define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD
  431. #define bJapanMode 0x2
  432. #define bCCKTxSC 0x30
  433. #define bCCKEn 0x1000000
  434. #define bOFDMEn 0x2000000
  435. #define bOFDMRxADCPhase 0x10000 // Useless now
  436. #define bOFDMTxDACPhase 0x40000
  437. #define bXATxAGC 0x3f
  438. #define bAntennaSelect 0x0300
  439. #define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage
  440. #define bXCTxAGC 0xf000
  441. #define bXDTxAGC 0xf0000
  442. #define bPAStart 0xf0000000 // Useless now
  443. #define bTRStart 0x00f00000
  444. #define bRFStart 0x0000f000
  445. #define bBBStart 0x000000f0
  446. #define bBBCCKStart 0x0000000f
  447. #define bPAEnd 0xf //Reg0x814
  448. #define bTREnd 0x0f000000
  449. #define bRFEnd 0x000f0000
  450. #define bCCAMask 0x000000f0 //T2R
  451. #define bR2RCCAMask 0x00000f00
  452. #define bHSSI_R2TDelay 0xf8000000
  453. #define bHSSI_T2RDelay 0xf80000
  454. #define bContTxHSSI 0x400 //chane gain at continue Tx
  455. #define bIGFromCCK 0x200
  456. #define bAGCAddress 0x3f
  457. #define bRxHPTx 0x7000
  458. #define bRxHPT2R 0x38000
  459. #define bRxHPCCKIni 0xc0000
  460. #define bAGCTxCode 0xc00000
  461. #define bAGCRxCode 0x300000
  462. #define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1
  463. #define b3WireAddressLength 0x400
  464. #define b3WireRFPowerDown 0x1 // Useless now
  465. //#define bHWSISelect 0x8
  466. #define b5GPAPEPolarity 0x40000000
  467. #define b2GPAPEPolarity 0x80000000
  468. #define bRFSW_TxDefaultAnt 0x3
  469. #define bRFSW_TxOptionAnt 0x30
  470. #define bRFSW_RxDefaultAnt 0x300
  471. #define bRFSW_RxOptionAnt 0x3000
  472. #define bRFSI_3WireData 0x1
  473. #define bRFSI_3WireClock 0x2
  474. #define bRFSI_3WireLoad 0x4
  475. #define bRFSI_3WireRW 0x8
  476. #define bRFSI_3Wire 0xf
  477. #define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW
  478. #define bRFSI_TRSW 0x20 // Useless now
  479. #define bRFSI_TRSWB 0x40
  480. #define bRFSI_ANTSW 0x100
  481. #define bRFSI_ANTSWB 0x200
  482. #define bRFSI_PAPE 0x400
  483. #define bRFSI_PAPE5G 0x800
  484. #define bBandSelect 0x1
  485. #define bHTSIG2_GI 0x80
  486. #define bHTSIG2_Smoothing 0x01
  487. #define bHTSIG2_Sounding 0x02
  488. #define bHTSIG2_Aggreaton 0x08
  489. #define bHTSIG2_STBC 0x30
  490. #define bHTSIG2_AdvCoding 0x40
  491. #define bHTSIG2_NumOfHTLTF 0x300
  492. #define bHTSIG2_CRC8 0x3fc
  493. #define bHTSIG1_MCS 0x7f
  494. #define bHTSIG1_BandWidth 0x80
  495. #define bHTSIG1_HTLength 0xffff
  496. #define bLSIG_Rate 0xf
  497. #define bLSIG_Reserved 0x10
  498. #define bLSIG_Length 0x1fffe
  499. #define bLSIG_Parity 0x20
  500. #define bCCKRxPhase 0x4
  501. #define bLSSIReadAddress 0x7f800000 // T65 RF
  502. #define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal
  503. #define bLSSIReadBackData 0xfffff // T65 RF
  504. #define bLSSIReadOKFlag 0x1000 // Useless now
  505. #define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz
  506. #define bRegulator0Standby 0x1
  507. #define bRegulatorPLLStandby 0x2
  508. #define bRegulator1Standby 0x4
  509. #define bPLLPowerUp 0x8
  510. #define bDPLLPowerUp 0x10
  511. #define bDA10PowerUp 0x20
  512. #define bAD7PowerUp 0x200
  513. #define bDA6PowerUp 0x2000
  514. #define bXtalPowerUp 0x4000
  515. #define b40MDClkPowerUP 0x8000
  516. #define bDA6DebugMode 0x20000
  517. #define bDA6Swing 0x380000
  518. #define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ
  519. #define b80MClkDelay 0x18000000 // Useless
  520. #define bAFEWatchDogEnable 0x20000000
  521. #define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap
  522. #define bXtalCap23 0x3
  523. #define bXtalCap92x 0x0f000000
  524. #define bXtalCap 0x0f000000
  525. #define bIntDifClkEnable 0x400 // Useless
  526. #define bExtSigClkEnable 0x800
  527. #define bBandgapMbiasPowerUp 0x10000
  528. #define bAD11SHGain 0xc0000
  529. #define bAD11InputRange 0x700000
  530. #define bAD11OPCurrent 0x3800000
  531. #define bIPathLoopback 0x4000000
  532. #define bQPathLoopback 0x8000000
  533. #define bAFELoopback 0x10000000
  534. #define bDA10Swing 0x7e0
  535. #define bDA10Reverse 0x800
  536. #define bDAClkSource 0x1000
  537. #define bAD7InputRange 0x6000
  538. #define bAD7Gain 0x38000
  539. #define bAD7OutputCMMode 0x40000
  540. #define bAD7InputCMMode 0x380000
  541. #define bAD7Current 0xc00000
  542. #define bRegulatorAdjust 0x7000000
  543. #define bAD11PowerUpAtTx 0x1
  544. #define bDA10PSAtTx 0x10
  545. #define bAD11PowerUpAtRx 0x100
  546. #define bDA10PSAtRx 0x1000
  547. #define bCCKRxAGCFormat 0x200
  548. #define bPSDFFTSamplepPoint 0xc000
  549. #define bPSDAverageNum 0x3000
  550. #define bIQPathControl 0xc00
  551. #define bPSDFreq 0x3ff
  552. #define bPSDAntennaPath 0x30
  553. #define bPSDIQSwitch 0x40
  554. #define bPSDRxTrigger 0x400000
  555. #define bPSDTxTrigger 0x80000000
  556. #define bPSDSineToneScale 0x7f000000
  557. #define bPSDReport 0xffff
  558. // 3. Page9(0x900)
  559. #define bOFDMTxSC 0x30000000 // Useless
  560. #define bCCKTxOn 0x1
  561. #define bOFDMTxOn 0x2
  562. #define bDebugPage 0xfff //reset debug page and also HWord, LWord
  563. #define bDebugItem 0xff //reset debug page and LWord
  564. #define bAntL 0x10
  565. #define bAntNonHT 0x100
  566. #define bAntHT1 0x1000
  567. #define bAntHT2 0x10000
  568. #define bAntHT1S1 0x100000
  569. #define bAntNonHTS1 0x1000000
  570. // 4. PageA(0xA00)
  571. #define bCCKBBMode 0x3 // Useless
  572. #define bCCKTxPowerSaving 0x80
  573. #define bCCKRxPowerSaving 0x40
  574. #define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch
  575. #define bCCKScramble 0x8 // Useless
  576. #define bCCKAntDiversity 0x8000
  577. #define bCCKCarrierRecovery 0x4000
  578. #define bCCKTxRate 0x3000
  579. #define bCCKDCCancel 0x0800
  580. #define bCCKISICancel 0x0400
  581. #define bCCKMatchFilter 0x0200
  582. #define bCCKEqualizer 0x0100
  583. #define bCCKPreambleDetect 0x800000
  584. #define bCCKFastFalseCCA 0x400000
  585. #define bCCKChEstStart 0x300000
  586. #define bCCKCCACount 0x080000
  587. #define bCCKcs_lim 0x070000
  588. #define bCCKBistMode 0x80000000
  589. #define bCCKCCAMask 0x40000000
  590. #define bCCKTxDACPhase 0x4
  591. #define bCCKRxADCPhase 0x20000000 //r_rx_clk
  592. #define bCCKr_cp_mode0 0x0100
  593. #define bCCKTxDCOffset 0xf0
  594. #define bCCKRxDCOffset 0xf
  595. #define bCCKCCAMode 0xc000
  596. #define bCCKFalseCS_lim 0x3f00
  597. #define bCCKCS_ratio 0xc00000
  598. #define bCCKCorgBit_sel 0x300000
  599. #define bCCKPD_lim 0x0f0000
  600. #define bCCKNewCCA 0x80000000
  601. #define bCCKRxHPofIG 0x8000
  602. #define bCCKRxIG 0x7f00
  603. #define bCCKLNAPolarity 0x800000
  604. #define bCCKRx1stGain 0x7f0000
  605. #define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity
  606. #define bCCKRxAGCSatLevel 0x1f000000
  607. #define bCCKRxAGCSatCount 0xe0
  608. #define bCCKRxRFSettle 0x1f //AGCsamp_dly
  609. #define bCCKFixedRxAGC 0x8000
  610. //#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824
  611. #define bCCKAntennaPolarity 0x2000
  612. #define bCCKTxFilterType 0x0c00
  613. #define bCCKRxAGCReportType 0x0300
  614. #define bCCKRxDAGCEn 0x80000000
  615. #define bCCKRxDAGCPeriod 0x20000000
  616. #define bCCKRxDAGCSatLevel 0x1f000000
  617. #define bCCKTimingRecovery 0x800000
  618. #define bCCKTxC0 0x3f0000
  619. #define bCCKTxC1 0x3f000000
  620. #define bCCKTxC2 0x3f
  621. #define bCCKTxC3 0x3f00
  622. #define bCCKTxC4 0x3f0000
  623. #define bCCKTxC5 0x3f000000
  624. #define bCCKTxC6 0x3f
  625. #define bCCKTxC7 0x3f00
  626. #define bCCKDebugPort 0xff0000
  627. #define bCCKDACDebug 0x0f000000
  628. #define bCCKFalseAlarmEnable 0x8000
  629. #define bCCKFalseAlarmRead 0x4000
  630. #define bCCKTRSSI 0x7f
  631. #define bCCKRxAGCReport 0xfe
  632. #define bCCKRxReport_AntSel 0x80000000
  633. #define bCCKRxReport_MFOff 0x40000000
  634. #define bCCKRxRxReport_SQLoss 0x20000000
  635. #define bCCKRxReport_Pktloss 0x10000000
  636. #define bCCKRxReport_Lockedbit 0x08000000
  637. #define bCCKRxReport_RateError 0x04000000
  638. #define bCCKRxReport_RxRate 0x03000000
  639. #define bCCKRxFACounterLower 0xff
  640. #define bCCKRxFACounterUpper 0xff000000
  641. #define bCCKRxHPAGCStart 0xe000
  642. #define bCCKRxHPAGCFinal 0x1c00
  643. #define bCCKRxFalseAlarmEnable 0x8000
  644. #define bCCKFACounterFreeze 0x4000
  645. #define bCCKTxPathSel 0x10000000
  646. #define bCCKDefaultRxPath 0xc000000
  647. #define bCCKOptionRxPath 0x3000000
  648. // 5. PageC(0xC00)
  649. #define bNumOfSTF 0x3 // Useless
  650. #define bShift_L 0xc0
  651. #define bGI_TH 0xc
  652. #define bRxPathA 0x1
  653. #define bRxPathB 0x2
  654. #define bRxPathC 0x4
  655. #define bRxPathD 0x8
  656. #define bTxPathA 0x1
  657. #define bTxPathB 0x2
  658. #define bTxPathC 0x4
  659. #define bTxPathD 0x8
  660. #define bTRSSIFreq 0x200
  661. #define bADCBackoff 0x3000
  662. #define bDFIRBackoff 0xc000
  663. #define bTRSSILatchPhase 0x10000
  664. #define bRxIDCOffset 0xff
  665. #define bRxQDCOffset 0xff00
  666. #define bRxDFIRMode 0x1800000
  667. #define bRxDCNFType 0xe000000
  668. #define bRXIQImb_A 0x3ff
  669. #define bRXIQImb_B 0xfc00
  670. #define bRXIQImb_C 0x3f0000
  671. #define bRXIQImb_D 0xffc00000
  672. #define bDC_dc_Notch 0x60000
  673. #define bRxNBINotch 0x1f000000
  674. #define bPD_TH 0xf
  675. #define bPD_TH_Opt2 0xc000
  676. #define bPWED_TH 0x700
  677. #define bIfMF_Win_L 0x800
  678. #define bPD_Option 0x1000
  679. #define bMF_Win_L 0xe000
  680. #define bBW_Search_L 0x30000
  681. #define bwin_enh_L 0xc0000
  682. #define bBW_TH 0x700000
  683. #define bED_TH2 0x3800000
  684. #define bBW_option 0x4000000
  685. #define bRatio_TH 0x18000000
  686. #define bWindow_L 0xe0000000
  687. #define bSBD_Option 0x1
  688. #define bFrame_TH 0x1c
  689. #define bFS_Option 0x60
  690. #define bDC_Slope_check 0x80
  691. #define bFGuard_Counter_DC_L 0xe00
  692. #define bFrame_Weight_Short 0x7000
  693. #define bSub_Tune 0xe00000
  694. #define bFrame_DC_Length 0xe000000
  695. #define bSBD_start_offset 0x30000000
  696. #define bFrame_TH_2 0x7
  697. #define bFrame_GI2_TH 0x38
  698. #define bGI2_Sync_en 0x40
  699. #define bSarch_Short_Early 0x300
  700. #define bSarch_Short_Late 0xc00
  701. #define bSarch_GI2_Late 0x70000
  702. #define bCFOAntSum 0x1
  703. #define bCFOAcc 0x2
  704. #define bCFOStartOffset 0xc
  705. #define bCFOLookBack 0x70
  706. #define bCFOSumWeight 0x80
  707. #define bDAGCEnable 0x10000
  708. #define bTXIQImb_A 0x3ff
  709. #define bTXIQImb_B 0xfc00
  710. #define bTXIQImb_C 0x3f0000
  711. #define bTXIQImb_D 0xffc00000
  712. #define bTxIDCOffset 0xff
  713. #define bTxQDCOffset 0xff00
  714. #define bTxDFIRMode 0x10000
  715. #define bTxPesudoNoiseOn 0x4000000
  716. #define bTxPesudoNoise_A 0xff
  717. #define bTxPesudoNoise_B 0xff00
  718. #define bTxPesudoNoise_C 0xff0000
  719. #define bTxPesudoNoise_D 0xff000000
  720. #define bCCADropOption 0x20000
  721. #define bCCADropThres 0xfff00000
  722. #define bEDCCA_H 0xf
  723. #define bEDCCA_L 0xf0
  724. #define bLambda_ED 0x300
  725. #define bRxInitialGain 0x7f
  726. #define bRxAntDivEn 0x80
  727. #define bRxAGCAddressForLNA 0x7f00
  728. #define bRxHighPowerFlow 0x8000
  729. #define bRxAGCFreezeThres 0xc0000
  730. #define bRxFreezeStep_AGC1 0x300000
  731. #define bRxFreezeStep_AGC2 0xc00000
  732. #define bRxFreezeStep_AGC3 0x3000000
  733. #define bRxFreezeStep_AGC0 0xc000000
  734. #define bRxRssi_Cmp_En 0x10000000
  735. #define bRxQuickAGCEn 0x20000000
  736. #define bRxAGCFreezeThresMode 0x40000000
  737. #define bRxOverFlowCheckType 0x80000000
  738. #define bRxAGCShift 0x7f
  739. #define bTRSW_Tri_Only 0x80
  740. #define bPowerThres 0x300
  741. #define bRxAGCEn 0x1
  742. #define bRxAGCTogetherEn 0x2
  743. #define bRxAGCMin 0x4
  744. #define bRxHP_Ini 0x7
  745. #define bRxHP_TRLNA 0x70
  746. #define bRxHP_RSSI 0x700
  747. #define bRxHP_BBP1 0x7000
  748. #define bRxHP_BBP2 0x70000
  749. #define bRxHP_BBP3 0x700000
  750. #define bRSSI_H 0x7f0000 //the threshold for high power
  751. #define bRSSI_Gen 0x7f000000 //the threshold for ant diversity
  752. #define bRxSettle_TRSW 0x7
  753. #define bRxSettle_LNA 0x38
  754. #define bRxSettle_RSSI 0x1c0
  755. #define bRxSettle_BBP 0xe00
  756. #define bRxSettle_RxHP 0x7000
  757. #define bRxSettle_AntSW_RSSI 0x38000
  758. #define bRxSettle_AntSW 0xc0000
  759. #define bRxProcessTime_DAGC 0x300000
  760. #define bRxSettle_HSSI 0x400000
  761. #define bRxProcessTime_BBPPW 0x800000
  762. #define bRxAntennaPowerShift 0x3000000
  763. #define bRSSITableSelect 0xc000000
  764. #define bRxHP_Final 0x7000000
  765. #define bRxHTSettle_BBP 0x7
  766. #define bRxHTSettle_HSSI 0x8
  767. #define bRxHTSettle_RxHP 0x70
  768. #define bRxHTSettle_BBPPW 0x80
  769. #define bRxHTSettle_Idle 0x300
  770. #define bRxHTSettle_Reserved 0x1c00
  771. #define bRxHTRxHPEn 0x8000
  772. #define bRxHTAGCFreezeThres 0x30000
  773. #define bRxHTAGCTogetherEn 0x40000
  774. #define bRxHTAGCMin 0x80000
  775. #define bRxHTAGCEn 0x100000
  776. #define bRxHTDAGCEn 0x200000
  777. #define bRxHTRxHP_BBP 0x1c00000
  778. #define bRxHTRxHP_Final 0xe0000000
  779. #define bRxPWRatioTH 0x3
  780. #define bRxPWRatioEn 0x4
  781. #define bRxMFHold 0x3800
  782. #define bRxPD_Delay_TH1 0x38
  783. #define bRxPD_Delay_TH2 0x1c0
  784. #define bRxPD_DC_COUNT_MAX 0x600
  785. //#define bRxMF_Hold 0x3800
  786. #define bRxPD_Delay_TH 0x8000
  787. #define bRxProcess_Delay 0xf0000
  788. #define bRxSearchrange_GI2_Early 0x700000
  789. #define bRxFrame_Guard_Counter_L 0x3800000
  790. #define bRxSGI_Guard_L 0xc000000
  791. #define bRxSGI_Search_L 0x30000000
  792. #define bRxSGI_TH 0xc0000000
  793. #define bDFSCnt0 0xff
  794. #define bDFSCnt1 0xff00
  795. #define bDFSFlag 0xf0000
  796. #define bMFWeightSum 0x300000
  797. #define bMinIdxTH 0x7f000000
  798. #define bDAFormat 0x40000
  799. #define bTxChEmuEnable 0x01000000
  800. #define bTRSWIsolation_A 0x7f
  801. #define bTRSWIsolation_B 0x7f00
  802. #define bTRSWIsolation_C 0x7f0000
  803. #define bTRSWIsolation_D 0x7f000000
  804. #define bExtLNAGain 0x7c00
  805. // 6. PageE(0xE00)
  806. #define bSTBCEn 0x4 // Useless
  807. #define bAntennaMapping 0x10
  808. #define bNss 0x20
  809. #define bCFOAntSumD 0x200
  810. #define bPHYCounterReset 0x8000000
  811. #define bCFOReportGet 0x4000000
  812. #define bOFDMContinueTx 0x10000000
  813. #define bOFDMSingleCarrier 0x20000000
  814. #define bOFDMSingleTone 0x40000000
  815. //#define bRxPath1 0x01
  816. //#define bRxPath2 0x02
  817. //#define bRxPath3 0x04
  818. //#define bRxPath4 0x08
  819. //#define bTxPath1 0x10
  820. //#define bTxPath2 0x20
  821. #define bHTDetect 0x100
  822. #define bCFOEn 0x10000
  823. #define bCFOValue 0xfff00000
  824. #define bSigTone_Re 0x3f
  825. #define bSigTone_Im 0x7f00
  826. #define bCounter_CCA 0xffff
  827. #define bCounter_ParityFail 0xffff0000
  828. #define bCounter_RateIllegal 0xffff
  829. #define bCounter_CRC8Fail 0xffff0000
  830. #define bCounter_MCSNoSupport 0xffff
  831. #define bCounter_FastSync 0xffff
  832. #define bShortCFO 0xfff
  833. #define bShortCFOTLength 12 //total
  834. #define bShortCFOFLength 11 //fraction
  835. #define bLongCFO 0x7ff
  836. #define bLongCFOTLength 11
  837. #define bLongCFOFLength 11
  838. #define bTailCFO 0x1fff
  839. #define bTailCFOTLength 13
  840. #define bTailCFOFLength 12
  841. #define bmax_en_pwdB 0xffff
  842. #define bCC_power_dB 0xffff0000
  843. #define bnoise_pwdB 0xffff
  844. #define bPowerMeasTLength 10
  845. #define bPowerMeasFLength 3
  846. #define bRx_HT_BW 0x1
  847. #define bRxSC 0x6
  848. #define bRx_HT 0x8
  849. #define bNB_intf_det_on 0x1
  850. #define bIntf_win_len_cfg 0x30
  851. #define bNB_Intf_TH_cfg 0x1c0
  852. #define bRFGain 0x3f
  853. #define bTableSel 0x40
  854. #define bTRSW 0x80
  855. #define bRxSNR_A 0xff
  856. #define bRxSNR_B 0xff00
  857. #define bRxSNR_C 0xff0000
  858. #define bRxSNR_D 0xff000000
  859. #define bSNREVMTLength 8
  860. #define bSNREVMFLength 1
  861. #define bCSI1st 0xff
  862. #define bCSI2nd 0xff00
  863. #define bRxEVM1st 0xff0000
  864. #define bRxEVM2nd 0xff000000
  865. #define bSIGEVM 0xff
  866. #define bPWDB 0xff00
  867. #define bSGIEN 0x10000
  868. #define bSFactorQAM1 0xf // Useless
  869. #define bSFactorQAM2 0xf0
  870. #define bSFactorQAM3 0xf00
  871. #define bSFactorQAM4 0xf000
  872. #define bSFactorQAM5 0xf0000
  873. #define bSFactorQAM6 0xf0000
  874. #define bSFactorQAM7 0xf00000
  875. #define bSFactorQAM8 0xf000000
  876. #define bSFactorQAM9 0xf0000000
  877. #define bCSIScheme 0x100000
  878. #define bNoiseLvlTopSet 0x3 // Useless
  879. #define bChSmooth 0x4
  880. #define bChSmoothCfg1 0x38
  881. #define bChSmoothCfg2 0x1c0
  882. #define bChSmoothCfg3 0xe00
  883. #define bChSmoothCfg4 0x7000
  884. #define bMRCMode 0x800000
  885. #define bTHEVMCfg 0x7000000
  886. #define bLoopFitType 0x1 // Useless
  887. #define bUpdCFO 0x40
  888. #define bUpdCFOOffData 0x80
  889. #define bAdvUpdCFO 0x100
  890. #define bAdvTimeCtrl 0x800
  891. #define bUpdClko 0x1000
  892. #define bFC 0x6000
  893. #define bTrackingMode 0x8000
  894. #define bPhCmpEnable 0x10000
  895. #define bUpdClkoLTF 0x20000
  896. #define bComChCFO 0x40000
  897. #define bCSIEstiMode 0x80000
  898. #define bAdvUpdEqz 0x100000
  899. #define bUChCfg 0x7000000
  900. #define bUpdEqz 0x8000000
  901. //Rx Pseduo noise
  902. #define bRxPesudoNoiseOn 0x20000000 // Useless
  903. #define bRxPesudoNoise_A 0xff
  904. #define bRxPesudoNoise_B 0xff00
  905. #define bRxPesudoNoise_C 0xff0000
  906. #define bRxPesudoNoise_D 0xff000000
  907. #define bPesudoNoiseState_A 0xffff
  908. #define bPesudoNoiseState_B 0xffff0000
  909. #define bPesudoNoiseState_C 0xffff
  910. #define bPesudoNoiseState_D 0xffff0000
  911. //7. RF Register
  912. //Zebra1
  913. #define bZebra1_HSSIEnable 0x8 // Useless
  914. #define bZebra1_TRxControl 0xc00
  915. #define bZebra1_TRxGainSetting 0x07f
  916. #define bZebra1_RxCorner 0xc00
  917. #define bZebra1_TxChargePump 0x38
  918. #define bZebra1_RxChargePump 0x7
  919. #define bZebra1_ChannelNum 0xf80
  920. #define bZebra1_TxLPFBW 0x400
  921. #define bZebra1_RxLPFBW 0x600
  922. //Zebra4
  923. #define bRTL8256RegModeCtrl1 0x100 // Useless
  924. #define bRTL8256RegModeCtrl0 0x40
  925. #define bRTL8256_TxLPFBW 0x18
  926. #define bRTL8256_RxLPFBW 0x600
  927. //RTL8258
  928. #define bRTL8258_TxLPFBW 0xc // Useless
  929. #define bRTL8258_RxLPFBW 0xc00
  930. #define bRTL8258_RSSILPFBW 0xc0
  931. //
  932. // Other Definition
  933. //
  934. //byte endable for sb_write
  935. #define bByte0 0x1 // Useless
  936. #define bByte1 0x2
  937. #define bByte2 0x4
  938. #define bByte3 0x8
  939. #define bWord0 0x3
  940. #define bWord1 0xc
  941. #define bDWord 0xf
  942. //for PutRegsetting & GetRegSetting BitMask
  943. #define bMaskByte0 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f
  944. #define bMaskByte1 0xff00
  945. #define bMaskByte2 0xff0000
  946. #define bMaskByte3 0xff000000
  947. #define bMaskHWord 0xffff0000
  948. #define bMaskLWord 0x0000ffff
  949. #define bMaskDWord 0xffffffff
  950. #define bMask12Bits 0xfff
  951. #define bMaskH4Bits 0xf0000000
  952. #define bMaskOFDM_D 0xffc00000
  953. #define bMaskCCK 0x3f3f3f3f
  954. #define bEnable 0x1 // Useless
  955. #define bDisable 0x0
  956. #define LeftAntenna 0x0 // Useless
  957. #define RightAntenna 0x1
  958. #define tCheckTxStatus 500 //500ms // Useless
  959. #define tUpdateRxCounter 100 //100ms
  960. #define rateCCK 0 // Useless
  961. #define rateOFDM 1
  962. #define rateHT 2
  963. //define Register-End
  964. #define bPMAC_End 0x1ff // Useless
  965. #define bFPGAPHY0_End 0x8ff
  966. #define bFPGAPHY1_End 0x9ff
  967. #define bCCKPHY0_End 0xaff
  968. #define bOFDMPHY0_End 0xcff
  969. #define bOFDMPHY1_End 0xdff
  970. //define max debug item in each debug page
  971. //#define bMaxItem_FPGA_PHY0 0x9
  972. //#define bMaxItem_FPGA_PHY1 0x3
  973. //#define bMaxItem_PHY_11B 0x16
  974. //#define bMaxItem_OFDM_PHY0 0x29
  975. //#define bMaxItem_OFDM_PHY1 0x0
  976. #define bPMACControl 0x0 // Useless
  977. #define bWMACControl 0x1
  978. #define bWNICControl 0x2
  979. #define PathA 0x0 // Useless
  980. #define PathB 0x1
  981. #define PathC 0x2
  982. #define PathD 0x3
  983. /*--------------------------Define Parameters-------------------------------*/
  984. #endif