rtl8723b_xmit.h 4.6 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. *
  19. ******************************************************************************/
  20. #ifndef __RTL8723B_XMIT_H__
  21. #define __RTL8723B_XMIT_H__
  22. //
  23. // Queue Select Value in TxDesc
  24. //
  25. #define QSLT_BK 0x2//0x01
  26. #define QSLT_BE 0x0
  27. #define QSLT_VI 0x5//0x4
  28. #define QSLT_VO 0x7//0x6
  29. #define QSLT_BEACON 0x10
  30. #define QSLT_HIGH 0x11
  31. #define QSLT_MGNT 0x12
  32. #define QSLT_CMD 0x13
  33. #define MAX_TID (15)
  34. //OFFSET 0
  35. #define OFFSET_SZ 0
  36. #define OFFSET_SHT 16
  37. #define BMC BIT(24)
  38. #define LSG BIT(26)
  39. #define FSG BIT(27)
  40. #define OWN BIT(31)
  41. //OFFSET 4
  42. #define PKT_OFFSET_SZ 0
  43. #define BK BIT(6)
  44. #define QSEL_SHT 8
  45. #define Rate_ID_SHT 16
  46. #define NAVUSEHDR BIT(20)
  47. #define PKT_OFFSET_SHT 26
  48. #define HWPC BIT(31)
  49. //OFFSET 8
  50. #define AGG_EN BIT(29)
  51. //OFFSET 12
  52. #define SEQ_SHT 16
  53. //OFFSET 16
  54. #define QoS BIT(6)
  55. #define HW_SEQ_EN BIT(7)
  56. #define USERATE BIT(8)
  57. #define DISDATAFB BIT(10)
  58. #define DATA_SHORT BIT(24)
  59. #define DATA_BW BIT(25)
  60. //OFFSET 20
  61. #define SGI BIT(6)
  62. //
  63. //defined for TX DESC Operation
  64. //
  65. typedef struct txdesc_8723b
  66. {
  67. //0
  68. u32 pktlen:16;
  69. u32 offset:8;
  70. u32 bmc:1;
  71. u32 htc:1;
  72. u32 ls:1;
  73. u32 fs:1;
  74. u32 linip:1;
  75. u32 noacm:1;
  76. u32 gf:1;
  77. u32 own:1;
  78. //4//4
  79. u32 macid:7;
  80. u32 rsvd0406:1;
  81. u32 qsel:5;
  82. u32 rd_nav_ext:1;
  83. u32 lsig_txop_en:1;
  84. u32 pifs:1;
  85. u32 rate_id:5;
  86. u32 en_desc_id:1;
  87. u32 sectype:2;
  88. u32 pkt_offset:5; // unit: 8 bytes
  89. u32 rsvd0431:3;
  90. //8
  91. u32 p_aid:9;
  92. u32 rsvd0809:1;
  93. u32 cca_rts:2;
  94. u32 agg_en:1;
  95. u32 rd_en:1;
  96. u32 null_0:1;
  97. u32 null_1:1;
  98. u32 bk:1;
  99. u32 morefrag:1;
  100. u32 raw:1;
  101. u32 sep_rpt:1;
  102. u32 ampdu_density:3;
  103. u32 bt_null:1;
  104. u32 gid:6;
  105. u32 rsvd0830:2;
  106. //12
  107. u32 wheader_len:4;
  108. u32 chk_en:1;
  109. u32 early_rate:1;
  110. u32 hwseq_sel:2;
  111. u32 userate:1;
  112. u32 disrtsfb:1;
  113. u32 disdatafb:1;
  114. u32 cts2self:1;
  115. u32 rtsen:1;
  116. u32 hw_rts_en:1;
  117. u32 port_id:1;
  118. u32 navusehdr:1;
  119. u32 use_max_len:1;
  120. u32 max_agg_num:5;
  121. u32 ndpa:2;
  122. u32 ampdu_max_time:8;
  123. //16
  124. u32 datarate:7;
  125. u32 try_rate:1;
  126. u32 data_ratefb_lmt:5;
  127. u32 rts_ratefb_lmt:4;
  128. u32 rty_lmt_en:1;
  129. u32 data_rt_lmt:6;
  130. u32 rtsrate:5;
  131. u32 pcts_en:1;
  132. u32 pcts_mask_idx:2;
  133. //20
  134. u32 data_sc:4;
  135. u32 data_short:1;
  136. u32 data_bw:2;
  137. u32 data_ldpc:1;
  138. u32 data_stbc:2;
  139. u32 vcs_stbc:2;
  140. u32 rts_short:1;
  141. u32 rts_sc:4;
  142. u32 rsvd2023:7;
  143. u32 tx_antl:4;
  144. u32 txpwr_ofset:3;
  145. u32 rsvd2031:1;
  146. //24
  147. u32 sw_def:12;
  148. u32 rsvd2412:4;
  149. u32 ant_sel_a:3;
  150. u32 ant_sel_b:3;
  151. u32 ant_sel_c:3;
  152. u32 ant_sel_d:3;
  153. u32 rsvd2428:4;
  154. //28
  155. u32 checksum:16;
  156. u32 rsvd2816:8;
  157. u32 usb_txagg_num:8;
  158. //32
  159. u32 rts_rc:6;
  160. u32 bar_rty_th:2;
  161. u32 data_rc:6;
  162. u32 rsvd3214:1;
  163. u32 hwseq_en:1;
  164. u32 nextheadpage:8;
  165. u32 tailpage:8;
  166. //36
  167. u32 padding_len:11;
  168. u32 txbf_path:1;
  169. u32 seq:12;
  170. u32 final_data_rate:8;
  171. }TXDESC_8723B, *PTXDESC_8723B;
  172. void rtl8723b_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);
  173. void rtl8723b_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 type, u8 IsBTQosNull);
  174. #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
  175. s32 rtl8723bs_init_xmit_priv(PADAPTER padapter);
  176. void rtl8723bs_free_xmit_priv(PADAPTER padapter);
  177. s32 rtl8723bs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
  178. s32 rtl8723bs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
  179. s32 rtl8723bs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
  180. s32 rtl8723bs_xmit_buf_handler(PADAPTER padapter);
  181. thread_return rtl8723bs_xmit_thread(thread_context context);
  182. #define hal_xmit_handler rtl8723bs_xmit_buf_handler
  183. #endif
  184. #ifdef CONFIG_USB_HCI
  185. s32 rtl8723bu_xmit_buf_handler(PADAPTER padapter);
  186. #define hal_xmit_handler rtl8723bu_xmit_buf_handler
  187. #endif
  188. #endif