hal_mcc.c 108 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2015 - 2017 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. *****************************************************************************/
  15. #ifdef CONFIG_MCC_MODE
  16. #define _HAL_MCC_C_
  17. #include <drv_types.h> /* PADAPTER */
  18. #include <rtw_mcc.h> /* mcc structure */
  19. #include <hal_data.h> /* HAL_DATA */
  20. #include <rtw_pwrctrl.h> /* power control */
  21. /* use for AP/GO + STA/GC case */
  22. #define MCC_DURATION_IDX 0 /* druration for station side */
  23. #define MCC_TSF_SYNC_OFFSET_IDX 1
  24. #define MCC_START_TIME_OFFSET_IDX 2
  25. #define MCC_INTERVAL_IDX 3
  26. #define MCC_GUARD_OFFSET0_IDX 4
  27. #define MCC_GUARD_OFFSET1_IDX 5
  28. #define MCC_STOP_THRESHOLD 6
  29. #define TU 1024 /* 1 TU equals 1024 microseconds */
  30. /* druration, TSF sync offset, start time offset, interval (unit:TU (1024 microseconds))*/
  31. u8 mcc_switch_channel_policy_table[][7]={
  32. {20, 50, 40, 100, 0, 0, 30},
  33. {80, 50, 10, 100, 0, 0, 30},
  34. {36, 50, 32, 100, 0, 0, 30},
  35. {30, 50, 35, 100, 0, 0, 30},
  36. };
  37. const int mcc_max_policy_num = sizeof(mcc_switch_channel_policy_table) /sizeof(u8) /7;
  38. static void dump_iqk_val_table(PADAPTER padapter)
  39. {
  40. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
  41. struct hal_iqk_reg_backup *iqk_reg_backup = pHalData->iqk_reg_backup;
  42. u8 total_rf_path = pHalData->NumTotalRFPath;
  43. u8 rf_path_idx = 0;
  44. u8 backup_chan_idx = 0;
  45. u8 backup_reg_idx = 0;
  46. #ifdef CONFIG_MCC_MODE_V2
  47. #else
  48. RTW_INFO("=============dump IQK backup table================\n");
  49. for (backup_chan_idx = 0; backup_chan_idx < MAX_IQK_INFO_BACKUP_CHNL_NUM; backup_chan_idx++) {
  50. for (rf_path_idx = 0; rf_path_idx < total_rf_path; rf_path_idx++) {
  51. for(backup_reg_idx = 0; backup_reg_idx < MAX_IQK_INFO_BACKUP_REG_NUM; backup_reg_idx++) {
  52. RTW_INFO("ch:%d. bw:%d. rf path:%d. reg[%d] = 0x%02x \n"
  53. , iqk_reg_backup[backup_chan_idx].central_chnl
  54. , iqk_reg_backup[backup_chan_idx].bw_mode
  55. , rf_path_idx
  56. , backup_reg_idx
  57. , iqk_reg_backup[backup_chan_idx].reg_backup[rf_path_idx][backup_reg_idx]
  58. );
  59. }
  60. }
  61. }
  62. RTW_INFO("=============================================\n");
  63. #endif
  64. }
  65. static void rtw_hal_mcc_build_p2p_noa_attr(PADAPTER padapter, u8 *ie, u32 *ie_len)
  66. {
  67. struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
  68. struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
  69. struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
  70. u8 p2p_noa_attr_ie[MAX_P2P_IE_LEN] = {0x00};
  71. u32 p2p_noa_attr_len = 0;
  72. u8 noa_desc_num = 1;
  73. u8 opp_ps = 0; /* Disable OppPS */
  74. u8 noa_count = 255;
  75. u32 noa_duration;
  76. u32 noa_interval;
  77. u8 noa_index = 0;
  78. u8 mcc_policy_idx = 0;
  79. mcc_policy_idx = pmccobjpriv->policy_index;
  80. noa_duration = mcc_switch_channel_policy_table[mcc_policy_idx][MCC_DURATION_IDX] * TU;
  81. noa_interval = mcc_switch_channel_policy_table[mcc_policy_idx][MCC_INTERVAL_IDX] * TU;
  82. /* P2P OUI(4 bytes) */
  83. _rtw_memcpy(p2p_noa_attr_ie, P2P_OUI, 4);
  84. p2p_noa_attr_len = p2p_noa_attr_len + 4;
  85. /* attrute ID(1 byte) */
  86. p2p_noa_attr_ie[p2p_noa_attr_len] = P2P_ATTR_NOA;
  87. p2p_noa_attr_len = p2p_noa_attr_len + 1;
  88. /* attrute length(2 bytes) length = noa_desc_num*13 + 2 */
  89. RTW_PUT_LE16(p2p_noa_attr_ie + p2p_noa_attr_len, (noa_desc_num * 13 + 2));
  90. p2p_noa_attr_len = p2p_noa_attr_len + 2;
  91. /* Index (1 byte) */
  92. p2p_noa_attr_ie[p2p_noa_attr_len] = noa_index;
  93. p2p_noa_attr_len = p2p_noa_attr_len + 1;
  94. /* CTWindow and OppPS Parameters (1 byte) */
  95. p2p_noa_attr_ie[p2p_noa_attr_len] = opp_ps;
  96. p2p_noa_attr_len = p2p_noa_attr_len+ 1;
  97. /* NoA Count (1 byte) */
  98. p2p_noa_attr_ie[p2p_noa_attr_len] = noa_count;
  99. p2p_noa_attr_len = p2p_noa_attr_len + 1;
  100. /* NoA Duration (4 bytes) unit: microseconds */
  101. RTW_PUT_LE32(p2p_noa_attr_ie + p2p_noa_attr_len, noa_duration);
  102. p2p_noa_attr_len = p2p_noa_attr_len + 4;
  103. /* NoA Interval (4 bytes) unit: microseconds */
  104. RTW_PUT_LE32(p2p_noa_attr_ie + p2p_noa_attr_len, noa_interval);
  105. p2p_noa_attr_len = p2p_noa_attr_len + 4;
  106. /* NoA Start Time (4 bytes) unit: microseconds */
  107. RTW_PUT_LE32(p2p_noa_attr_ie + p2p_noa_attr_len, pmccadapriv->noa_start_time);
  108. if (0)
  109. RTW_INFO("indxe:%d, start_time=0x%02x:0x%02x:0x%02x:0x%02x\n"
  110. , noa_index
  111. , p2p_noa_attr_ie[p2p_noa_attr_len]
  112. , p2p_noa_attr_ie[p2p_noa_attr_len + 1]
  113. , p2p_noa_attr_ie[p2p_noa_attr_len + 2]
  114. , p2p_noa_attr_ie[p2p_noa_attr_len + 3]);
  115. p2p_noa_attr_len = p2p_noa_attr_len + 4;
  116. rtw_set_ie(ie, _VENDOR_SPECIFIC_IE_, p2p_noa_attr_len, (u8 *)p2p_noa_attr_ie, ie_len);
  117. }
  118. /**
  119. * rtw_hal_mcc_update_go_p2p_ie - update go p2p ie(add NoA attribute)
  120. * @padapter: the adapter to be update go p2p ie
  121. */
  122. static void rtw_hal_mcc_update_go_p2p_ie(PADAPTER padapter)
  123. {
  124. struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
  125. struct mcc_obj_priv *mccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
  126. u8 *pos = NULL;
  127. /* no noa attribute, build it */
  128. if (pmccadapriv->p2p_go_noa_ie_len == 0)
  129. rtw_hal_mcc_build_p2p_noa_attr(padapter, pmccadapriv->p2p_go_noa_ie, &pmccadapriv->p2p_go_noa_ie_len);
  130. else {
  131. /* has noa attribut, modify it */
  132. u32 noa_duration = 0;
  133. /* update index */
  134. pos = pmccadapriv->p2p_go_noa_ie + pmccadapriv->p2p_go_noa_ie_len - 15;
  135. /* 0~255 */
  136. (*pos) = ((*pos) + 1) % 256;
  137. if (0)
  138. RTW_INFO("indxe:%d\n", (*pos));
  139. /* update duration */
  140. noa_duration = mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_DURATION_IDX] * TU;
  141. pos = pmccadapriv->p2p_go_noa_ie + pmccadapriv->p2p_go_noa_ie_len - 12;
  142. RTW_PUT_LE32(pos, noa_duration);
  143. /* update start time */
  144. pos = pmccadapriv->p2p_go_noa_ie + pmccadapriv->p2p_go_noa_ie_len - 4;
  145. RTW_PUT_LE32(pos, pmccadapriv->noa_start_time);
  146. if (0)
  147. RTW_INFO("start_time=0x%02x:0x%02x:0x%02x:0x%02x\n"
  148. , ((u8*)(pos))[0]
  149. , ((u8*)(pos))[1]
  150. , ((u8*)(pos))[2]
  151. , ((u8*)(pos))[3]);
  152. }
  153. if (0) {
  154. RTW_INFO("p2p_go_noa_ie_len:%d\n", pmccadapriv->p2p_go_noa_ie_len);
  155. RTW_INFO_DUMP("\n", pmccadapriv->p2p_go_noa_ie, pmccadapriv->p2p_go_noa_ie_len);
  156. }
  157. update_beacon(padapter, _VENDOR_SPECIFIC_IE_, P2P_OUI, _TRUE);
  158. }
  159. /**
  160. * rtw_hal_mcc_remove_go_p2p_ie - remove go p2p ie(add NoA attribute)
  161. * @padapter: the adapter to be update go p2p ie
  162. */
  163. static void rtw_hal_mcc_remove_go_p2p_ie(PADAPTER padapter)
  164. {
  165. struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
  166. struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
  167. /* chech has noa ie or not */
  168. if (pmccadapriv->p2p_go_noa_ie_len == 0)
  169. return;
  170. pmccadapriv->p2p_go_noa_ie_len = 0;
  171. update_beacon(padapter, _VENDOR_SPECIFIC_IE_, P2P_OUI, _TRUE);
  172. }
  173. /* restore IQK value for all interface */
  174. void rtw_hal_mcc_restore_iqk_val(PADAPTER padapter)
  175. {
  176. u8 take_care_iqk = _FALSE;
  177. struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
  178. _adapter *iface = NULL;
  179. struct mcc_adapter_priv *mccadapriv = NULL;
  180. u8 i = 0;
  181. rtw_hal_get_hwreg(padapter, HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO, &take_care_iqk);
  182. if (take_care_iqk == _TRUE && MCC_EN(padapter)) {
  183. for (i = 0; i < dvobj->iface_nums; i++) {
  184. iface = dvobj->padapters[i];
  185. if (iface == NULL)
  186. continue;
  187. mccadapriv = &iface->mcc_adapterpriv;
  188. if (mccadapriv->role == MCC_ROLE_MAX)
  189. continue;
  190. rtw_hal_ch_sw_iqk_info_restore(iface, CH_SW_USE_CASE_MCC);
  191. }
  192. }
  193. if (0)
  194. dump_iqk_val_table(padapter);
  195. }
  196. u8 rtw_hal_check_mcc_status(PADAPTER padapter, u8 mcc_status)
  197. {
  198. struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
  199. if (pmccobjpriv->mcc_status & (mcc_status))
  200. return _TRUE;
  201. else
  202. return _FALSE;
  203. }
  204. void rtw_hal_set_mcc_status(PADAPTER padapter, u8 mcc_status)
  205. {
  206. struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
  207. pmccobjpriv->mcc_status |= (mcc_status);
  208. }
  209. void rtw_hal_clear_mcc_status(PADAPTER padapter, u8 mcc_status)
  210. {
  211. struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
  212. pmccobjpriv->mcc_status &= (~mcc_status);
  213. }
  214. static void rtw_hal_mcc_update_policy_table(PADAPTER adapter)
  215. {
  216. struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
  217. struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
  218. u8 mcc_duration = mccobjpriv->duration;
  219. s8 mcc_policy_idx = mccobjpriv->policy_index;
  220. u8 interval = mcc_switch_channel_policy_table[mcc_policy_idx][MCC_INTERVAL_IDX];
  221. u8 new_mcc_duration_time = 0;
  222. u8 new_starttime_offset = 0;
  223. /* convert % to ms */
  224. new_mcc_duration_time = mcc_duration * interval / 100;
  225. /* start time offset = (interval - duration time)/2 */
  226. new_starttime_offset = (interval - new_mcc_duration_time) >> 1;
  227. /* update modified parameters */
  228. mcc_switch_channel_policy_table[mcc_policy_idx][MCC_DURATION_IDX]
  229. = new_mcc_duration_time;
  230. mcc_switch_channel_policy_table[mcc_policy_idx][MCC_START_TIME_OFFSET_IDX]
  231. = new_starttime_offset;
  232. }
  233. static void rtw_hal_config_mcc_switch_channel_setting(PADAPTER padapter)
  234. {
  235. struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
  236. struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
  237. struct registry_priv *registry_par = &padapter->registrypriv;
  238. u8 mcc_duration = 0;
  239. s8 mcc_policy_idx = 0;
  240. mcc_policy_idx = registry_par->rtw_mcc_policy_table_idx;
  241. mcc_duration = mccobjpriv->duration;
  242. if (mcc_policy_idx < 0 || mcc_policy_idx >= mcc_max_policy_num) {
  243. mccobjpriv->policy_index = 0;
  244. RTW_INFO("[MCC] can't find table(%d), use default policy(%d)\n",
  245. mcc_policy_idx, mccobjpriv->policy_index);
  246. } else
  247. mccobjpriv->policy_index = mcc_policy_idx;
  248. /* convert % to time */
  249. if (mcc_duration != 0)
  250. rtw_hal_mcc_update_policy_table(padapter);
  251. RTW_INFO("[MCC] policy(%d): %d,%d,%d,%d,%d,%d\n"
  252. , mccobjpriv->policy_index
  253. , mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_DURATION_IDX]
  254. , mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_TSF_SYNC_OFFSET_IDX]
  255. , mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_START_TIME_OFFSET_IDX]
  256. , mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_INTERVAL_IDX]
  257. , mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_GUARD_OFFSET0_IDX]
  258. , mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_GUARD_OFFSET1_IDX]);
  259. }
  260. static void rtw_hal_mcc_assign_tx_threshold(PADAPTER padapter)
  261. {
  262. struct registry_priv *preg = &padapter->registrypriv;
  263. struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
  264. struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
  265. switch (pmccadapriv->role) {
  266. case MCC_ROLE_STA:
  267. case MCC_ROLE_GC:
  268. switch (pmlmeext->cur_bwmode) {
  269. case CHANNEL_WIDTH_20:
  270. /*
  271. * target tx byte(bytes) = target tx tp(Mbits/sec) * 1024 * 1024 / 8 * (duration(ms) / 1024)
  272. * = target tx tp(Mbits/sec) * 128 * duration(ms)
  273. * note:
  274. * target tx tp(Mbits/sec) * 1024 * 1024 / 8 ==> Mbits to bytes
  275. * duration(ms) / 1024 ==> msec to sec
  276. */
  277. pmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_sta_bw20_target_tx_tp * 128 * pmccadapriv->mcc_duration;
  278. break;
  279. case CHANNEL_WIDTH_40:
  280. pmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_sta_bw40_target_tx_tp * 128 * pmccadapriv->mcc_duration;
  281. break;
  282. case CHANNEL_WIDTH_80:
  283. pmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_sta_bw80_target_tx_tp * 128 * pmccadapriv->mcc_duration;
  284. break;
  285. case CHANNEL_WIDTH_160:
  286. case CHANNEL_WIDTH_80_80:
  287. RTW_INFO(FUNC_ADPT_FMT": not support bwmode = %d\n"
  288. , FUNC_ADPT_ARG(padapter), pmlmeext->cur_bwmode);
  289. break;
  290. }
  291. break;
  292. case MCC_ROLE_AP:
  293. case MCC_ROLE_GO:
  294. switch (pmlmeext->cur_bwmode) {
  295. case CHANNEL_WIDTH_20:
  296. pmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_ap_bw20_target_tx_tp * 128 * pmccadapriv->mcc_duration;
  297. break;
  298. case CHANNEL_WIDTH_40:
  299. pmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_ap_bw40_target_tx_tp * 128 * pmccadapriv->mcc_duration;
  300. break;
  301. case CHANNEL_WIDTH_80:
  302. pmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_ap_bw80_target_tx_tp * 128 * pmccadapriv->mcc_duration;
  303. break;
  304. case CHANNEL_WIDTH_160:
  305. case CHANNEL_WIDTH_80_80:
  306. RTW_INFO(FUNC_ADPT_FMT": not support bwmode = %d\n"
  307. , FUNC_ADPT_ARG(padapter), pmlmeext->cur_bwmode);
  308. break;
  309. }
  310. break;
  311. default:
  312. RTW_INFO(FUNC_ADPT_FMT": unknown role = %d\n"
  313. , FUNC_ADPT_ARG(padapter), pmccadapriv->role);
  314. break;
  315. }
  316. }
  317. static void rtw_hal_config_mcc_role_setting(PADAPTER padapter, u8 order)
  318. {
  319. struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
  320. struct mcc_obj_priv *pmccobjpriv = &(pdvobjpriv->mcc_objpriv);
  321. struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
  322. struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
  323. struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
  324. struct wlan_network *cur_network = &(pmlmepriv->cur_network);
  325. struct sta_priv *pstapriv = &padapter->stapriv;
  326. struct sta_info *psta = NULL;
  327. struct registry_priv *preg = &padapter->registrypriv;
  328. _irqL irqL;
  329. _list *phead =NULL, *plist = NULL;
  330. u8 policy_index = 0;
  331. u8 mcc_duration = 0;
  332. u8 mcc_interval = 0;
  333. u8 starting_ap_num = DEV_AP_STARTING_NUM(pdvobjpriv);
  334. u8 ap_num = DEV_AP_NUM(pdvobjpriv);
  335. policy_index = pmccobjpriv->policy_index;
  336. mcc_duration = mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_DURATION_IDX]
  337. - mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_GUARD_OFFSET0_IDX]
  338. - mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_GUARD_OFFSET1_IDX];
  339. mcc_interval = mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_INTERVAL_IDX];
  340. if (starting_ap_num == 0 && ap_num == 0) {
  341. pmccadapriv->order = order;
  342. if (pmccadapriv->order == 0) {
  343. /* setting is smiliar to GO/AP */
  344. /* pmccadapriv->mcc_duration = mcc_interval - mcc_duration;*/
  345. pmccadapriv->mgmt_queue_macid = MCC_ROLE_SOFTAP_GO_MGMT_QUEUE_MACID;
  346. } else if (pmccadapriv->order == 1) {
  347. /* pmccadapriv->mcc_duration = mcc_duration; */
  348. pmccadapriv->mgmt_queue_macid = MCC_ROLE_STA_GC_MGMT_QUEUE_MACID;
  349. } else {
  350. RTW_INFO("[MCC] not support >= 3 interface\n");
  351. rtw_warn_on(1);
  352. }
  353. rtw_hal_mcc_assign_tx_threshold(padapter);
  354. psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress);
  355. if (psta) {
  356. /* combine AP/GO macid and mgmt queue macid to bitmap */
  357. pmccadapriv->mcc_macid_bitmap = BIT(psta->cmn.mac_id) | BIT(pmccadapriv->mgmt_queue_macid);
  358. } else {
  359. RTW_INFO(FUNC_ADPT_FMT":AP/GO station info is NULL\n", FUNC_ADPT_ARG(padapter));
  360. rtw_warn_on(1);
  361. }
  362. } else {
  363. /* GO/AP is 1nd order GC/STA is 2nd order */
  364. switch (pmccadapriv->role) {
  365. case MCC_ROLE_STA:
  366. case MCC_ROLE_GC:
  367. pmccadapriv->order = 1;
  368. pmccadapriv->mcc_duration = mcc_duration;
  369. rtw_hal_mcc_assign_tx_threshold(padapter);
  370. /* assign used mac to avoid affecting RA */
  371. pmccadapriv->mgmt_queue_macid = MCC_ROLE_STA_GC_MGMT_QUEUE_MACID;
  372. psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress);
  373. if (psta) {
  374. /* combine AP/GO macid and mgmt queue macid to bitmap */
  375. pmccadapriv->mcc_macid_bitmap = BIT(psta->cmn.mac_id) | BIT(pmccadapriv->mgmt_queue_macid);
  376. } else {
  377. RTW_INFO(FUNC_ADPT_FMT":AP/GO station info is NULL\n", FUNC_ADPT_ARG(padapter));
  378. rtw_warn_on(1);
  379. }
  380. break;
  381. case MCC_ROLE_AP:
  382. case MCC_ROLE_GO:
  383. pmccadapriv->order = 0;
  384. /* total druation value equals interval */
  385. pmccadapriv->mcc_duration = mcc_interval - mcc_duration;
  386. pmccadapriv->p2p_go_noa_ie_len = 0; /* not NoA attribute at init time */
  387. rtw_hal_mcc_assign_tx_threshold(padapter);
  388. _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
  389. phead = &pstapriv->asoc_list;
  390. plist = get_next(phead);
  391. pmccadapriv->mcc_macid_bitmap = 0;
  392. while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
  393. psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
  394. plist = get_next(plist);
  395. pmccadapriv->mcc_macid_bitmap |= BIT(psta->cmn.mac_id);
  396. }
  397. _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
  398. psta = rtw_get_bcmc_stainfo(padapter);
  399. if (psta != NULL)
  400. pmccadapriv->mgmt_queue_macid = psta->cmn.mac_id;
  401. else {
  402. pmccadapriv->mgmt_queue_macid = MCC_ROLE_SOFTAP_GO_MGMT_QUEUE_MACID;
  403. RTW_INFO(FUNC_ADPT_FMT":bcmc station is NULL, use macid %d\n"
  404. , FUNC_ADPT_ARG(padapter), pmccadapriv->mgmt_queue_macid);
  405. }
  406. /* combine client macid and mgmt queue macid to bitmap */
  407. pmccadapriv->mcc_macid_bitmap |= BIT(pmccadapriv->mgmt_queue_macid);
  408. break;
  409. default:
  410. RTW_INFO("Unknown role\n");
  411. rtw_warn_on(1);
  412. break;
  413. }
  414. }
  415. /* setting Null data parameters */
  416. if (pmccadapriv->role == MCC_ROLE_STA) {
  417. pmccadapriv->null_early = 3;
  418. pmccadapriv->null_rty_num= 5;
  419. } else if (pmccadapriv->role == MCC_ROLE_GC) {
  420. pmccadapriv->null_early = 2;
  421. pmccadapriv->null_rty_num= 5;
  422. } else {
  423. pmccadapriv->null_early = 0;
  424. pmccadapriv->null_rty_num= 0;
  425. }
  426. RTW_INFO("********* "FUNC_ADPT_FMT" *********\n", FUNC_ADPT_ARG(padapter));
  427. RTW_INFO("order:%d\n", pmccadapriv->order);
  428. RTW_INFO("role:%d\n", pmccadapriv->role);
  429. RTW_INFO("mcc duration:%d\n", pmccadapriv->mcc_duration);
  430. RTW_INFO("null_early:%d\n", pmccadapriv->null_early);
  431. RTW_INFO("null_rty_num:%d\n", pmccadapriv->null_rty_num);
  432. RTW_INFO("mgmt queue macid:%d\n", pmccadapriv->mgmt_queue_macid);
  433. RTW_INFO("bitmap:0x%02x\n", pmccadapriv->mcc_macid_bitmap);
  434. RTW_INFO("target tx bytes:%d\n", pmccadapriv->mcc_target_tx_bytes_to_port);
  435. RTW_INFO("**********************************\n");
  436. pmccobjpriv->iface[pmccadapriv->order] = padapter;
  437. }
  438. static void rtw_hal_clear_mcc_macid(PADAPTER padapter)
  439. {
  440. u16 media_status_rpt;
  441. struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
  442. switch (pmccadapriv->role) {
  443. case MCC_ROLE_STA:
  444. case MCC_ROLE_GC:
  445. break;
  446. case MCC_ROLE_AP:
  447. case MCC_ROLE_GO:
  448. /* nothing to do */
  449. break;
  450. default:
  451. RTW_INFO("Unknown role\n");
  452. rtw_warn_on(1);
  453. break;
  454. }
  455. }
  456. static void rtw_hal_mcc_rqt_tsf(PADAPTER padapter, u64 *out_tsf)
  457. {
  458. struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
  459. struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
  460. PADAPTER order0_iface = NULL;
  461. PADAPTER order1_iface = NULL;
  462. struct submit_ctx *tsf_req_sctx = NULL;
  463. enum _hw_port tsfx = MAX_HW_PORT;
  464. enum _hw_port tsfy = MAX_HW_PORT;
  465. u8 cmd[H2C_MCC_RQT_TSF_LEN] = {0};
  466. _enter_critical_mutex(&mccobjpriv->mcc_tsf_req_mutex, NULL);
  467. order0_iface = mccobjpriv->iface[0];
  468. order1_iface = mccobjpriv->iface[1];
  469. tsf_req_sctx = &mccobjpriv->mcc_tsf_req_sctx;
  470. rtw_sctx_init(tsf_req_sctx, MCC_EXPIRE_TIME);
  471. mccobjpriv->mcc_tsf_req_sctx_order = 0;
  472. tsfx = rtw_hal_get_port(order0_iface);
  473. tsfy = rtw_hal_get_port(order1_iface);
  474. SET_H2CCMD_MCC_RQT_TSFX(cmd, tsfx);
  475. SET_H2CCMD_MCC_RQT_TSFY(cmd, tsfy);
  476. rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_RQT_TSF, H2C_MCC_RQT_TSF_LEN, cmd);
  477. if (!rtw_sctx_wait(tsf_req_sctx, __func__))
  478. RTW_INFO(FUNC_ADPT_FMT": wait for mcc tsf req C2H time out\n", FUNC_ADPT_ARG(padapter));
  479. if (tsf_req_sctx->status == RTW_SCTX_DONE_SUCCESS && out_tsf != NULL) {
  480. out_tsf[0] = order0_iface->mcc_adapterpriv.tsf;
  481. out_tsf[1] = order1_iface->mcc_adapterpriv.tsf;
  482. }
  483. _exit_critical_mutex(&mccobjpriv->mcc_tsf_req_mutex, NULL);
  484. }
  485. static u8 rtw_hal_mcc_check_start_time_is_valid(PADAPTER padapter, u8 case_num,
  486. u32 tsfdiff, s8 *upper_bound_0, s8 *lower_bound_0, s8 *upper_bound_1, s8 *lower_bound_1)
  487. {
  488. struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
  489. struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
  490. u8 duration_0 = 0, duration_1 = 0;
  491. s8 final_upper_bound = 0, final_lower_bound = 0;
  492. u8 intersection = _FALSE;
  493. u8 min_start_time = 5;
  494. u8 max_start_time = 95;
  495. duration_0 = mccobjpriv->iface[0]->mcc_adapterpriv.mcc_duration;
  496. duration_1 = mccobjpriv->iface[1]->mcc_adapterpriv.mcc_duration;
  497. switch(case_num) {
  498. case 1:
  499. *upper_bound_0 = tsfdiff;
  500. *lower_bound_0 = tsfdiff - duration_1;
  501. *upper_bound_1 = 150 - duration_1;
  502. *lower_bound_1= 0;
  503. break;
  504. case 2:
  505. *upper_bound_0 = tsfdiff + 100;
  506. *lower_bound_0 = tsfdiff + 100 - duration_1;
  507. *upper_bound_1 = 150 - duration_1;
  508. *lower_bound_1= 0;
  509. break;
  510. case 3:
  511. *upper_bound_0 = tsfdiff + 50;
  512. *lower_bound_0 = tsfdiff + 50 - duration_1;
  513. *upper_bound_1 = 150 - duration_1;
  514. *lower_bound_1= 0;
  515. break;
  516. case 4:
  517. *upper_bound_0 = tsfdiff;
  518. *lower_bound_0 = tsfdiff - duration_1;
  519. *upper_bound_1 = 150 - duration_1;
  520. *lower_bound_1= 0;
  521. break;
  522. case 5:
  523. *upper_bound_0 = 200 - tsfdiff;
  524. *lower_bound_0 = 200 - tsfdiff - duration_1;
  525. *upper_bound_1 = 150 - duration_1;
  526. *lower_bound_1= 0;
  527. break;
  528. case 6:
  529. *upper_bound_0 = tsfdiff - 50;
  530. *lower_bound_0 = tsfdiff - 50 - duration_1;
  531. *upper_bound_1 = 150 - duration_1;
  532. *lower_bound_1= 0;
  533. break;
  534. default:
  535. RTW_ERR("[MCC] %s: error case number(%d\n)", __func__, case_num);
  536. }
  537. /* check Intersection or not */
  538. if ((*lower_bound_1 >= *upper_bound_0) ||
  539. (*lower_bound_0 >= *upper_bound_1))
  540. intersection = _FALSE;
  541. else
  542. intersection = _TRUE;
  543. if (intersection) {
  544. if (*upper_bound_0 > *upper_bound_1)
  545. final_upper_bound = *upper_bound_1;
  546. else
  547. final_upper_bound = *upper_bound_0;
  548. if (*lower_bound_0 > *lower_bound_1)
  549. final_lower_bound = *lower_bound_0;
  550. else
  551. final_lower_bound = *lower_bound_1;
  552. mccobjpriv->start_time = (final_lower_bound + final_upper_bound) / 2;
  553. /* check start time less than 5ms, request by Pablo@SD1 */
  554. if (mccobjpriv->start_time <= min_start_time) {
  555. mccobjpriv->start_time = 6;
  556. if (mccobjpriv->start_time < final_lower_bound && mccobjpriv->start_time > final_upper_bound) {
  557. intersection = _FALSE;
  558. goto exit;
  559. }
  560. }
  561. /* check start time less than 95ms */
  562. if (mccobjpriv->start_time >= max_start_time) {
  563. mccobjpriv->start_time = 90;
  564. if (mccobjpriv->start_time < final_lower_bound && mccobjpriv->start_time > final_upper_bound) {
  565. intersection = _FALSE;
  566. goto exit;
  567. }
  568. }
  569. }
  570. exit:
  571. return intersection;
  572. }
  573. static void rtw_hal_mcc_decide_duration(PADAPTER padapter)
  574. {
  575. struct registry_priv *registry_par = &padapter->registrypriv;
  576. struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
  577. struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
  578. struct mcc_adapter_priv *mccadapriv = NULL, *mccadapriv_order0 = NULL, *mccadapriv_order1 = NULL;
  579. _adapter *iface = NULL, *iface_order0 = NULL, *iface_order1 = NULL;
  580. u8 duration = 0, i = 0, duration_time;
  581. u8 mcc_interval = 150;
  582. iface_order0 = mccobjpriv->iface[0];
  583. iface_order1 = mccobjpriv->iface[1];
  584. mccadapriv_order0 = &iface_order0->mcc_adapterpriv;
  585. mccadapriv_order1 = &iface_order1->mcc_adapterpriv;
  586. if (mccobjpriv->duration == 0) {
  587. /* default */
  588. duration = 30;/*(%)*/
  589. RTW_INFO("%s: mccobjpriv->duration=0, use default value(%d)\n",
  590. __FUNCTION__, duration);
  591. } else {
  592. duration = mccobjpriv->duration;/*(%)*/
  593. RTW_INFO("%s: mccobjpriv->duration=%d\n",
  594. __FUNCTION__, duration);
  595. }
  596. mccobjpriv->interval = mcc_interval;
  597. mccobjpriv->mcc_stop_threshold = 2000 * 4 / 300 - 6;
  598. /* convert % to ms, for primary adapter */
  599. duration_time = mccobjpriv->interval * duration / 100;
  600. for (i = 0; i < dvobj->iface_nums; i++) {
  601. iface = dvobj->padapters[i];
  602. if (!iface)
  603. continue;
  604. mccadapriv = &iface->mcc_adapterpriv;
  605. if (mccadapriv->role == MCC_ROLE_MAX)
  606. continue;
  607. if (is_primary_adapter(iface))
  608. mccadapriv->mcc_duration = duration_time;
  609. else
  610. mccadapriv->mcc_duration = mccobjpriv->interval - duration_time;
  611. }
  612. RTW_INFO("[MCC]" FUNC_ADPT_FMT " order 0 duration=%d\n", FUNC_ADPT_ARG(iface_order0), mccadapriv_order0->mcc_duration);
  613. RTW_INFO("[MCC]" FUNC_ADPT_FMT " order 1 duration=%d\n", FUNC_ADPT_ARG(iface_order1), mccadapriv_order1->mcc_duration);
  614. }
  615. static u8 rtw_hal_mcc_update_timing_parameters(PADAPTER padapter, u8 force_update)
  616. {
  617. struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
  618. u8 need_update = _FALSE;
  619. u8 starting_ap_num = DEV_AP_STARTING_NUM(dvobj);
  620. u8 ap_num = DEV_AP_NUM(dvobj);
  621. /* for STA+STA, modify policy table */
  622. if (starting_ap_num == 0 && ap_num == 0) {
  623. struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
  624. struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
  625. struct mcc_adapter_priv *pmccadapriv = NULL;
  626. _adapter *iface = NULL;
  627. u64 tsf[MAX_MCC_NUM] = {0};
  628. u64 tsf0 = 0, tsf1 = 0;
  629. u32 beaconperiod_0 = 0, beaconperiod_1 = 0, tsfdiff = 0;
  630. s8 upper_bound_0 = 0, lower_bound_0 = 0;
  631. s8 upper_bound_1 = 0, lower_bound_1 = 0;
  632. u8 valid = _FALSE;
  633. u8 case_num = 1;
  634. u8 i = 0;
  635. /* query TSF */
  636. rtw_hal_mcc_rqt_tsf(padapter, tsf);
  637. /* selecet policy table according TSF diff */
  638. tsf0 = tsf[0];
  639. beaconperiod_0 = pmccobjpriv->iface[0]->mlmepriv.cur_network.network.Configuration.BeaconPeriod;
  640. tsf0 = rtw_modular64(tsf0, (beaconperiod_0 * TU));
  641. tsf1 = tsf[1];
  642. beaconperiod_1 = pmccobjpriv->iface[1]->mlmepriv.cur_network.network.Configuration.BeaconPeriod;
  643. tsf1 = rtw_modular64(tsf1, (beaconperiod_1 * TU));
  644. if (tsf0 > tsf1)
  645. tsfdiff = tsf0- tsf1;
  646. else
  647. tsfdiff = (tsf0 + beaconperiod_0 * TU) - tsf1;
  648. /* convert to ms */
  649. tsfdiff = (tsfdiff / TU);
  650. /* force update*/
  651. if (force_update) {
  652. RTW_INFO("orig TSF0:%lld, orig TSF1:%lld\n",
  653. pmccobjpriv->iface[0]->mcc_adapterpriv.tsf, pmccobjpriv->iface[1]->mcc_adapterpriv.tsf);
  654. RTW_INFO("tsf0:%lld, tsf1:%lld\n", tsf0, tsf1);
  655. RTW_INFO("%s: force=%d, last_tsfdiff=%d, tsfdiff=%d, THRESHOLD=%d\n",
  656. __func__, force_update, pmccobjpriv->last_tsfdiff, tsfdiff, MCC_UPDATE_PARAMETER_THRESHOLD);
  657. pmccobjpriv->last_tsfdiff = tsfdiff;
  658. need_update = _TRUE;
  659. } else {
  660. if (pmccobjpriv->last_tsfdiff > tsfdiff) {
  661. /* last tsfdiff - current tsfdiff > THRESHOLD, update parameters */
  662. if (pmccobjpriv->last_tsfdiff > (tsfdiff + MCC_UPDATE_PARAMETER_THRESHOLD)) {
  663. RTW_INFO("orig TSF0:%lld, orig TSF1:%lld\n",
  664. pmccobjpriv->iface[0]->mcc_adapterpriv.tsf, pmccobjpriv->iface[1]->mcc_adapterpriv.tsf);
  665. RTW_INFO("tsf0:%lld, tsf1:%lld\n", tsf0, tsf1);
  666. RTW_INFO("%s: force=%d, last_tsfdiff=%d, tsfdiff=%d, THRESHOLD=%d\n",
  667. __func__, force_update, pmccobjpriv->last_tsfdiff, tsfdiff, MCC_UPDATE_PARAMETER_THRESHOLD);
  668. pmccobjpriv->last_tsfdiff = tsfdiff;
  669. need_update = _TRUE;
  670. } else {
  671. need_update = _FALSE;
  672. }
  673. } else if (tsfdiff > pmccobjpriv->last_tsfdiff){
  674. /* current tsfdiff - last tsfdiff > THRESHOLD, update parameters */
  675. if (tsfdiff > (pmccobjpriv->last_tsfdiff + MCC_UPDATE_PARAMETER_THRESHOLD)) {
  676. RTW_INFO("orig TSF0:%lld, orig TSF1:%lld\n",
  677. pmccobjpriv->iface[0]->mcc_adapterpriv.tsf, pmccobjpriv->iface[1]->mcc_adapterpriv.tsf);
  678. RTW_INFO("tsf0:%lld, tsf1:%lld\n", tsf0, tsf1);
  679. RTW_INFO("%s: force=%d, last_tsfdiff=%d, tsfdiff=%d, THRESHOLD=%d\n",
  680. __func__, force_update, pmccobjpriv->last_tsfdiff, tsfdiff, MCC_UPDATE_PARAMETER_THRESHOLD);
  681. pmccobjpriv->last_tsfdiff = tsfdiff;
  682. need_update = _TRUE;
  683. } else {
  684. need_update = _FALSE;
  685. }
  686. } else {
  687. need_update = _FALSE;
  688. }
  689. }
  690. if (need_update == _FALSE)
  691. goto exit;
  692. rtw_hal_mcc_decide_duration(padapter);
  693. if (tsfdiff <= 50) {
  694. /* RX TBTT 0 */
  695. case_num = 1;
  696. valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,
  697. &upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);
  698. if (valid)
  699. goto valid_result;
  700. /* RX TBTT 1 */
  701. case_num = 2;
  702. valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,
  703. &upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);
  704. if (valid)
  705. goto valid_result;
  706. /* RX TBTT 2 */
  707. case_num = 3;
  708. valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,
  709. &upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);
  710. if (valid)
  711. goto valid_result;
  712. if (valid == _FALSE) {
  713. RTW_INFO("[MCC] do not find fit start time\n");
  714. RTW_INFO("[MCC] tsfdiff:%d, duration:%d(%c), interval:%d\n",
  715. tsfdiff, pmccobjpriv->duration, 37, pmccobjpriv->interval);
  716. }
  717. } else {
  718. /* RX TBTT 0 */
  719. case_num = 4;
  720. valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,
  721. &upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);
  722. if (valid)
  723. goto valid_result;
  724. /* RX TBTT 1 */
  725. case_num = 5;
  726. valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,
  727. &upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);
  728. if (valid)
  729. goto valid_result;
  730. /* RX TBTT 2 */
  731. case_num = 6;
  732. valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,
  733. &upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);
  734. if (valid)
  735. goto valid_result;
  736. if (valid == _FALSE) {
  737. RTW_INFO("[MCC] do not find fit start time\n");
  738. RTW_INFO("[MCC] tsfdiff:%d, duration:%d(%c), interval:%d\n",
  739. tsfdiff, pmccobjpriv->duration, 37, pmccobjpriv->interval);
  740. }
  741. }
  742. valid_result:
  743. RTW_INFO("********************\n");
  744. RTW_INFO("%s: case_num:%d, start time:%d\n",
  745. __func__, case_num, pmccobjpriv->start_time);
  746. RTW_INFO("%s: upper_bound_0:%d, lower_bound_0:%d\n",
  747. __func__, upper_bound_0, lower_bound_0);
  748. RTW_INFO("%s: upper_bound_1:%d, lower_bound_1:%d\n",
  749. __func__, upper_bound_1, lower_bound_1);
  750. for (i = 0; i < dvobj->iface_nums; i++) {
  751. iface = dvobj->padapters[i];
  752. if (iface == NULL)
  753. continue;
  754. pmccadapriv = &iface->mcc_adapterpriv;
  755. pmccadapriv = &iface->mcc_adapterpriv;
  756. if (pmccadapriv->role == MCC_ROLE_MAX)
  757. continue;
  758. #if 0
  759. if (pmccadapriv->order == 0) {
  760. pmccadapriv->mcc_duration = mcc_duration;
  761. } else if (pmccadapriv->order == 1) {
  762. pmccadapriv->mcc_duration = mcc_interval - mcc_duration;
  763. } else {
  764. RTW_INFO("[MCC] not support >= 3 interface\n");
  765. rtw_warn_on(1);
  766. }
  767. #endif
  768. RTW_INFO("********************\n");
  769. RTW_INFO(FUNC_ADPT_FMT": order:%d, role:%d\n",
  770. FUNC_ADPT_ARG(iface), pmccadapriv->order, pmccadapriv->role);
  771. RTW_INFO(FUNC_ADPT_FMT": mcc duration:%d, target tx bytes:%d\n",
  772. FUNC_ADPT_ARG(iface), pmccadapriv->mcc_duration, pmccadapriv->mcc_target_tx_bytes_to_port);
  773. RTW_INFO(FUNC_ADPT_FMT": mgmt queue macid:%d, bitmap:0x%02x\n",
  774. FUNC_ADPT_ARG(iface), pmccadapriv->mgmt_queue_macid, pmccadapriv->mcc_macid_bitmap);
  775. RTW_INFO("********************\n");
  776. }
  777. }
  778. exit:
  779. return need_update;
  780. }
  781. static u8 rtw_hal_decide_mcc_role(PADAPTER padapter)
  782. {
  783. struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
  784. _adapter *iface = NULL;
  785. struct mcc_adapter_priv *pmccadapriv = NULL;
  786. struct wifidirect_info *pwdinfo = NULL;
  787. struct mlme_priv *pmlmepriv = NULL;
  788. u8 ret = _SUCCESS, i = 0;
  789. u8 order = 1;
  790. for (i = 0; i < dvobj->iface_nums; i++) {
  791. iface = dvobj->padapters[i];
  792. if (iface == NULL)
  793. continue;
  794. pmccadapriv = &iface->mcc_adapterpriv;
  795. pwdinfo = &iface->wdinfo;
  796. if (MLME_IS_GO(iface))
  797. pmccadapriv->role = MCC_ROLE_GO;
  798. else if (MLME_IS_AP(iface))
  799. pmccadapriv->role = MCC_ROLE_AP;
  800. else if (MLME_IS_GC(iface))
  801. pmccadapriv->role = MCC_ROLE_GC;
  802. else if (MLME_IS_STA(iface)) {
  803. if (MLME_IS_LINKING(iface) || MLME_IS_ASOC(iface))
  804. pmccadapriv->role = MCC_ROLE_STA;
  805. else {
  806. /* bypass non-linked/non-linking interface */
  807. RTW_INFO(FUNC_ADPT_FMT" mlme state:0x%2x\n",
  808. FUNC_ADPT_ARG(iface), MLME_STATE(iface));
  809. continue;
  810. }
  811. } else {
  812. /* bypass non-linked/non-linking interface */
  813. RTW_INFO(FUNC_ADPT_FMT" P2P Role:%d, mlme state:0x%2x\n",
  814. FUNC_ADPT_ARG(iface), pwdinfo->role, MLME_STATE(iface));
  815. continue;
  816. }
  817. if (padapter == iface) {
  818. /* current adapter is order 0 */
  819. rtw_hal_config_mcc_role_setting(iface, 0);
  820. } else {
  821. rtw_hal_config_mcc_role_setting(iface, order);
  822. order ++;
  823. }
  824. }
  825. rtw_hal_mcc_update_timing_parameters(padapter, _TRUE);
  826. exit:
  827. return ret;
  828. }
  829. static void rtw_hal_construct_CTS(PADAPTER padapter, u8 *pframe, u32 *pLength)
  830. {
  831. u8 broadcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
  832. /* frame type, length = 1*/
  833. set_frame_sub_type(pframe, WIFI_RTS);
  834. /* frame control flag, length = 1 */
  835. *(pframe + 1) = 0;
  836. /* frame duration, length = 2 */
  837. *(pframe + 2) = 0x00;
  838. *(pframe + 3) = 0x78;
  839. /* frame recvaddr, length = 6 */
  840. _rtw_memcpy((pframe + 4), broadcast_addr, ETH_ALEN);
  841. _rtw_memcpy((pframe + 4 + ETH_ALEN), adapter_mac_addr(padapter), ETH_ALEN);
  842. _rtw_memcpy((pframe + 4 + ETH_ALEN*2), adapter_mac_addr(padapter), ETH_ALEN);
  843. *pLength = 22;
  844. }
  845. /* avoid wrong information for power limit */
  846. void rtw_hal_mcc_upadate_chnl_bw(_adapter *padapter, u8 ch, u8 ch_offset, u8 bw, u8 print)
  847. {
  848. u8 center_ch, chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
  849. struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
  850. PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter);
  851. u8 cch_160, cch_80, cch_40, cch_20;
  852. center_ch = rtw_get_center_ch(ch, bw, ch_offset);
  853. if (bw == CHANNEL_WIDTH_80) {
  854. if (center_ch > ch)
  855. chnl_offset80 = HAL_PRIME_CHNL_OFFSET_LOWER;
  856. else if (center_ch < ch)
  857. chnl_offset80 = HAL_PRIME_CHNL_OFFSET_UPPER;
  858. else
  859. chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
  860. }
  861. /* set Channel */
  862. /* saved channel/bw info */
  863. rtw_set_oper_ch(padapter, ch);
  864. rtw_set_oper_bw(padapter, bw);
  865. rtw_set_oper_choffset(padapter, ch_offset);
  866. cch_80 = bw == CHANNEL_WIDTH_80 ? center_ch : 0;
  867. cch_40 = bw == CHANNEL_WIDTH_40 ? center_ch : 0;
  868. cch_20 = bw == CHANNEL_WIDTH_20 ? center_ch : 0;
  869. if (cch_80 != 0)
  870. cch_40 = rtw_get_scch_by_cch_offset(cch_80, CHANNEL_WIDTH_80, chnl_offset80);
  871. if (cch_40 != 0)
  872. cch_20 = rtw_get_scch_by_cch_offset(cch_40, CHANNEL_WIDTH_40, ch_offset);
  873. hal->cch_80 = cch_80;
  874. hal->cch_40 = cch_40;
  875. hal->cch_20 = cch_20;
  876. hal->current_channel = center_ch;
  877. hal->CurrentCenterFrequencyIndex1 = center_ch;
  878. hal->current_channel_bw = bw;
  879. hal->nCur40MhzPrimeSC = ch_offset;
  880. hal->nCur80MhzPrimeSC = chnl_offset80;
  881. hal->current_band_type = ch > 14 ? BAND_ON_5G:BAND_ON_2_4G;
  882. if (print) {
  883. RTW_INFO(FUNC_ADPT_FMT" cch:%u, %s, offset40:%u, offset80:%u (%u, %u, %u), band:%s\n"
  884. , FUNC_ADPT_ARG(padapter), center_ch, ch_width_str(bw)
  885. , ch_offset, chnl_offset80
  886. , hal->cch_80, hal->cch_40, hal->cch_20
  887. , band_str(hal->current_band_type));
  888. }
  889. }
  890. #ifdef DBG_RSVD_PAGE_CFG
  891. #define RSVD_PAGE_CFG(ops, v1, v2, v3) \
  892. RTW_INFO("=== [RSVD][%s]-NeedPage:%d, TotalPageNum:%d TotalPacketLen:%d ===\n", \
  893. ops, v1, v2, v3)
  894. #endif
  895. u8 rtw_hal_dl_mcc_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 *index,
  896. u8 tx_desc, u32 page_size, u8 *total_page_num, RSVDPAGE_LOC *rsvd_page_loc, u8 *page_num)
  897. {
  898. u32 len = 0;
  899. _adapter *iface = NULL;
  900. struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
  901. struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
  902. struct mlme_ext_info *pmlmeinfo = NULL;
  903. struct mlme_ext_priv *pmlmeext = NULL;
  904. struct hal_com_data *hal = GET_HAL_DATA(adapter);
  905. struct mcc_adapter_priv *mccadapriv = NULL;
  906. u8 ret = _SUCCESS, i = 0, j =0, order = 0, CurtPktPageNum = 0;
  907. u8 *start = NULL;
  908. u8 path = RF_PATH_A;
  909. if (page_num) {
  910. #ifdef CONFIG_MCC_MODE_V2
  911. if (!hal->RegIQKFWOffload)
  912. RTW_WARN("[MCC] must enable FW IQK for New IC\n");
  913. #endif /* CONFIG_MCC_MODE_V2 */
  914. /* Null data(interface number) + power index(interface number) + 1 */
  915. *total_page_num += (2 * dvobj->iface_nums + 3);
  916. goto exit;
  917. }
  918. /* check proccess mcc start setting */
  919. if (!rtw_hal_check_mcc_status(adapter, MCC_STATUS_PROCESS_MCC_START_SETTING)) {
  920. ret = _FAIL;
  921. goto exit;
  922. }
  923. for (i = 0; i < dvobj->iface_nums; i++) {
  924. iface = dvobj->padapters[i];
  925. if (iface == NULL)
  926. continue;
  927. mccadapriv = &iface->mcc_adapterpriv;
  928. if (mccadapriv->role == MCC_ROLE_MAX)
  929. continue;
  930. order = mccadapriv->order;
  931. pmccobjpriv->mcc_loc_rsvd_paga[order] = *total_page_num;
  932. switch (mccadapriv->role) {
  933. case MCC_ROLE_STA:
  934. case MCC_ROLE_GC:
  935. /* Build NULL DATA */
  936. RTW_INFO("LocNull(order:%d): %d\n"
  937. , order, pmccobjpriv->mcc_loc_rsvd_paga[order]);
  938. len = 0;
  939. rtw_hal_construct_NullFunctionData(iface
  940. , &pframe[*index], &len, _FALSE, 0, 0, _FALSE);
  941. rtw_hal_fill_fake_txdesc(iface, &pframe[*index-tx_desc],
  942. len, _FALSE, _FALSE, _FALSE);
  943. CurtPktPageNum = (u8)PageNum(tx_desc + len, page_size);
  944. *total_page_num += CurtPktPageNum;
  945. *index += (CurtPktPageNum * page_size);
  946. #ifdef DBG_RSVD_PAGE_CFG
  947. RSVD_PAGE_CFG("LocNull", CurtPktPageNum, *total_page_num, *index);
  948. #endif
  949. break;
  950. case MCC_ROLE_AP:
  951. /* Bulid CTS */
  952. RTW_INFO("LocCTS(order:%d): %d\n"
  953. , order, pmccobjpriv->mcc_loc_rsvd_paga[order]);
  954. len = 0;
  955. rtw_hal_construct_CTS(iface, &pframe[*index], &len);
  956. rtw_hal_fill_fake_txdesc(iface, &pframe[*index-tx_desc],
  957. len, _FALSE, _FALSE, _FALSE);
  958. CurtPktPageNum = (u8)PageNum(tx_desc + len, page_size);
  959. *total_page_num += CurtPktPageNum;
  960. *index += (CurtPktPageNum * page_size);
  961. #ifdef DBG_RSVD_PAGE_CFG
  962. RSVD_PAGE_CFG("LocCTS", CurtPktPageNum, *total_page_num, *index);
  963. #endif
  964. break;
  965. case MCC_ROLE_GO:
  966. /* To DO */
  967. break;
  968. default:
  969. RTW_INFO(FUNC_ADPT_FMT": unknown role = %d\n"
  970. , FUNC_ADPT_ARG(iface), mccadapriv->role);
  971. break;
  972. }
  973. }
  974. for (i = 0; i < MAX_MCC_NUM; i++) {
  975. u8 center_ch = 0, ch = 0, bw = 0, bw_offset = 0;
  976. u8 power_index = 0;
  977. u8 rate_array_sz = 0;
  978. u8 *rates = NULL;
  979. u8 rate = 0;
  980. u8 shift = 0;
  981. u32 power_index_4bytes = 0;
  982. u8 total_rate = 0;
  983. u8 *total_rate_offset = NULL;
  984. iface = pmccobjpriv->iface[i];
  985. pmlmeext = &iface->mlmeextpriv;
  986. ch = pmlmeext->cur_channel;
  987. bw = pmlmeext->cur_bwmode;
  988. bw_offset = pmlmeext->cur_ch_offset;
  989. center_ch = rtw_get_center_ch(ch, bw, bw_offset);
  990. rtw_hal_mcc_upadate_chnl_bw(iface, ch, bw_offset, bw, _TRUE);
  991. start = &pframe[*index - tx_desc];
  992. _rtw_memset(start, 0, page_size);
  993. pmccobjpriv->mcc_pwr_idx_rsvd_page[i] = *total_page_num;
  994. RTW_INFO(ADPT_FMT" order:%d, pwr_idx_rsvd_page location[%d]: %d\n",
  995. ADPT_ARG(iface), mccadapriv->order,
  996. i, pmccobjpriv->mcc_pwr_idx_rsvd_page[i]);
  997. total_rate_offset = start;
  998. for (path = RF_PATH_A; path < hal->NumTotalRFPath; ++path) {
  999. total_rate = 0;
  1000. /* PATH A for 0~63 byte, PATH B for 64~127 byte*/
  1001. if (path == RF_PATH_A)
  1002. start = total_rate_offset + 1;
  1003. else if (path == RF_PATH_B)
  1004. start = total_rate_offset + 64;
  1005. else {
  1006. RTW_INFO("[MCC] %s: unknow RF PATH(%d)\n", __func__, path);
  1007. break;
  1008. }
  1009. /* CCK */
  1010. if (ch <= 14) {
  1011. rate_array_sz = rates_by_sections[CCK].rate_num;
  1012. rates = rates_by_sections[CCK].rates;
  1013. for (j = 0; j < rate_array_sz; ++j) {
  1014. power_index = rtw_hal_get_tx_power_index(iface, path, rates[j], bw, center_ch, NULL);
  1015. rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
  1016. shift = rate % 4;
  1017. if (shift == 0) {
  1018. *start = rate;
  1019. start++;
  1020. total_rate++;
  1021. #ifdef DBG_PWR_IDX_RSVD_PAGE
  1022. RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
  1023. ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
  1024. center_ch, MGN_RATE_STR(rates[j]), power_index);
  1025. #endif
  1026. }
  1027. *start = power_index;
  1028. start++;
  1029. #ifdef DBG_PWR_IDX_RSVD_PAGE
  1030. RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
  1031. ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
  1032. center_ch, MGN_RATE_STR(rates[j]), power_index);
  1033. shift = rate % 4;
  1034. power_index_4bytes |= ((power_index & 0xff) << (shift * 8));
  1035. if (shift == 3) {
  1036. rate = rate - 3;
  1037. RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate);
  1038. power_index_4bytes = 0;
  1039. total_rate++;
  1040. }
  1041. #endif
  1042. }
  1043. }
  1044. /* OFDM */
  1045. rate_array_sz = rates_by_sections[OFDM].rate_num;
  1046. rates = rates_by_sections[OFDM].rates;
  1047. for (j = 0; j < rate_array_sz; ++j) {
  1048. power_index = rtw_hal_get_tx_power_index(iface, path, rates[j], bw, center_ch, NULL);
  1049. rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
  1050. shift = rate % 4;
  1051. if (shift == 0) {
  1052. *start = rate;
  1053. start++;
  1054. total_rate++;
  1055. #ifdef DBG_PWR_IDX_RSVD_PAGE
  1056. RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
  1057. ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
  1058. center_ch, MGN_RATE_STR(rates[j]), power_index);
  1059. #endif
  1060. }
  1061. *start = power_index;
  1062. start++;
  1063. #ifdef DBG_PWR_IDX_RSVD_PAGE
  1064. RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
  1065. ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
  1066. center_ch, MGN_RATE_STR(rates[j]), power_index);
  1067. shift = rate % 4;
  1068. power_index_4bytes |= ((power_index & 0xff) << (shift * 8));
  1069. if (shift == 3) {
  1070. rate = rate - 3;
  1071. RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate);
  1072. power_index_4bytes = 0;
  1073. total_rate++;
  1074. }
  1075. #endif
  1076. }
  1077. /* HT_MCS0_MCS7 */
  1078. rate_array_sz = rates_by_sections[HT_MCS0_MCS7].rate_num;
  1079. rates = rates_by_sections[HT_MCS0_MCS7].rates;
  1080. for (j = 0; j < rate_array_sz; ++j) {
  1081. power_index = rtw_hal_get_tx_power_index(iface, path, rates[j], bw, center_ch, NULL);
  1082. rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
  1083. shift = rate % 4;
  1084. if (shift == 0) {
  1085. *start = rate;
  1086. start++;
  1087. total_rate++;
  1088. #ifdef DBG_PWR_IDX_RSVD_PAGE
  1089. RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
  1090. ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
  1091. center_ch, MGN_RATE_STR(rates[j]), power_index);
  1092. #endif
  1093. }
  1094. *start = power_index;
  1095. start++;
  1096. #ifdef DBG_PWR_IDX_RSVD_PAGE
  1097. RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
  1098. ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
  1099. center_ch, MGN_RATE_STR(rates[j]), power_index);
  1100. shift = rate % 4;
  1101. power_index_4bytes |= ((power_index & 0xff) << (shift * 8));
  1102. if (shift == 3) {
  1103. rate = rate - 3;
  1104. RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate);
  1105. power_index_4bytes = 0;
  1106. total_rate++;
  1107. }
  1108. #endif
  1109. }
  1110. /* HT_MCS8_MCS15 */
  1111. rate_array_sz = rates_by_sections[HT_MCS8_MCS15].rate_num;
  1112. rates = rates_by_sections[HT_MCS8_MCS15].rates;
  1113. for (j = 0; j < rate_array_sz; ++j) {
  1114. power_index = rtw_hal_get_tx_power_index(iface, path, rates[j], bw, center_ch, NULL);
  1115. rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
  1116. shift = rate % 4;
  1117. if (shift == 0) {
  1118. *start = rate;
  1119. start++;
  1120. total_rate++;
  1121. #ifdef DBG_PWR_IDX_RSVD_PAGE
  1122. RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
  1123. ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
  1124. center_ch, MGN_RATE_STR(rates[j]), power_index);
  1125. #endif
  1126. }
  1127. *start = power_index;
  1128. start++;
  1129. #ifdef DBG_PWR_IDX_RSVD_PAGE
  1130. RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
  1131. ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
  1132. center_ch, MGN_RATE_STR(rates[j]), power_index);
  1133. shift = rate % 4;
  1134. power_index_4bytes |= ((power_index & 0xff) << (shift * 8));
  1135. if (shift == 3) {
  1136. rate = rate - 3;
  1137. RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate);
  1138. power_index_4bytes = 0;
  1139. total_rate++;
  1140. }
  1141. #endif
  1142. }
  1143. /* VHT_1SSMCS0_1SSMCS9 */
  1144. rate_array_sz = rates_by_sections[VHT_1SSMCS0_1SSMCS9].rate_num;
  1145. rates = rates_by_sections[VHT_1SSMCS0_1SSMCS9].rates;
  1146. for (j = 0; j < rate_array_sz; ++j) {
  1147. power_index = rtw_hal_get_tx_power_index(iface, path, rates[j], bw, center_ch, NULL);
  1148. rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
  1149. shift = rate % 4;
  1150. if (shift == 0) {
  1151. *start = rate;
  1152. start++;
  1153. total_rate++;
  1154. #ifdef DBG_PWR_IDX_RSVD_PAGE
  1155. RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:0x%02x\n",
  1156. ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
  1157. center_ch, MGN_RATE_STR(rates[j]), power_index);
  1158. #endif
  1159. }
  1160. *start = power_index;
  1161. start++;
  1162. #ifdef DBG_PWR_IDX_RSVD_PAGE
  1163. RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
  1164. ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
  1165. center_ch, MGN_RATE_STR(rates[j]), power_index);
  1166. shift = rate % 4;
  1167. power_index_4bytes |= ((power_index & 0xff) << (shift * 8));
  1168. if (shift == 3) {
  1169. rate = rate - 3;
  1170. RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate);
  1171. power_index_4bytes = 0;
  1172. total_rate++;
  1173. }
  1174. #endif
  1175. }
  1176. /* VHT_2SSMCS0_2SSMCS9 */
  1177. rate_array_sz = rates_by_sections[VHT_2SSMCS0_2SSMCS9].rate_num;
  1178. rates = rates_by_sections[VHT_2SSMCS0_2SSMCS9].rates;
  1179. for (j = 0; j < rate_array_sz; ++j) {
  1180. power_index = rtw_hal_get_tx_power_index(iface, path, rates[j], bw, center_ch, NULL);
  1181. rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
  1182. shift = rate % 4;
  1183. if (shift == 0) {
  1184. *start = rate;
  1185. start++;
  1186. total_rate++;
  1187. #ifdef DBG_PWR_IDX_RSVD_PAGE
  1188. RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
  1189. ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
  1190. center_ch, MGN_RATE_STR(rates[j]), power_index);
  1191. #endif
  1192. }
  1193. *start = power_index;
  1194. start++;
  1195. #ifdef DBG_PWR_IDX_RSVD_PAGE
  1196. RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
  1197. ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
  1198. center_ch, MGN_RATE_STR(rates[j]), power_index);
  1199. shift = rate % 4;
  1200. power_index_4bytes |= ((power_index & 0xff) << (shift * 8));
  1201. if (shift == 3) {
  1202. rate = rate - 3;
  1203. RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate);
  1204. power_index_4bytes = 0;
  1205. total_rate++;
  1206. }
  1207. #endif
  1208. }
  1209. }
  1210. /* total rate store in offset 0 */
  1211. *total_rate_offset = total_rate;
  1212. #ifdef DBG_PWR_IDX_RSVD_PAGE
  1213. RTW_INFO("total_rate=%d\n", total_rate);
  1214. RTW_INFO(" ======================="ADPT_FMT"===========================\n", ADPT_ARG(iface));
  1215. RTW_INFO_DUMP("\n", total_rate_offset, 128);
  1216. RTW_INFO(" ==================================================\n");
  1217. #endif
  1218. CurtPktPageNum = 1;
  1219. *total_page_num += CurtPktPageNum;
  1220. *index += (CurtPktPageNum * page_size);
  1221. #ifdef DBG_RSVD_PAGE_CFG
  1222. RSVD_PAGE_CFG("mcc_pwr_idx_rsvd_page", CurtPktPageNum, *total_page_num, *index);
  1223. #endif
  1224. }
  1225. exit:
  1226. return ret;
  1227. }
  1228. /*
  1229. * 1. Download MCC rsvd page
  1230. * 2. Re-Download beacon after download rsvd page
  1231. */
  1232. static void rtw_hal_set_fw_mcc_rsvd_page(PADAPTER padapter)
  1233. {
  1234. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
  1235. struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
  1236. struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
  1237. PADAPTER port0_iface = dvobj_get_port0_adapter(dvobj);
  1238. PADAPTER iface = NULL;
  1239. struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
  1240. u8 mstatus = RT_MEDIA_CONNECT, i = 0;
  1241. RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
  1242. rtw_hal_set_hwreg(port0_iface, HW_VAR_H2C_FW_JOINBSSRPT, (u8 *)(&mstatus));
  1243. /* Re-Download beacon */
  1244. for (i = 0; i < MAX_MCC_NUM; i++) {
  1245. iface = pmccobjpriv->iface[i];
  1246. if (iface == NULL)
  1247. continue;
  1248. pmccadapriv = &iface->mcc_adapterpriv;
  1249. if (pmccadapriv->role == MCC_ROLE_AP
  1250. || pmccadapriv->role == MCC_ROLE_GO) {
  1251. tx_beacon_hdl(iface, NULL);
  1252. }
  1253. }
  1254. }
  1255. static void rtw_hal_set_mcc_rsvdpage_cmd(_adapter *padapter)
  1256. {
  1257. u8 cmd[H2C_MCC_LOCATION_LEN] = {0}, i = 0, order = 0;
  1258. _adapter *iface = NULL;
  1259. PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter);
  1260. struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
  1261. struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
  1262. SET_H2CCMD_MCC_PWRIDX_OFFLOAD_EN(cmd, _TRUE);
  1263. SET_H2CCMD_MCC_PWRIDX_OFFLOAD_RFNUM(cmd, hal->NumTotalRFPath);
  1264. for (order = 0; order < MAX_MCC_NUM; order++) {
  1265. iface = pmccobjpriv->iface[i];
  1266. SET_H2CCMD_MCC_RSVDPAGE_LOC((cmd + order), pmccobjpriv->mcc_loc_rsvd_paga[order]);
  1267. SET_H2CCMD_MCC_PWRIDX_RSVDPAGE_LOC ((cmd + order), pmccobjpriv->mcc_pwr_idx_rsvd_page[order]);
  1268. }
  1269. #ifdef CONFIG_MCC_MODE_DEBUG
  1270. RTW_INFO("=========================\n");
  1271. RTW_INFO("MCC RSVD PAGE LOC:\n");
  1272. for (i = 0; i < H2C_MCC_LOCATION_LEN; i++)
  1273. pr_dbg("0x%x ", cmd[i]);
  1274. pr_dbg("\n");
  1275. RTW_INFO("=========================\n");
  1276. #endif /* CONFIG_MCC_MODE_DEBUG */
  1277. rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_LOCATION, H2C_MCC_LOCATION_LEN, cmd);
  1278. }
  1279. static void rtw_hal_set_mcc_time_setting_cmd(PADAPTER padapter)
  1280. {
  1281. struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
  1282. struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
  1283. struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
  1284. struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
  1285. u8 cmd[H2C_MCC_TIME_SETTING_LEN] = {0};
  1286. u8 fw_eable = 1;
  1287. u8 swchannel_early_time = MCC_SWCH_FW_EARLY_TIME;
  1288. u8 starting_ap_num = DEV_AP_STARTING_NUM(dvobj);
  1289. u8 ap_num = DEV_AP_NUM(dvobj);
  1290. if (starting_ap_num == 0 && ap_num == 0)
  1291. /* For STA+GC/STA+STA, TSF of GC/STA does not need to sync from TSF of other STA/GC */
  1292. fw_eable = 0;
  1293. else
  1294. /* Only for STA+GO/STA+AP, TSF of AP/GO need to sync from TSF of STA */
  1295. fw_eable = 1;
  1296. if (fw_eable == 1) {
  1297. PADAPTER order0_iface = NULL;
  1298. PADAPTER order1_iface = NULL;
  1299. u8 policy_idx = mccobjpriv->policy_index;
  1300. u8 tsf_sync_offset = mcc_switch_channel_policy_table[policy_idx][MCC_TSF_SYNC_OFFSET_IDX];
  1301. u8 start_time_offset = mcc_switch_channel_policy_table[policy_idx][MCC_START_TIME_OFFSET_IDX];
  1302. u8 interval = mcc_switch_channel_policy_table[policy_idx][MCC_INTERVAL_IDX];
  1303. u8 guard_offset0 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET0_IDX];
  1304. u8 guard_offset1 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET1_IDX];
  1305. enum _hw_port tsf_bsae_port = MAX_HW_PORT;
  1306. enum _hw_port tsf_sync_port = MAX_HW_PORT;
  1307. order0_iface = mccobjpriv->iface[0];
  1308. order1_iface = mccobjpriv->iface[1];
  1309. tsf_bsae_port = rtw_hal_get_port(order1_iface);
  1310. tsf_sync_port = rtw_hal_get_port(order0_iface);
  1311. /* FW set enable */
  1312. SET_H2CCMD_MCC_TIME_SETTING_FW_EN(cmd, fw_eable);
  1313. /* TSF Sync offset */
  1314. SET_H2CCMD_MCC_TIME_SETTING_TSF_SYNC_OFFSET(cmd, tsf_sync_offset);
  1315. /* start time offset */
  1316. SET_H2CCMD_MCC_TIME_SETTING_START_TIME(cmd, (start_time_offset + guard_offset0));
  1317. /* interval */
  1318. SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(cmd, interval);
  1319. /* Early time to inform driver by C2H before switch channel */
  1320. SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(cmd, swchannel_early_time);
  1321. /* Port0 sync from Port1, not support multi-port */
  1322. SET_H2CCMD_MCC_TIME_SETTING_ORDER_BASE(cmd, tsf_bsae_port);
  1323. SET_H2CCMD_MCC_TIME_SETTING_ORDER_SYNC(cmd, tsf_sync_port);
  1324. } else {
  1325. /* start time offset */
  1326. SET_H2CCMD_MCC_TIME_SETTING_START_TIME(cmd, mccobjpriv->start_time);
  1327. /* interval */
  1328. SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(cmd, mccobjpriv->interval);
  1329. /* Early time to inform driver by C2H before switch channel */
  1330. SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(cmd, swchannel_early_time);
  1331. }
  1332. #ifdef CONFIG_MCC_MODE_DEBUG
  1333. {
  1334. u8 i = 0;
  1335. RTW_INFO("=========================\n");
  1336. RTW_INFO("NoA:\n");
  1337. for (i = 0; i < H2C_MCC_TIME_SETTING_LEN; i++)
  1338. pr_dbg("0x%x ", cmd[i]);
  1339. pr_dbg("\n");
  1340. RTW_INFO("=========================\n");
  1341. }
  1342. #endif /* CONFIG_MCC_MODE_DEBUG */
  1343. rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_TIME_SETTING, H2C_MCC_TIME_SETTING_LEN, cmd);
  1344. }
  1345. static void rtw_hal_set_mcc_IQK_offload_cmd(PADAPTER padapter)
  1346. {
  1347. struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
  1348. struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
  1349. struct mcc_adapter_priv *pmccadapriv = NULL;
  1350. _adapter *iface = NULL;
  1351. u8 cmd[H2C_MCC_IQK_PARAM_LEN] = {0}, bready = 0, i = 0, order = 0;
  1352. u16 TX_X = 0, TX_Y = 0, RX_X = 0, RX_Y = 0;
  1353. u8 total_rf_path = GET_HAL_DATA(padapter)->NumTotalRFPath;
  1354. u8 rf_path_idx = 0, last_order = MAX_MCC_NUM - 1, last_rf_path_index = total_rf_path - 1;
  1355. /* by order, last order & last_rf_path_index must set ready bit = 1 */
  1356. for (i = 0; i < MAX_MCC_NUM; i++) {
  1357. iface = pmccobjpriv->iface[i];
  1358. if (iface == NULL)
  1359. continue;
  1360. pmccadapriv = &iface->mcc_adapterpriv;
  1361. order = pmccadapriv->order;
  1362. for (rf_path_idx = 0; rf_path_idx < total_rf_path; rf_path_idx ++) {
  1363. _rtw_memset(cmd, 0, H2C_MCC_IQK_PARAM_LEN);
  1364. TX_X = pmccadapriv->mcc_iqk_arr[rf_path_idx].TX_X & 0x7ff;/* [10:0] */
  1365. TX_Y = pmccadapriv->mcc_iqk_arr[rf_path_idx].TX_Y & 0x7ff;/* [10:0] */
  1366. RX_X = pmccadapriv->mcc_iqk_arr[rf_path_idx].RX_X & 0x3ff;/* [9:0] */
  1367. RX_Y = pmccadapriv->mcc_iqk_arr[rf_path_idx].RX_Y & 0x3ff;/* [9:0] */
  1368. /* ready or not */
  1369. if (order == last_order && rf_path_idx == last_rf_path_index)
  1370. bready = 1;
  1371. else
  1372. bready = 0;
  1373. SET_H2CCMD_MCC_IQK_READY(cmd, bready);
  1374. SET_H2CCMD_MCC_IQK_ORDER(cmd, order);
  1375. SET_H2CCMD_MCC_IQK_PATH(cmd, rf_path_idx);
  1376. /* fill RX_X[7:0] to (cmd+1)[7:0] bitlen=8 */
  1377. SET_H2CCMD_MCC_IQK_RX_L(cmd, (u8)(RX_X & 0xff));
  1378. /* fill RX_X[9:8] to (cmd+2)[1:0] bitlen=2 */
  1379. SET_H2CCMD_MCC_IQK_RX_M1(cmd, (u8)((RX_X >> 8) & 0x03));
  1380. /* fill RX_Y[5:0] to (cmd+2)[7:2] bitlen=6 */
  1381. SET_H2CCMD_MCC_IQK_RX_M2(cmd, (u8)(RX_Y & 0x3f));
  1382. /* fill RX_Y[9:6] to (cmd+3)[3:0] bitlen=4 */
  1383. SET_H2CCMD_MCC_IQK_RX_H(cmd, (u8)((RX_Y >> 6) & 0x0f));
  1384. /* fill TX_X[7:0] to (cmd+4)[7:0] bitlen=8 */
  1385. SET_H2CCMD_MCC_IQK_TX_L(cmd, (u8)(TX_X & 0xff));
  1386. /* fill TX_X[10:8] to (cmd+5)[2:0] bitlen=3 */
  1387. SET_H2CCMD_MCC_IQK_TX_M1(cmd, (u8)((TX_X >> 8) & 0x07));
  1388. /* fill TX_Y[4:0] to (cmd+5)[7:3] bitlen=5 */
  1389. SET_H2CCMD_MCC_IQK_TX_M2(cmd, (u8)(TX_Y & 0x1f));
  1390. /* fill TX_Y[10:5] to (cmd+6)[5:0] bitlen=6 */
  1391. SET_H2CCMD_MCC_IQK_TX_H(cmd, (u8)((TX_Y >> 5) & 0x3f));
  1392. #ifdef CONFIG_MCC_MODE_DEBUG
  1393. RTW_INFO("=========================\n");
  1394. RTW_INFO(FUNC_ADPT_FMT" IQK:\n", FUNC_ADPT_ARG(iface));
  1395. RTW_INFO("TX_X: 0x%02x\n", TX_X);
  1396. RTW_INFO("TX_Y: 0x%02x\n", TX_Y);
  1397. RTW_INFO("RX_X: 0x%02x\n", RX_X);
  1398. RTW_INFO("RX_Y: 0x%02x\n", RX_Y);
  1399. RTW_INFO("cmd[0]:0x%02x\n", cmd[0]);
  1400. RTW_INFO("cmd[1]:0x%02x\n", cmd[1]);
  1401. RTW_INFO("cmd[2]:0x%02x\n", cmd[2]);
  1402. RTW_INFO("cmd[3]:0x%02x\n", cmd[3]);
  1403. RTW_INFO("cmd[4]:0x%02x\n", cmd[4]);
  1404. RTW_INFO("cmd[5]:0x%02x\n", cmd[5]);
  1405. RTW_INFO("cmd[6]:0x%02x\n", cmd[6]);
  1406. RTW_INFO("=========================\n");
  1407. #endif /* CONFIG_MCC_MODE_DEBUG */
  1408. rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_IQK_PARAM, H2C_MCC_IQK_PARAM_LEN, cmd);
  1409. }
  1410. }
  1411. }
  1412. static void rtw_hal_set_mcc_macid_cmd(PADAPTER padapter)
  1413. {
  1414. struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
  1415. struct mcc_adapter_priv *pmccadapriv = NULL;
  1416. _adapter *iface = NULL;
  1417. u8 cmd[H2C_MCC_MACID_BITMAP_LEN] = {0}, i = 0, order = 0;
  1418. u16 bitmap = 0;
  1419. for (i = 0; i < dvobj->iface_nums; i++) {
  1420. iface = dvobj->padapters[i];
  1421. if (iface == NULL)
  1422. continue;
  1423. pmccadapriv = &iface->mcc_adapterpriv;
  1424. if (pmccadapriv->role == MCC_ROLE_MAX)
  1425. continue;
  1426. order = pmccadapriv->order;
  1427. bitmap = pmccadapriv->mcc_macid_bitmap;
  1428. if (order >= (H2C_MCC_MACID_BITMAP_LEN/2)) {
  1429. RTW_INFO(FUNC_ADPT_FMT" only support 3 interface at most(%d)\n"
  1430. , FUNC_ADPT_ARG(padapter), order);
  1431. continue;
  1432. }
  1433. SET_H2CCMD_MCC_MACID_BITMAP_L((cmd + order * 2), (u8)(bitmap & 0xff));
  1434. SET_H2CCMD_MCC_MACID_BITMAP_H((cmd + order * 2), (u8)((bitmap >> 8) & 0xff));
  1435. }
  1436. #ifdef CONFIG_MCC_MODE_DEBUG
  1437. RTW_INFO("=========================\n");
  1438. RTW_INFO("MACID BITMAP: ");
  1439. for (i = 0; i < H2C_MCC_MACID_BITMAP_LEN; i++)
  1440. printk("0x%x ", cmd[i]);
  1441. printk("\n");
  1442. RTW_INFO("=========================\n");
  1443. #endif /* CONFIG_MCC_MODE_DEBUG */
  1444. rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_MACID_BITMAP, H2C_MCC_MACID_BITMAP_LEN, cmd);
  1445. }
  1446. #ifdef CONFIG_MCC_MODE_V2
  1447. static u8 get_pri_ch_idx_by_adapter(u8 center_ch, u8 channel, u8 bw, u8 ch_offset40)
  1448. {
  1449. u8 pri_ch_idx = 0, chnl_offset80 = 0;
  1450. if (bw == CHANNEL_WIDTH_80) {
  1451. if (center_ch > channel)
  1452. chnl_offset80 = HAL_PRIME_CHNL_OFFSET_LOWER;
  1453. else if (center_ch < channel)
  1454. chnl_offset80 = HAL_PRIME_CHNL_OFFSET_UPPER;
  1455. else
  1456. chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
  1457. }
  1458. if (bw == CHANNEL_WIDTH_80) {
  1459. /* primary channel is at lower subband of 80MHz & 40MHz */
  1460. if ((ch_offset40 == HAL_PRIME_CHNL_OFFSET_LOWER) && (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_LOWER))
  1461. pri_ch_idx = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
  1462. /* primary channel is at lower subband of 80MHz & upper subband of 40MHz */
  1463. else if ((ch_offset40 == HAL_PRIME_CHNL_OFFSET_UPPER) && (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_LOWER))
  1464. pri_ch_idx = VHT_DATA_SC_20_LOWER_OF_80MHZ;
  1465. /* primary channel is at upper subband of 80MHz & lower subband of 40MHz */
  1466. else if ((ch_offset40 == HAL_PRIME_CHNL_OFFSET_LOWER) && (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_UPPER))
  1467. pri_ch_idx = VHT_DATA_SC_20_UPPER_OF_80MHZ;
  1468. /* primary channel is at upper subband of 80MHz & upper subband of 40MHz */
  1469. else if ((ch_offset40 == HAL_PRIME_CHNL_OFFSET_UPPER) && (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_UPPER))
  1470. pri_ch_idx = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
  1471. else {
  1472. if (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_LOWER)
  1473. pri_ch_idx = VHT_DATA_SC_40_LOWER_OF_80MHZ;
  1474. else if (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_UPPER)
  1475. pri_ch_idx = VHT_DATA_SC_40_UPPER_OF_80MHZ;
  1476. else
  1477. RTW_INFO("SCMapping: DONOT CARE Mode Setting\n");
  1478. }
  1479. } else if (bw == CHANNEL_WIDTH_40) {
  1480. /* primary channel is at upper subband of 40MHz */
  1481. if (ch_offset40== HAL_PRIME_CHNL_OFFSET_UPPER)
  1482. pri_ch_idx = VHT_DATA_SC_20_UPPER_OF_80MHZ;
  1483. /* primary channel is at lower subband of 40MHz */
  1484. else if (ch_offset40 == HAL_PRIME_CHNL_OFFSET_LOWER)
  1485. pri_ch_idx = VHT_DATA_SC_20_LOWER_OF_80MHZ;
  1486. else
  1487. RTW_INFO("SCMapping: DONOT CARE Mode Setting\n");
  1488. }
  1489. return pri_ch_idx;
  1490. }
  1491. static void rtw_hal_set_mcc_ctrl_cmd_v2(PADAPTER padapter, u8 stop)
  1492. {
  1493. u8 cmd[H2C_MCC_CTRL_LEN] = {0}, i = 0;
  1494. u8 order = 0, totalnum = 0;
  1495. u8 center_ch = 0, pri_ch_idx = 0, bw = 0;
  1496. u8 duration = 0, role = 0, incurch = 0, rfetype = 0, distxnull = 0, c2hrpt = 0;
  1497. u8 dis_sw_retry = 0, null_early_time=2, tsfx = 0, update_parm = 0;
  1498. struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
  1499. struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
  1500. struct mcc_adapter_priv *mccadapriv = NULL;
  1501. struct mlme_ext_priv *pmlmeext = NULL;
  1502. struct mlme_ext_info *pmlmeinfo = NULL;
  1503. _adapter *iface = NULL;
  1504. RTW_INFO(FUNC_ADPT_FMT": stop=%d\n", FUNC_ADPT_ARG(padapter), stop);
  1505. for (i = 0; i < MAX_MCC_NUM; i++) {
  1506. iface = pmccobjpriv->iface[i];
  1507. if (iface == NULL)
  1508. continue;
  1509. if (stop) {
  1510. if (iface != padapter)
  1511. continue;
  1512. }
  1513. mccadapriv = &iface->mcc_adapterpriv;
  1514. order = mccadapriv->order;
  1515. if (!stop)
  1516. totalnum = MAX_MCC_NUM;
  1517. else
  1518. totalnum = 0xff; /* 0xff means stop */
  1519. pmlmeext = &iface->mlmeextpriv;
  1520. center_ch = rtw_get_center_ch(pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset);
  1521. pri_ch_idx = get_pri_ch_idx_by_adapter(center_ch, pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset);
  1522. bw = pmlmeext->cur_bwmode;
  1523. duration = mccadapriv->mcc_duration;
  1524. role = mccadapriv->role;
  1525. incurch = _FALSE;
  1526. dis_sw_retry = _TRUE;
  1527. /* STA/GC TX NULL data to inform AP/GC for ps mode */
  1528. switch (role) {
  1529. case MCC_ROLE_GO:
  1530. case MCC_ROLE_AP:
  1531. distxnull = MCC_DISABLE_TX_NULL;
  1532. break;
  1533. case MCC_ROLE_GC:
  1534. set_channel_bwmode(iface, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
  1535. distxnull = MCC_ENABLE_TX_NULL;
  1536. break;
  1537. case MCC_ROLE_STA:
  1538. distxnull = MCC_ENABLE_TX_NULL;
  1539. break;
  1540. }
  1541. null_early_time = mccadapriv->null_early;
  1542. c2hrpt = MCC_C2H_REPORT_ALL_STATUS;
  1543. tsfx = rtw_hal_get_port(iface);
  1544. update_parm = 0;
  1545. SET_H2CCMD_MCC_CTRL_V2_ORDER(cmd, order);
  1546. SET_H2CCMD_MCC_CTRL_V2_TOTALNUM(cmd, totalnum);
  1547. SET_H2CCMD_MCC_CTRL_V2_CENTRAL_CH(cmd, center_ch);
  1548. SET_H2CCMD_MCC_CTRL_V2_PRIMARY_CH(cmd, pri_ch_idx);
  1549. SET_H2CCMD_MCC_CTRL_V2_BW(cmd, bw);
  1550. SET_H2CCMD_MCC_CTRL_V2_DURATION(cmd, duration);
  1551. SET_H2CCMD_MCC_CTRL_V2_ROLE(cmd, role);
  1552. SET_H2CCMD_MCC_CTRL_V2_INCURCH(cmd, incurch);
  1553. SET_H2CCMD_MCC_CTRL_V2_DIS_SW_RETRY(cmd, dis_sw_retry);
  1554. SET_H2CCMD_MCC_CTRL_V2_DISTXNULL(cmd, distxnull);
  1555. SET_H2CCMD_MCC_CTRL_V2_C2HRPT(cmd, c2hrpt);
  1556. SET_H2CCMD_MCC_CTRL_V2_TSFX(cmd, tsfx);
  1557. SET_H2CCMD_MCC_CTRL_V2_NULL_EARLY(cmd, null_early_time);
  1558. SET_H2CCMD_MCC_CTRL_V2_UPDATE_PARM(cmd, update_parm);
  1559. #ifdef CONFIG_MCC_MODE_DEBUG
  1560. RTW_INFO("=========================\n");
  1561. RTW_INFO(FUNC_ADPT_FMT" MCC INFO:\n", FUNC_ADPT_ARG(iface));
  1562. RTW_INFO("cmd[0]:0x%02x\n", cmd[0]);
  1563. RTW_INFO("cmd[1]:0x%02x\n", cmd[1]);
  1564. RTW_INFO("cmd[2]:0x%02x\n", cmd[2]);
  1565. RTW_INFO("cmd[3]:0x%02x\n", cmd[3]);
  1566. RTW_INFO("cmd[4]:0x%02x\n", cmd[4]);
  1567. RTW_INFO("cmd[5]:0x%02x\n", cmd[5]);
  1568. RTW_INFO("cmd[6]:0x%02x\n", cmd[6]);
  1569. RTW_INFO("=========================\n");
  1570. #endif /* CONFIG_MCC_MODE_DEBUG */
  1571. rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_CTRL_V2, H2C_MCC_CTRL_LEN, cmd);
  1572. }
  1573. }
  1574. #else
  1575. static void rtw_hal_set_mcc_ctrl_cmd_v1(PADAPTER padapter, u8 stop)
  1576. {
  1577. u8 cmd[H2C_MCC_CTRL_LEN] = {0}, i = 0;
  1578. u8 order = 0, totalnum = 0, chidx = 0, bw = 0, bw40sc = 0, bw80sc = 0;
  1579. u8 duration = 0, role = 0, incurch = 0, rfetype = 0, distxnull = 0, c2hrpt = 0, chscan = 0;
  1580. struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
  1581. struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
  1582. struct mcc_adapter_priv *mccadapriv = NULL;
  1583. struct mlme_ext_priv *pmlmeext = NULL;
  1584. struct mlme_ext_info *pmlmeinfo = NULL;
  1585. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
  1586. _adapter *iface = NULL;
  1587. RTW_INFO(FUNC_ADPT_FMT": stop=%d\n", FUNC_ADPT_ARG(padapter), stop);
  1588. for (i = 0; i < MAX_MCC_NUM; i++) {
  1589. iface = pmccobjpriv->iface[i];
  1590. if (iface == NULL)
  1591. continue;
  1592. if (stop) {
  1593. if (iface != padapter)
  1594. continue;
  1595. }
  1596. mccadapriv = &iface->mcc_adapterpriv;
  1597. order = mccadapriv->order;
  1598. if (!stop)
  1599. totalnum = MAX_MCC_NUM;
  1600. else
  1601. totalnum = 0xff; /* 0xff means stop */
  1602. pmlmeext = &iface->mlmeextpriv;
  1603. chidx = pmlmeext->cur_channel;
  1604. bw = pmlmeext->cur_bwmode;
  1605. bw40sc = pmlmeext->cur_ch_offset;
  1606. /* decide 80 band width offset */
  1607. if (bw == CHANNEL_WIDTH_80) {
  1608. u8 center_ch = rtw_get_center_ch(chidx, bw, bw40sc);
  1609. if (center_ch > chidx)
  1610. bw80sc = HAL_PRIME_CHNL_OFFSET_LOWER;
  1611. else if (center_ch < chidx)
  1612. bw80sc = HAL_PRIME_CHNL_OFFSET_UPPER;
  1613. else
  1614. bw80sc = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
  1615. } else
  1616. bw80sc = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
  1617. duration = mccadapriv->mcc_duration;
  1618. role = mccadapriv->role;
  1619. incurch = _FALSE;
  1620. if (IS_HARDWARE_TYPE_8812(padapter))
  1621. rfetype = pHalData->rfe_type; /* RFETYPE (only for 8812)*/
  1622. else
  1623. rfetype = 0;
  1624. /* STA/GC TX NULL data to inform AP/GC for ps mode */
  1625. switch (role) {
  1626. case MCC_ROLE_GO:
  1627. case MCC_ROLE_AP:
  1628. distxnull = MCC_DISABLE_TX_NULL;
  1629. break;
  1630. case MCC_ROLE_GC:
  1631. case MCC_ROLE_STA:
  1632. distxnull = MCC_ENABLE_TX_NULL;
  1633. break;
  1634. }
  1635. c2hrpt = MCC_C2H_REPORT_ALL_STATUS;
  1636. chscan = MCC_CHIDX;
  1637. SET_H2CCMD_MCC_CTRL_ORDER(cmd, order);
  1638. SET_H2CCMD_MCC_CTRL_TOTALNUM(cmd, totalnum);
  1639. SET_H2CCMD_MCC_CTRL_CHIDX(cmd, chidx);
  1640. SET_H2CCMD_MCC_CTRL_BW(cmd, bw);
  1641. SET_H2CCMD_MCC_CTRL_BW40SC(cmd, bw40sc);
  1642. SET_H2CCMD_MCC_CTRL_BW80SC(cmd, bw80sc);
  1643. SET_H2CCMD_MCC_CTRL_DURATION(cmd, duration);
  1644. SET_H2CCMD_MCC_CTRL_ROLE(cmd, role);
  1645. SET_H2CCMD_MCC_CTRL_INCURCH(cmd, incurch);
  1646. SET_H2CCMD_MCC_CTRL_RFETYPE(cmd, rfetype);
  1647. SET_H2CCMD_MCC_CTRL_DISTXNULL(cmd, distxnull);
  1648. SET_H2CCMD_MCC_CTRL_C2HRPT(cmd, c2hrpt);
  1649. SET_H2CCMD_MCC_CTRL_CHSCAN(cmd, chscan);
  1650. #ifdef CONFIG_MCC_MODE_DEBUG
  1651. RTW_INFO("=========================\n");
  1652. RTW_INFO(FUNC_ADPT_FMT" MCC INFO:\n", FUNC_ADPT_ARG(iface));
  1653. RTW_INFO("cmd[0]:0x%02x\n", cmd[0]);
  1654. RTW_INFO("cmd[1]:0x%02x\n", cmd[1]);
  1655. RTW_INFO("cmd[2]:0x%02x\n", cmd[2]);
  1656. RTW_INFO("cmd[3]:0x%02x\n", cmd[3]);
  1657. RTW_INFO("cmd[4]:0x%02x\n", cmd[4]);
  1658. RTW_INFO("cmd[5]:0x%02x\n", cmd[5]);
  1659. RTW_INFO("cmd[6]:0x%02x\n", cmd[6]);
  1660. RTW_INFO("=========================\n");
  1661. #endif /* CONFIG_MCC_MODE_DEBUG */
  1662. rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_CTRL, H2C_MCC_CTRL_LEN, cmd);
  1663. }
  1664. }
  1665. #endif
  1666. static void rtw_hal_set_mcc_ctrl_cmd(PADAPTER padapter, u8 stop)
  1667. {
  1668. #ifdef CONFIG_MCC_MODE_V2
  1669. /* new cmd 0x17 */
  1670. rtw_hal_set_mcc_ctrl_cmd_v2(padapter, stop);
  1671. #else
  1672. /* old cmd 0x18 */
  1673. rtw_hal_set_mcc_ctrl_cmd_v1(padapter, stop);
  1674. #endif
  1675. }
  1676. static u8 check_mcc_support(PADAPTER adapter)
  1677. {
  1678. struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
  1679. u8 sta_linking_num = DEV_STA_LG_NUM(dvobj);
  1680. u8 sta_linked_num = DEV_STA_LD_NUM(dvobj);
  1681. u8 starting_ap_num = DEV_AP_STARTING_NUM(dvobj);
  1682. u8 ap_num = DEV_AP_NUM(dvobj);
  1683. u8 ret = _SUCCESS;
  1684. /* case for linking sta + linked sta */
  1685. if ((sta_linking_num + sta_linked_num) != MAX_MCC_NUM) {
  1686. ret = _FAIL;
  1687. goto exit;
  1688. }
  1689. /* case for starting AP + linked sta */
  1690. if ((starting_ap_num + sta_linked_num) != MAX_MCC_NUM) {
  1691. ret = _FAIL;
  1692. goto exit;
  1693. }
  1694. /* case for linking sta + started AP */
  1695. if ((sta_linking_num + ap_num) != MAX_MCC_NUM) {
  1696. ret = _FAIL;
  1697. goto exit;
  1698. }
  1699. /* case for starting AP + started AP */
  1700. if ((starting_ap_num + ap_num) != MAX_MCC_NUM) {
  1701. ret = _FAIL;
  1702. goto exit;
  1703. }
  1704. exit:
  1705. return ret;
  1706. }
  1707. static void rtw_hal_mcc_start_prehdl(PADAPTER padapter)
  1708. {
  1709. struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
  1710. _adapter *iface = NULL;
  1711. struct mcc_adapter_priv *mccadapriv = NULL;
  1712. u8 i = 1;
  1713. for (i = 0; i < dvobj->iface_nums; i++) {
  1714. iface = dvobj->padapters[i];
  1715. if (iface == NULL)
  1716. continue;
  1717. mccadapriv = &iface->mcc_adapterpriv;
  1718. mccadapriv->role = MCC_ROLE_MAX;
  1719. }
  1720. }
  1721. static u8 rtw_hal_set_mcc_start_setting(PADAPTER padapter, u8 status)
  1722. {
  1723. u8 ret = _SUCCESS, enable_tsf_auto_sync = _FALSE;
  1724. struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
  1725. struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
  1726. if (pwrpriv->pwr_mode != PS_MODE_ACTIVE) {
  1727. rtw_warn_on(1);
  1728. RTW_INFO("PS mode is not active before start mcc, force exit ps mode\n");
  1729. LeaveAllPowerSaveModeDirect(padapter);
  1730. }
  1731. if (check_mcc_support(padapter)) {
  1732. RTW_INFO("%s: check_mcc_support fail\n", __func__);
  1733. dump_dvobj_mi_status(RTW_DBGDUMP, __func__, padapter);
  1734. ret = _FAIL;
  1735. goto exit;
  1736. }
  1737. rtw_hal_mcc_start_prehdl(padapter);
  1738. /* configure mcc switch channel setting */
  1739. rtw_hal_config_mcc_switch_channel_setting(padapter);
  1740. if (rtw_hal_decide_mcc_role(padapter) == _FAIL) {
  1741. ret = _FAIL;
  1742. goto exit;
  1743. }
  1744. /* set mcc status to indicate process mcc start setting */
  1745. rtw_hal_set_mcc_status(padapter, MCC_STATUS_PROCESS_MCC_START_SETTING);
  1746. /* only download rsvd page for connect */
  1747. if (status == MCC_SETCMD_STATUS_START_CONNECT) {
  1748. /* download mcc rsvd page */
  1749. rtw_hal_set_fw_mcc_rsvd_page(padapter);
  1750. rtw_hal_set_mcc_rsvdpage_cmd(padapter);
  1751. }
  1752. /* configure time setting */
  1753. rtw_hal_set_mcc_time_setting_cmd(padapter);
  1754. #ifndef CONFIG_MCC_MODE_V2
  1755. /* IQK value offload */
  1756. rtw_hal_set_mcc_IQK_offload_cmd(padapter);
  1757. #endif
  1758. /* set mac id to fw */
  1759. rtw_hal_set_mcc_macid_cmd(padapter);
  1760. if (dvobj->p0_tsf.sync_port != MAX_HW_PORT ) {
  1761. /* disable tsf auto sync */
  1762. RTW_INFO("[MCC] disable HW TSF sync\n");
  1763. rtw_hal_set_hwreg(padapter, HW_VAR_TSF_AUTO_SYNC, &enable_tsf_auto_sync);
  1764. } else {
  1765. RTW_INFO("[MCC] already disable HW TSF sync\n");
  1766. }
  1767. /* set mcc parameter */
  1768. rtw_hal_set_mcc_ctrl_cmd(padapter, _FALSE);
  1769. exit:
  1770. return ret;
  1771. }
  1772. static void rtw_hal_set_mcc_stop_setting(PADAPTER padapter, u8 status)
  1773. {
  1774. struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
  1775. struct mcc_obj_priv *mccobjpriv = &dvobj->mcc_objpriv;
  1776. _adapter *iface = NULL;
  1777. struct mcc_adapter_priv *mccadapriv = NULL;
  1778. u8 i = 0;
  1779. /*
  1780. * when adapter disconnect, stop mcc mod
  1781. * total=0xf means stop mcc mode
  1782. */
  1783. switch (status) {
  1784. default:
  1785. /* let fw switch to other interface channel */
  1786. for (i = 0; i < MAX_MCC_NUM; i++) {
  1787. iface = mccobjpriv->iface[i];
  1788. if (iface == NULL)
  1789. continue;
  1790. mccadapriv = &iface->mcc_adapterpriv;
  1791. /* use other interface to set cmd */
  1792. if (iface != padapter) {
  1793. rtw_hal_set_mcc_ctrl_cmd(iface, _TRUE);
  1794. break;
  1795. }
  1796. }
  1797. break;
  1798. }
  1799. }
  1800. static void rtw_hal_mcc_status_hdl(PADAPTER padapter, u8 status)
  1801. {
  1802. switch (status) {
  1803. case MCC_SETCMD_STATUS_STOP_DISCONNECT:
  1804. rtw_hal_clear_mcc_status(padapter, MCC_STATUS_NEED_MCC | MCC_STATUS_DOING_MCC);
  1805. break;
  1806. case MCC_SETCMD_STATUS_STOP_SCAN_START:
  1807. rtw_hal_set_mcc_status(padapter, MCC_STATUS_NEED_MCC);
  1808. rtw_hal_clear_mcc_status(padapter, MCC_STATUS_DOING_MCC);
  1809. break;
  1810. case MCC_SETCMD_STATUS_START_CONNECT:
  1811. case MCC_SETCMD_STATUS_START_SCAN_DONE:
  1812. rtw_hal_set_mcc_status(padapter, MCC_STATUS_NEED_MCC | MCC_STATUS_DOING_MCC);
  1813. break;
  1814. default:
  1815. RTW_INFO(FUNC_ADPT_FMT" error status(%d)\n", FUNC_ADPT_ARG(padapter), status);
  1816. break;
  1817. }
  1818. }
  1819. static void rtw_hal_mcc_stop_posthdl(PADAPTER padapter)
  1820. {
  1821. struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
  1822. struct mcc_obj_priv *mccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
  1823. struct mcc_adapter_priv *mccadapriv = NULL;
  1824. _adapter *iface = NULL;
  1825. PHAL_DATA_TYPE hal;
  1826. struct dm_struct *p_dm_odm;
  1827. u8 i = 0;
  1828. u8 enable_rx_bar = _FALSE;
  1829. for (i = 0; i < MAX_MCC_NUM; i++) {
  1830. iface = mccobjpriv->iface[i];
  1831. if (iface == NULL)
  1832. continue;
  1833. /* release network queue */
  1834. rtw_netif_wake_queue(iface->pnetdev);
  1835. mccadapriv = &iface->mcc_adapterpriv;
  1836. mccadapriv->mcc_tx_bytes_from_kernel = 0;
  1837. mccadapriv->mcc_last_tx_bytes_from_kernel = 0;
  1838. mccadapriv->mcc_tx_bytes_to_port = 0;
  1839. if (mccadapriv->role == MCC_ROLE_GO)
  1840. rtw_hal_mcc_remove_go_p2p_ie(iface);
  1841. #ifdef CONFIG_TDLS
  1842. if (MLME_IS_STA(iface)) {
  1843. if (mccadapriv->backup_tdls_en) {
  1844. rtw_enable_tdls_func(iface);
  1845. RTW_INFO("%s: Disable MCC, Enable TDLS\n", __func__);
  1846. mccadapriv->backup_tdls_en = _FALSE;
  1847. }
  1848. }
  1849. #endif /* CONFIG_TDLS */
  1850. mccadapriv->role = MCC_ROLE_MAX;
  1851. mccobjpriv->iface[i] = NULL;
  1852. }
  1853. hal = GET_HAL_DATA(padapter);
  1854. p_dm_odm = &hal->odmpriv;
  1855. phydm_dm_early_init(p_dm_odm);
  1856. /* force switch channel */
  1857. hal->current_channel = 0;
  1858. hal->current_channel_bw = CHANNEL_WIDTH_MAX;
  1859. }
  1860. static void rtw_hal_mcc_start_posthdl(PADAPTER padapter)
  1861. {
  1862. struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
  1863. struct mcc_obj_priv *mccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
  1864. struct mcc_adapter_priv *mccadapriv = NULL;
  1865. _adapter *iface = NULL;
  1866. PHAL_DATA_TYPE hal;
  1867. struct dm_struct *p_dm_odm;
  1868. struct _hal_rf_ *p_rf;
  1869. u32 support_ability = 0;
  1870. u8 i = 0;
  1871. u8 enable_rx_bar = _TRUE;
  1872. for (i = 0; i < dvobj->iface_nums; i++) {
  1873. iface = dvobj->padapters[i];
  1874. if (iface == NULL)
  1875. continue;
  1876. mccadapriv = &iface->mcc_adapterpriv;
  1877. if (mccadapriv->role == MCC_ROLE_MAX)
  1878. continue;
  1879. mccadapriv->mcc_tx_bytes_from_kernel = 0;
  1880. mccadapriv->mcc_last_tx_bytes_from_kernel = 0;
  1881. mccadapriv->mcc_tx_bytes_to_port = 0;
  1882. #ifdef CONFIG_TDLS
  1883. if (MLME_IS_STA(iface)) {
  1884. if (rtw_is_tdls_enabled(iface)) {
  1885. mccadapriv->backup_tdls_en = _TRUE;
  1886. rtw_disable_tdls_func(iface, _TRUE);
  1887. RTW_INFO("%s: Enable MCC, Disable TDLS\n", __func__);
  1888. }
  1889. }
  1890. #endif /* CONFIG_TDLS */
  1891. }
  1892. hal = GET_HAL_DATA(padapter);
  1893. p_dm_odm = &hal->odmpriv;
  1894. p_rf = &(p_dm_odm->rf_table);
  1895. mccobjpriv->backup_phydm_ability = p_rf->rf_supportability;
  1896. p_rf->rf_supportability = p_rf->rf_supportability & (~HAL_RF_TX_PWR_TRACK) & (~HAL_RF_IQK);
  1897. }
  1898. /*
  1899. * rtw_hal_set_mcc_setting - set mcc setting
  1900. * @padapter: currnet padapter to stop/start MCC
  1901. * @stop: stop mcc or not
  1902. * @return val: 1 for SUCCESS, 0 for fail
  1903. */
  1904. static u8 rtw_hal_set_mcc_setting(PADAPTER padapter, u8 status)
  1905. {
  1906. u8 ret = _FAIL;
  1907. struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
  1908. u8 stop = (status < MCC_SETCMD_STATUS_START_CONNECT) ? _TRUE : _FALSE;
  1909. u32 start_time = rtw_get_current_time();
  1910. RTW_INFO("===> "FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
  1911. rtw_sctx_init(&pmccobjpriv->mcc_sctx, MCC_EXPIRE_TIME);
  1912. pmccobjpriv->mcc_c2h_status = MCC_RPT_MAX;
  1913. if (stop == _FALSE) {
  1914. /* handle mcc start */
  1915. if (rtw_hal_set_mcc_start_setting(padapter, status) == _FAIL)
  1916. goto exit;
  1917. /* wait for C2H */
  1918. if (!rtw_sctx_wait(&pmccobjpriv->mcc_sctx, __func__))
  1919. RTW_INFO(FUNC_ADPT_FMT": wait for mcc start C2H time out\n", FUNC_ADPT_ARG(padapter));
  1920. else
  1921. ret = _SUCCESS;
  1922. if (ret == _SUCCESS) {
  1923. RTW_INFO(FUNC_ADPT_FMT": mcc start sucecssfully\n", FUNC_ADPT_ARG(padapter));
  1924. rtw_hal_mcc_status_hdl(padapter, status);
  1925. rtw_hal_mcc_start_posthdl(padapter);
  1926. }
  1927. } else {
  1928. /* set mcc status to indicate process mcc start setting */
  1929. rtw_hal_set_mcc_status(padapter, MCC_STATUS_PROCESS_MCC_STOP_SETTING);
  1930. /* handle mcc stop */
  1931. rtw_hal_set_mcc_stop_setting(padapter, status);
  1932. /* wait for C2H */
  1933. if (!rtw_sctx_wait(&pmccobjpriv->mcc_sctx, __func__))
  1934. RTW_INFO(FUNC_ADPT_FMT": wait for mcc stop C2H time out\n", FUNC_ADPT_ARG(padapter));
  1935. else {
  1936. ret = _SUCCESS;
  1937. rtw_hal_mcc_status_hdl(padapter, status);
  1938. rtw_hal_mcc_stop_posthdl(padapter);
  1939. }
  1940. }
  1941. exit:
  1942. /* clear mcc status */
  1943. rtw_hal_clear_mcc_status(padapter
  1944. , MCC_STATUS_PROCESS_MCC_START_SETTING | MCC_STATUS_PROCESS_MCC_STOP_SETTING);
  1945. RTW_INFO(FUNC_ADPT_FMT" in %dms <===\n"
  1946. , FUNC_ADPT_ARG(padapter), rtw_get_passing_time_ms(start_time));
  1947. return ret;
  1948. }
  1949. /**
  1950. * rtw_hal_mcc_check_case_not_limit_traffic - handler flow ctrl for special case
  1951. * @cur_iface: fw stay channel setting of this iface
  1952. * @next_iface: fw will swich channel setting of this iface
  1953. */
  1954. static void rtw_hal_mcc_check_case_not_limit_traffic(PADAPTER cur_iface, PADAPTER next_iface)
  1955. {
  1956. u8 cur_bw = cur_iface->mlmeextpriv.cur_bwmode;
  1957. u8 next_bw = next_iface->mlmeextpriv.cur_bwmode;
  1958. /* for both interface are VHT80, doesn't limit_traffic according to iperf results */
  1959. if (cur_bw == CHANNEL_WIDTH_80 && next_bw == CHANNEL_WIDTH_80) {
  1960. cur_iface->mcc_adapterpriv.mcc_tp_limit = _FALSE;
  1961. next_iface->mcc_adapterpriv.mcc_tp_limit = _FALSE;
  1962. }
  1963. }
  1964. /**
  1965. * rtw_hal_mcc_sw_ch_fw_notify_hdl - handler flow ctrl
  1966. */
  1967. static void rtw_hal_mcc_sw_ch_fw_notify_hdl(PADAPTER padapter)
  1968. {
  1969. struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
  1970. struct mcc_obj_priv *pmccobjpriv = &(pdvobjpriv->mcc_objpriv);
  1971. struct mcc_adapter_priv *cur_mccadapriv = NULL, *next_mccadapriv = NULL;
  1972. _adapter *iface = NULL, *cur_iface = NULL, *next_iface = NULL;
  1973. struct registry_priv *preg = &padapter->registrypriv;
  1974. u8 cur_op_ch = pdvobjpriv->oper_channel;
  1975. u8 i = 0, iface_num = pdvobjpriv->iface_nums, cur_order = 0, next_order = 0;
  1976. static u8 cnt = 1;
  1977. u32 single_tx_cri = preg->rtw_mcc_single_tx_cri;
  1978. for (i = 0; i < iface_num; i++) {
  1979. iface = pdvobjpriv->padapters[i];
  1980. if (iface == NULL)
  1981. continue;
  1982. if (cur_op_ch == iface->mlmeextpriv.cur_channel) {
  1983. cur_iface = iface;
  1984. cur_mccadapriv = &cur_iface->mcc_adapterpriv;
  1985. cur_order = cur_mccadapriv->order;
  1986. next_order = (cur_order + 1) % iface_num;
  1987. next_iface = pmccobjpriv->iface[next_order];
  1988. next_mccadapriv = &next_iface->mcc_adapterpriv;
  1989. break;
  1990. }
  1991. }
  1992. if (cur_iface == NULL || next_iface == NULL) {
  1993. RTW_ERR("cur_iface=%p,next_iface=%p\n", cur_iface, next_iface);
  1994. rtw_warn_on(1);
  1995. return;
  1996. }
  1997. /* check other interface tx busy traffic or not under every 2 switch channel notify(Mbits/100ms) */
  1998. if (cnt == 2) {
  1999. cur_mccadapriv->mcc_tp = (cur_mccadapriv->mcc_tx_bytes_from_kernel
  2000. - cur_mccadapriv->mcc_last_tx_bytes_from_kernel) * 10 * 8 / 1024 / 1024;
  2001. cur_mccadapriv->mcc_last_tx_bytes_from_kernel = cur_mccadapriv->mcc_tx_bytes_from_kernel;
  2002. next_mccadapriv->mcc_tp = (next_mccadapriv->mcc_tx_bytes_from_kernel
  2003. - next_mccadapriv->mcc_last_tx_bytes_from_kernel) * 10 * 8 / 1024 / 1024;
  2004. next_mccadapriv->mcc_last_tx_bytes_from_kernel = next_mccadapriv->mcc_tx_bytes_from_kernel;
  2005. cnt = 1;
  2006. } else
  2007. cnt = 2;
  2008. /* check single TX or cuncurrnet TX */
  2009. if (next_mccadapriv->mcc_tp < single_tx_cri) {
  2010. /* single TX, does not stop */
  2011. cur_mccadapriv->mcc_tx_stop = _FALSE;
  2012. cur_mccadapriv->mcc_tp_limit = _FALSE;
  2013. } else {
  2014. /* concurrent TX, stop */
  2015. cur_mccadapriv->mcc_tx_stop = _TRUE;
  2016. cur_mccadapriv->mcc_tp_limit = _TRUE;
  2017. }
  2018. if (cur_mccadapriv->mcc_tp < single_tx_cri) {
  2019. next_mccadapriv->mcc_tx_stop = _FALSE;
  2020. next_mccadapriv->mcc_tp_limit = _FALSE;
  2021. } else {
  2022. next_mccadapriv->mcc_tx_stop = _FALSE;
  2023. next_mccadapriv->mcc_tp_limit = _TRUE;
  2024. next_mccadapriv->mcc_tx_bytes_to_port = 0;
  2025. }
  2026. /* stop current iface kernel queue or not */
  2027. if (cur_mccadapriv->mcc_tx_stop)
  2028. rtw_netif_stop_queue(cur_iface->pnetdev);
  2029. else
  2030. rtw_netif_wake_queue(cur_iface->pnetdev);
  2031. /* stop next iface kernel queue or not */
  2032. if (next_mccadapriv->mcc_tx_stop)
  2033. rtw_netif_stop_queue(next_iface->pnetdev);
  2034. else
  2035. rtw_netif_wake_queue(next_iface->pnetdev);
  2036. /* start xmit tasklet */
  2037. rtw_os_xmit_schedule(next_iface);
  2038. rtw_hal_mcc_check_case_not_limit_traffic(cur_iface, next_iface);
  2039. if (0) {
  2040. RTW_INFO("order:%d, mcc_tx_stop:%d, mcc_tp:%d\n",
  2041. cur_mccadapriv->order, cur_mccadapriv->mcc_tx_stop, cur_mccadapriv->mcc_tp);
  2042. dump_os_queue(0, cur_iface);
  2043. RTW_INFO("order:%d, mcc_tx_stop:%d, mcc_tp:%d\n",
  2044. next_mccadapriv->order, next_mccadapriv->mcc_tx_stop, next_mccadapriv->mcc_tp);
  2045. dump_os_queue(0, next_iface);
  2046. }
  2047. }
  2048. static void rtw_hal_mcc_update_noa_start_time_hdl(PADAPTER padapter, u8 buflen, u8 *tmpBuf)
  2049. {
  2050. struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
  2051. struct mcc_obj_priv *pmccobjpriv = &(pdvobjpriv->mcc_objpriv);
  2052. struct mcc_adapter_priv *pmccadapriv = NULL;
  2053. PADAPTER iface = NULL;
  2054. u8 i = 0;
  2055. u8 policy_idx = pmccobjpriv->policy_index;
  2056. u8 noa_tsf_sync_offset = mcc_switch_channel_policy_table[policy_idx][MCC_TSF_SYNC_OFFSET_IDX];
  2057. u8 noa_start_time_offset = mcc_switch_channel_policy_table[policy_idx][MCC_START_TIME_OFFSET_IDX];
  2058. for (i = 0; i < pdvobjpriv->iface_nums; i++) {
  2059. iface = pdvobjpriv->padapters[i];
  2060. if (iface == NULL)
  2061. continue;
  2062. pmccadapriv = &iface->mcc_adapterpriv;
  2063. if (pmccadapriv->role == MCC_ROLE_MAX)
  2064. continue;
  2065. /* GO & channel match */
  2066. if (pmccadapriv->role == MCC_ROLE_GO) {
  2067. /* convert GO TBTT from FW to noa_start_time(TU convert to mircosecond) */
  2068. pmccadapriv->noa_start_time = RTW_GET_LE32(tmpBuf + 2) + noa_start_time_offset * TU;
  2069. if (0) {
  2070. RTW_INFO("TBTT:0x%02x\n", RTW_GET_LE32(tmpBuf + 2));
  2071. RTW_INFO("noa_tsf_sync_offset:%d, noa_start_time_offset:%d\n", noa_tsf_sync_offset, noa_start_time_offset);
  2072. RTW_INFO(FUNC_ADPT_FMT"buf=0x%02x:0x%02x:0x%02x:0x%02x, noa_start_time=0x%02x\n"
  2073. , FUNC_ADPT_ARG(iface)
  2074. , tmpBuf[2]
  2075. , tmpBuf[3]
  2076. , tmpBuf[4]
  2077. , tmpBuf[5]
  2078. ,pmccadapriv->noa_start_time);
  2079. }
  2080. rtw_hal_mcc_update_go_p2p_ie(iface);
  2081. break;
  2082. }
  2083. }
  2084. }
  2085. static void rtw_hal_mcc_rpt_tsf_hdl(PADAPTER padapter, u8 buflen, u8 *tmpBuf)
  2086. {
  2087. struct dvobj_priv *dvobjpriv = adapter_to_dvobj(padapter);
  2088. struct mcc_obj_priv *mccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
  2089. struct submit_ctx *mcc_tsf_req_sctx = &mccobjpriv->mcc_tsf_req_sctx;
  2090. struct mcc_adapter_priv *mccadapriv = NULL;
  2091. _adapter *iface = NULL;
  2092. u8 order = 0;
  2093. order = mccobjpriv->mcc_tsf_req_sctx_order;
  2094. iface = mccobjpriv->iface[order];
  2095. mccadapriv = &iface->mcc_adapterpriv;
  2096. mccadapriv->tsf = RTW_GET_LE64(tmpBuf + 2);
  2097. if (0)
  2098. RTW_INFO(FUNC_ADPT_FMT" TSF(order:%d):0x%02llx\n", FUNC_ADPT_ARG(iface), mccadapriv->order, mccadapriv->tsf);
  2099. if (mccadapriv->order == (MAX_MCC_NUM - 1))
  2100. rtw_sctx_done(&mcc_tsf_req_sctx);
  2101. else
  2102. mccobjpriv->mcc_tsf_req_sctx_order ++;
  2103. }
  2104. /**
  2105. * rtw_hal_mcc_c2h_handler - mcc c2h handler
  2106. */
  2107. void rtw_hal_mcc_c2h_handler(PADAPTER padapter, u8 buflen, u8 *tmpBuf)
  2108. {
  2109. struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
  2110. struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
  2111. struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
  2112. struct submit_ctx *mcc_sctx = &pmccobjpriv->mcc_sctx;
  2113. _adapter *cur_adapter = NULL;
  2114. u8 cur_ch = 0, cur_bw = 0, cur_ch_offset = 0;
  2115. _irqL irqL;
  2116. /* RTW_INFO("[length]=%d, [C2H data]="MAC_FMT"\n", buflen, MAC_ARG(tmpBuf)); */
  2117. /* To avoid reg is set, but driver recive c2h to set wrong oper_channel */
  2118. if (MCC_RPT_STOPMCC == pmccobjpriv->mcc_c2h_status) {
  2119. RTW_INFO(FUNC_ADPT_FMT" MCC alread stops return\n", FUNC_ADPT_ARG(padapter));
  2120. return;
  2121. }
  2122. pmccobjpriv->mcc_c2h_status = tmpBuf[0];
  2123. pmccobjpriv->current_order = tmpBuf[1];
  2124. cur_adapter = pmccobjpriv->iface[pmccobjpriv->current_order];
  2125. cur_ch = cur_adapter->mlmeextpriv.cur_channel;
  2126. cur_bw = cur_adapter->mlmeextpriv.cur_bwmode;
  2127. cur_ch_offset = cur_adapter->mlmeextpriv.cur_ch_offset;
  2128. rtw_set_oper_ch(cur_adapter, cur_ch);
  2129. rtw_set_oper_bw(cur_adapter, cur_bw);
  2130. rtw_set_oper_choffset(cur_adapter, cur_ch_offset);
  2131. if (0)
  2132. RTW_INFO("%d,order:%d,TSF:0x%llx\n", tmpBuf[0], tmpBuf[1], RTW_GET_LE64(tmpBuf + 2));
  2133. switch (pmccobjpriv->mcc_c2h_status) {
  2134. case MCC_RPT_SUCCESS:
  2135. _enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
  2136. pmccobjpriv->cur_mcc_success_cnt++;
  2137. rtw_hal_mcc_upadate_chnl_bw(cur_adapter, cur_ch, cur_ch_offset, cur_bw, _FALSE);
  2138. _exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
  2139. break;
  2140. case MCC_RPT_TXNULL_FAIL:
  2141. RTW_INFO("[MCC] TXNULL FAIL\n");
  2142. break;
  2143. case MCC_RPT_STOPMCC:
  2144. RTW_INFO("[MCC] MCC stop\n");
  2145. pmccobjpriv->mcc_c2h_status = MCC_RPT_STOPMCC;
  2146. rtw_hal_mcc_upadate_chnl_bw(cur_adapter, cur_ch, cur_ch_offset, cur_bw, _TRUE);
  2147. rtw_sctx_done(&mcc_sctx);
  2148. break;
  2149. case MCC_RPT_READY:
  2150. _enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
  2151. /* initialize counter & time */
  2152. pmccobjpriv->mcc_launch_time = rtw_get_current_time();
  2153. pmccobjpriv->mcc_c2h_status = MCC_RPT_READY;
  2154. pmccobjpriv->cur_mcc_success_cnt = 0;
  2155. pmccobjpriv->prev_mcc_success_cnt = 0;
  2156. pmccobjpriv->mcc_tolerance_time = MCC_TOLERANCE_TIME;
  2157. _exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
  2158. RTW_INFO("[MCC] MCC ready\n");
  2159. rtw_sctx_done(&mcc_sctx);
  2160. break;
  2161. case MCC_RPT_SWICH_CHANNEL_NOTIFY:
  2162. rtw_hal_mcc_sw_ch_fw_notify_hdl(padapter);
  2163. break;
  2164. case MCC_RPT_UPDATE_NOA_START_TIME:
  2165. rtw_hal_mcc_update_noa_start_time_hdl(padapter, buflen, tmpBuf);
  2166. break;
  2167. case MCC_RPT_TSF:
  2168. _enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
  2169. rtw_hal_mcc_rpt_tsf_hdl(padapter, buflen, tmpBuf);
  2170. _exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
  2171. break;
  2172. default:
  2173. /* RTW_INFO("[MCC] Other MCC status(%d)\n", pmccobjpriv->mcc_c2h_status); */
  2174. break;
  2175. }
  2176. }
  2177. void rtw_hal_mcc_update_parameter(PADAPTER padapter, u8 force_update)
  2178. {
  2179. struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
  2180. struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
  2181. u8 cmd[H2C_MCC_TIME_SETTING_LEN] = {0};
  2182. u8 swchannel_early_time = MCC_SWCH_FW_EARLY_TIME;
  2183. u8 ap_num = DEV_AP_NUM(dvobj);
  2184. if (ap_num == 0) {
  2185. u8 need_update = _FALSE;
  2186. u8 start_time_offset = 0, interval = 0, duration = 0;
  2187. need_update = rtw_hal_mcc_update_timing_parameters(padapter, force_update);
  2188. if (need_update == _FALSE)
  2189. return;
  2190. start_time_offset = mccobjpriv->start_time;
  2191. interval = mccobjpriv->interval;
  2192. duration = mccobjpriv->iface[0]->mcc_adapterpriv.mcc_duration;
  2193. SET_H2CCMD_MCC_TIME_SETTING_START_TIME(cmd, start_time_offset);
  2194. SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(cmd, interval);
  2195. SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(cmd, swchannel_early_time);
  2196. SET_H2CCMD_MCC_TIME_SETTING_UPDATE(cmd, _TRUE);
  2197. SET_H2CCMD_MCC_TIME_SETTING_ORDER0_DURATION(cmd, duration);
  2198. } else {
  2199. PADAPTER order0_iface = NULL;
  2200. PADAPTER order1_iface = NULL;
  2201. u8 policy_idx = mccobjpriv->policy_index;
  2202. u8 duration = mcc_switch_channel_policy_table[policy_idx][MCC_DURATION_IDX];
  2203. u8 tsf_sync_offset = mcc_switch_channel_policy_table[policy_idx][MCC_TSF_SYNC_OFFSET_IDX];
  2204. u8 start_time_offset = mcc_switch_channel_policy_table[policy_idx][MCC_START_TIME_OFFSET_IDX];
  2205. u8 interval = mcc_switch_channel_policy_table[policy_idx][MCC_INTERVAL_IDX];
  2206. u8 guard_offset0 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET0_IDX];
  2207. u8 guard_offset1 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET1_IDX];
  2208. u8 order0_duration = 0;
  2209. u8 i = 0;
  2210. enum _hw_port tsf_bsae_port = MAX_HW_PORT;
  2211. enum _hw_port tsf_sync_port = MAX_HW_PORT;
  2212. RTW_INFO("%s: policy_idx=%d\n", __func__, policy_idx);
  2213. order0_iface = mccobjpriv->iface[0];
  2214. order1_iface = mccobjpriv->iface[1];
  2215. /* GO/AP is order 0, GC/STA is order 1 */
  2216. order0_duration = order0_iface->mcc_adapterpriv.mcc_duration = interval - duration;
  2217. order0_iface->mcc_adapterpriv.mcc_duration = duration;
  2218. tsf_bsae_port = rtw_hal_get_port(order1_iface);
  2219. tsf_sync_port = rtw_hal_get_port(order0_iface);
  2220. /* update IE */
  2221. for (i = 0; i < dvobj->iface_nums; i++) {
  2222. PADAPTER iface = NULL;
  2223. struct mcc_adapter_priv *mccadapriv = NULL;
  2224. iface = dvobj->padapters[i];
  2225. if (iface == NULL)
  2226. continue;
  2227. mccadapriv = &iface->mcc_adapterpriv;
  2228. if (mccadapriv->role == MCC_ROLE_MAX)
  2229. continue;
  2230. if (mccadapriv->role == MCC_ROLE_GO)
  2231. rtw_hal_mcc_update_go_p2p_ie(iface);
  2232. }
  2233. /* update H2C cmd */
  2234. /* FW set enable */
  2235. SET_H2CCMD_MCC_TIME_SETTING_FW_EN(cmd, _TRUE);
  2236. /* TSF Sync offset */
  2237. SET_H2CCMD_MCC_TIME_SETTING_TSF_SYNC_OFFSET(cmd, tsf_sync_offset);
  2238. /* start time offset */
  2239. SET_H2CCMD_MCC_TIME_SETTING_START_TIME(cmd, (start_time_offset + guard_offset0));
  2240. /* interval */
  2241. SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(cmd, interval);
  2242. /* Early time to inform driver by C2H before switch channel */
  2243. SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(cmd, swchannel_early_time);
  2244. /* Port0 sync from Port1, not support multi-port */
  2245. SET_H2CCMD_MCC_TIME_SETTING_ORDER_BASE(cmd, tsf_bsae_port);
  2246. SET_H2CCMD_MCC_TIME_SETTING_ORDER_SYNC(cmd, tsf_sync_port);
  2247. SET_H2CCMD_MCC_TIME_SETTING_UPDATE(cmd, _TRUE);
  2248. SET_H2CCMD_MCC_TIME_SETTING_ORDER0_DURATION(cmd, order0_duration);
  2249. }
  2250. rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_TIME_SETTING, H2C_MCC_TIME_SETTING_LEN, cmd);
  2251. }
  2252. /**
  2253. * rtw_hal_mcc_sw_status_check - check mcc swich channel status
  2254. * @padapter: primary adapter
  2255. */
  2256. void rtw_hal_mcc_sw_status_check(PADAPTER padapter)
  2257. {
  2258. struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
  2259. struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
  2260. struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
  2261. struct mcc_adapter_priv *mccadapriv = NULL;
  2262. _adapter *iface = NULL;
  2263. u8 cur_cnt = 0, prev_cnt = 0, diff_cnt = 0, check_ret = _FAIL, threshold = 0;
  2264. u8 policy_idx = pmccobjpriv->policy_index;
  2265. u8 noa_enable = _FALSE;
  2266. u8 i = 0;
  2267. _irqL irqL;
  2268. u8 ap_num = DEV_AP_NUM(dvobj);
  2269. /* #define MCC_RESTART 1 */
  2270. if (!MCC_EN(padapter))
  2271. return;
  2272. _enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
  2273. if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
  2274. /* check noa enable or not */
  2275. for (i = 0; i < dvobj->iface_nums; i++) {
  2276. iface = dvobj->padapters[i];
  2277. if (iface == NULL)
  2278. continue;
  2279. mccadapriv = &iface->mcc_adapterpriv;
  2280. if (mccadapriv->role == MCC_ROLE_MAX)
  2281. continue;
  2282. if (iface->wdinfo.p2p_ps_mode == P2P_PS_NOA) {
  2283. noa_enable = _TRUE;
  2284. break;
  2285. }
  2286. }
  2287. if (!noa_enable && ap_num == 0)
  2288. rtw_hal_mcc_update_parameter(padapter, _FALSE);
  2289. threshold = pmccobjpriv->mcc_stop_threshold;
  2290. if (pwrpriv->pwr_mode != PS_MODE_ACTIVE) {
  2291. rtw_warn_on(1);
  2292. RTW_INFO("PS mode is not active under mcc, force exit ps mode\n");
  2293. LeaveAllPowerSaveModeDirect(padapter);
  2294. }
  2295. if (rtw_get_passing_time_ms(pmccobjpriv->mcc_launch_time) > 2000) {
  2296. _enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
  2297. cur_cnt = pmccobjpriv->cur_mcc_success_cnt;
  2298. prev_cnt = pmccobjpriv->prev_mcc_success_cnt;
  2299. if (cur_cnt < prev_cnt)
  2300. diff_cnt = (cur_cnt + 255) - prev_cnt;
  2301. else
  2302. diff_cnt = cur_cnt - prev_cnt;
  2303. if (diff_cnt < threshold) {
  2304. pmccobjpriv->mcc_tolerance_time--;
  2305. RTW_INFO("%s: diff_cnt:%d, tolerance_time:%d\n",
  2306. __func__, diff_cnt, pmccobjpriv->mcc_tolerance_time);
  2307. } else
  2308. pmccobjpriv->mcc_tolerance_time = MCC_TOLERANCE_TIME;
  2309. pmccobjpriv->prev_mcc_success_cnt = pmccobjpriv->cur_mcc_success_cnt;
  2310. if (pmccobjpriv->mcc_tolerance_time != 0)
  2311. check_ret = _SUCCESS;
  2312. _exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
  2313. if (check_ret != _SUCCESS) {
  2314. RTW_INFO("============ MCC swich channel check fail (%d)=============\n", diff_cnt);
  2315. /* restart MCC */
  2316. #ifdef MCC_RESTART
  2317. rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_STOP_DISCONNECT);
  2318. rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_CONNECT);
  2319. #endif /* MCC_RESTART */
  2320. }
  2321. } else {
  2322. _enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
  2323. pmccobjpriv->prev_mcc_success_cnt = pmccobjpriv->cur_mcc_success_cnt;
  2324. _exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
  2325. }
  2326. }
  2327. _exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
  2328. }
  2329. /**
  2330. * rtw_hal_mcc_change_scan_flag - change scan flag under mcc
  2331. *
  2332. * MCC mode under sitesurvey goto AP channel to tx bcn & data
  2333. * MCC mode under sitesurvey doesn't support TX data for station mode (FW not support)
  2334. *
  2335. * @padapter: the adapter to be change scan flag
  2336. * @ch: pointer to rerurn ch
  2337. * @bw: pointer to rerurn bw
  2338. * @offset: pointer to rerurn offset
  2339. */
  2340. u8 rtw_hal_mcc_change_scan_flag(PADAPTER padapter, u8 *ch, u8 *bw, u8 *offset)
  2341. {
  2342. u8 need_ch_setting_union = _TRUE, i = 0, flags = 0, back_op = _FALSE;
  2343. struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
  2344. struct mcc_adapter_priv *mccadapriv = NULL;
  2345. struct mlme_ext_priv *mlmeext = NULL;
  2346. _adapter *iface = NULL;
  2347. if (!MCC_EN(padapter))
  2348. goto exit;
  2349. if (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC))
  2350. goto exit;
  2351. /* disable PS_ANNC & TX_RESUME for all interface */
  2352. /* ToDo: TX_RESUME by interface in SCAN_BACKING_OP */
  2353. mlmeext = &padapter->mlmeextpriv;
  2354. flags = mlmeext_scan_backop_flags(mlmeext);
  2355. if (mlmeext_chk_scan_backop_flags(mlmeext, SS_BACKOP_PS_ANNC))
  2356. flags &= ~SS_BACKOP_PS_ANNC;
  2357. if (mlmeext_chk_scan_backop_flags(mlmeext, SS_BACKOP_TX_RESUME))
  2358. flags &= ~SS_BACKOP_TX_RESUME;
  2359. mlmeext_assign_scan_backop_flags(mlmeext, flags);
  2360. for (i = 0; i < dvobj->iface_nums; i++) {
  2361. iface = dvobj->padapters[i];
  2362. if (!iface)
  2363. continue;
  2364. mlmeext = &iface->mlmeextpriv;
  2365. if (MLME_IS_GO(iface) || MLME_IS_AP(iface))
  2366. back_op = _TRUE;
  2367. else if (MLME_IS_GC(iface) && (iface != padapter))
  2368. /* switch to another linked interface(GO) to receive beacon to avoid no beacon disconnect */
  2369. back_op = _TRUE;
  2370. else if (MLME_IS_STA(iface) && MLME_IS_ASOC(iface) && (iface != padapter))
  2371. /* switch to another linked interface(STA) to receive beacon to avoid no beacon disconnect */
  2372. back_op = _TRUE;
  2373. else {
  2374. /* bypass non-linked/non-linking interface/scan interface */
  2375. continue;
  2376. }
  2377. if (back_op) {
  2378. *ch = mlmeext->cur_channel;
  2379. *bw = mlmeext->cur_bwmode;
  2380. *offset = mlmeext->cur_ch_offset;
  2381. need_ch_setting_union = _FALSE;
  2382. }
  2383. }
  2384. exit:
  2385. return need_ch_setting_union;
  2386. }
  2387. /**
  2388. * rtw_hal_mcc_calc_tx_bytes_from_kernel - calculte tx bytes from kernel to check concurrent tx or not
  2389. * @padapter: the adapter to be record tx bytes
  2390. * @len: data len
  2391. */
  2392. inline void rtw_hal_mcc_calc_tx_bytes_from_kernel(PADAPTER padapter, u32 len)
  2393. {
  2394. struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
  2395. if (MCC_EN(padapter)) {
  2396. if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
  2397. pmccadapriv->mcc_tx_bytes_from_kernel += len;
  2398. if (0)
  2399. RTW_INFO("%s(order:%d): mcc tx bytes from kernel:%lld\n"
  2400. , __func__, pmccadapriv->order, pmccadapriv->mcc_tx_bytes_from_kernel);
  2401. }
  2402. }
  2403. }
  2404. /**
  2405. * rtw_hal_mcc_calc_tx_bytes_to_port - calculte tx bytes to write port in order to flow crtl
  2406. * @padapter: the adapter to be record tx bytes
  2407. * @len: data len
  2408. */
  2409. inline void rtw_hal_mcc_calc_tx_bytes_to_port(PADAPTER padapter, u32 len)
  2410. {
  2411. if (MCC_EN(padapter)) {
  2412. struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
  2413. struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
  2414. if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
  2415. pmccadapriv->mcc_tx_bytes_to_port += len;
  2416. if (0)
  2417. RTW_INFO("%s(order:%d): mcc tx bytes to port:%d, mcc target tx bytes to port:%d\n"
  2418. , __func__, pmccadapriv->order, pmccadapriv->mcc_tx_bytes_to_port
  2419. , pmccadapriv->mcc_target_tx_bytes_to_port);
  2420. }
  2421. }
  2422. }
  2423. /**
  2424. * rtw_hal_mcc_stop_tx_bytes_to_port - stop write port to hw or not
  2425. * @padapter: the adapter to be stopped
  2426. */
  2427. inline u8 rtw_hal_mcc_stop_tx_bytes_to_port(PADAPTER padapter)
  2428. {
  2429. if (MCC_EN(padapter)) {
  2430. struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
  2431. struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
  2432. if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
  2433. if (pmccadapriv->mcc_tp_limit) {
  2434. if (pmccadapriv->mcc_tx_bytes_to_port >= pmccadapriv->mcc_target_tx_bytes_to_port) {
  2435. pmccadapriv->mcc_tx_stop = _TRUE;
  2436. rtw_netif_stop_queue(padapter->pnetdev);
  2437. return _TRUE;
  2438. }
  2439. }
  2440. }
  2441. }
  2442. return _FALSE;
  2443. }
  2444. static void rtw_hal_mcc_assign_scan_flag(PADAPTER padapter, u8 scan_done)
  2445. {
  2446. struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
  2447. struct mcc_adapter_priv *mccadapriv = NULL;
  2448. _adapter *iface = NULL;
  2449. struct mlme_ext_priv *pmlmeext = NULL;
  2450. u8 i = 0, flags;
  2451. if (!MCC_EN(padapter))
  2452. return;
  2453. for (i = 0; i < dvobj->iface_nums; i++) {
  2454. iface = dvobj->padapters[i];
  2455. if (iface == NULL)
  2456. continue;
  2457. mccadapriv = &iface->mcc_adapterpriv;
  2458. if (mccadapriv->role == MCC_ROLE_MAX)
  2459. continue;
  2460. pmlmeext = &iface->mlmeextpriv;
  2461. if (is_client_associated_to_ap(iface)) {
  2462. flags = mlmeext_scan_backop_flags_sta(pmlmeext);
  2463. if (scan_done) {
  2464. if (mlmeext_chk_scan_backop_flags_sta(pmlmeext, SS_BACKOP_EN)) {
  2465. flags &= ~SS_BACKOP_EN;
  2466. mlmeext_assign_scan_backop_flags_sta(pmlmeext, flags);
  2467. }
  2468. } else {
  2469. if (!mlmeext_chk_scan_backop_flags_sta(pmlmeext, SS_BACKOP_EN)) {
  2470. flags |= SS_BACKOP_EN;
  2471. mlmeext_assign_scan_backop_flags_sta(pmlmeext, flags);
  2472. }
  2473. }
  2474. }
  2475. }
  2476. }
  2477. /**
  2478. * rtw_hal_set_mcc_setting_scan_start - setting mcc under scan start
  2479. * @padapter: the adapter to be setted
  2480. * @ch_setting_changed: softap channel setting to be changed or not
  2481. */
  2482. u8 rtw_hal_set_mcc_setting_scan_start(PADAPTER padapter)
  2483. {
  2484. u8 ret = _FAIL;
  2485. if (MCC_EN(padapter)) {
  2486. struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
  2487. _enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
  2488. if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) {
  2489. if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
  2490. ret = rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_STOP_SCAN_START);
  2491. rtw_hal_mcc_assign_scan_flag(padapter, 0);
  2492. }
  2493. }
  2494. _exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
  2495. }
  2496. return ret;
  2497. }
  2498. /**
  2499. * rtw_hal_set_mcc_setting_scan_complete - setting mcc after scan commplete
  2500. * @padapter: the adapter to be setted
  2501. * @ch_setting_changed: softap channel setting to be changed or not
  2502. */
  2503. u8 rtw_hal_set_mcc_setting_scan_complete(PADAPTER padapter)
  2504. {
  2505. u8 ret = _FAIL;
  2506. if (MCC_EN(padapter)) {
  2507. struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
  2508. _enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
  2509. if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) {
  2510. rtw_hal_mcc_assign_scan_flag(padapter, 1);
  2511. ret = rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_SCAN_DONE);
  2512. }
  2513. _exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
  2514. }
  2515. return ret;
  2516. }
  2517. /**
  2518. * rtw_hal_set_mcc_setting_start_bss_network - setting mcc under softap start
  2519. * @padapter: the adapter to be setted
  2520. * @chbw_grouped: channel bw offset can not be allowed or not
  2521. */
  2522. u8 rtw_hal_set_mcc_setting_start_bss_network(PADAPTER padapter, u8 chbw_allow)
  2523. {
  2524. u8 ret = _FAIL;
  2525. if (MCC_EN(padapter)) {
  2526. /* channel bw offset can not be allowed, start MCC */
  2527. if (chbw_allow == _FALSE) {
  2528. struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
  2529. rtw_hal_mcc_restore_iqk_val(padapter);
  2530. _enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
  2531. ret = rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_CONNECT);
  2532. _exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
  2533. }
  2534. }
  2535. return ret;
  2536. }
  2537. /**
  2538. * rtw_hal_set_mcc_setting_disconnect - setting mcc under mlme disconnect(stop softap/disconnect from AP)
  2539. * @padapter: the adapter to be setted
  2540. */
  2541. u8 rtw_hal_set_mcc_setting_disconnect(PADAPTER padapter)
  2542. {
  2543. u8 ret = _FAIL;
  2544. if (MCC_EN(padapter)) {
  2545. struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
  2546. _enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
  2547. if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) {
  2548. if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
  2549. ret = rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_STOP_DISCONNECT);
  2550. }
  2551. _exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
  2552. }
  2553. return ret;
  2554. }
  2555. /**
  2556. * rtw_hal_set_mcc_setting_join_done_chk_ch - setting mcc under join done
  2557. * @padapter: the adapter to be checked
  2558. */
  2559. u8 rtw_hal_set_mcc_setting_join_done_chk_ch(PADAPTER padapter)
  2560. {
  2561. u8 ret = _FAIL;
  2562. if (MCC_EN(padapter)) {
  2563. struct mi_state mstate;
  2564. rtw_mi_status_no_self(padapter, &mstate);
  2565. if (MSTATE_STA_LD_NUM(&mstate) || MSTATE_STA_LG_NUM(&mstate) || MSTATE_AP_NUM(&mstate)) {
  2566. bool chbw_allow = _TRUE;
  2567. u8 u_ch, u_offset, u_bw;
  2568. struct mlme_ext_priv *cur_mlmeext = &padapter->mlmeextpriv;
  2569. struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
  2570. if (rtw_mi_get_ch_setting_union_no_self(padapter, &u_ch, &u_bw, &u_offset) <= 0) {
  2571. dump_adapters_status(RTW_DBGDUMP , dvobj);
  2572. rtw_warn_on(1);
  2573. }
  2574. RTW_INFO(FUNC_ADPT_FMT" union no self: %u,%u,%u\n"
  2575. , FUNC_ADPT_ARG(padapter), u_ch, u_bw, u_offset);
  2576. /* chbw_allow? */
  2577. chbw_allow = rtw_is_chbw_grouped(cur_mlmeext->cur_channel
  2578. , cur_mlmeext->cur_bwmode, cur_mlmeext->cur_ch_offset
  2579. , u_ch, u_bw, u_offset);
  2580. RTW_INFO(FUNC_ADPT_FMT" chbw_allow:%d\n"
  2581. , FUNC_ADPT_ARG(padapter), chbw_allow);
  2582. /* if chbw_allow = false, start MCC setting */
  2583. if (chbw_allow == _FALSE) {
  2584. struct mcc_obj_priv *pmccobjpriv = &dvobj->mcc_objpriv;
  2585. rtw_hal_mcc_restore_iqk_val(padapter);
  2586. _enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
  2587. ret = rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_CONNECT);
  2588. _exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
  2589. }
  2590. }
  2591. }
  2592. return ret;
  2593. }
  2594. /**
  2595. * rtw_hal_set_mcc_setting_chk_start_clnt_join - check change channel under start clnt join
  2596. * @padapter: the adapter to be checked
  2597. * @ch: pointer to rerurn ch
  2598. * @bw: pointer to rerurn bw
  2599. * @offset: pointer to rerurn offset
  2600. * @chbw_allow: allow to use adapter's channel setting
  2601. */
  2602. u8 rtw_hal_set_mcc_setting_chk_start_clnt_join(PADAPTER padapter, u8 *ch, u8 *bw, u8 *offset, u8 chbw_allow)
  2603. {
  2604. u8 ret = _FAIL;
  2605. /* if chbw_allow = false under en_mcc = TRUE, we do not change channel related setting */
  2606. if (MCC_EN(padapter)) {
  2607. /* restore union channel related setting to current channel related setting */
  2608. if (chbw_allow == _FALSE) {
  2609. struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
  2610. /* issue null data to other interface connected to AP */
  2611. rtw_hal_mcc_issue_null_data(padapter, chbw_allow, _TRUE);
  2612. *ch = pmlmeext->cur_channel;
  2613. *bw = pmlmeext->cur_bwmode;
  2614. *offset = pmlmeext->cur_ch_offset;
  2615. RTW_INFO(FUNC_ADPT_FMT" en_mcc:%d(%d,%d,%d,)\n"
  2616. , FUNC_ADPT_ARG(padapter), MCC_EN(padapter)
  2617. , *ch, *bw, *offset);
  2618. ret = _SUCCESS;
  2619. }
  2620. }
  2621. return ret;
  2622. }
  2623. static void rtw_hal_mcc_dump_noa_content(void *sel, PADAPTER padapter)
  2624. {
  2625. struct mcc_adapter_priv *pmccadapriv = NULL;
  2626. u8 *pos = NULL;
  2627. pmccadapriv = &padapter->mcc_adapterpriv;
  2628. /* last position for NoA attribute */
  2629. pos = pmccadapriv->p2p_go_noa_ie + pmccadapriv->p2p_go_noa_ie_len;
  2630. RTW_PRINT_SEL(sel, "\nStart to dump NoA Content\n");
  2631. RTW_PRINT_SEL(sel, "NoA Counts:%d\n", *(pos - 13));
  2632. RTW_PRINT_SEL(sel, "NoA Duration(TU):%d\n", (RTW_GET_LE32(pos - 12))/TU);
  2633. RTW_PRINT_SEL(sel, "NoA Interval(TU):%d\n", (RTW_GET_LE32(pos - 8))/TU);
  2634. RTW_PRINT_SEL(sel, "NoA Start time(microseconds):0x%02x\n", RTW_GET_LE32(pos - 4));
  2635. RTW_PRINT_SEL(sel, "End to dump NoA Content\n");
  2636. }
  2637. void rtw_hal_dump_mcc_info(void *sel, struct dvobj_priv *dvobj)
  2638. {
  2639. struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
  2640. struct mcc_adapter_priv *mccadapriv = NULL;
  2641. _adapter *iface = NULL, *adapter = NULL;
  2642. struct registry_priv *regpriv = NULL;
  2643. u64 tsf[MAX_MCC_NUM] = {0};
  2644. u8 i = 0;
  2645. /* regpriv is common for all adapter */
  2646. adapter = dvobj_get_primary_adapter(dvobj);
  2647. RTW_PRINT_SEL(sel, "**********************************************\n");
  2648. RTW_PRINT_SEL(sel, "en_mcc:%d\n", MCC_EN(adapter));
  2649. RTW_PRINT_SEL(sel, "primary adapter("ADPT_FMT") duration:%d%c\n",
  2650. ADPT_ARG(dvobj_get_primary_adapter(dvobj)), mccobjpriv->duration, 37);
  2651. RTW_PRINT_SEL(sel, "runtime duration:%s\n", mccobjpriv->enable_runtime_duration ? "enable":"disable");
  2652. rtw_hal_mcc_rqt_tsf(dvobj_get_primary_adapter(dvobj), tsf);
  2653. for (i = 0; i < dvobj->iface_nums; i++) {
  2654. iface = dvobj->padapters[i];
  2655. if (!iface)
  2656. continue;
  2657. regpriv = &iface->registrypriv;
  2658. mccadapriv = &iface->mcc_adapterpriv;
  2659. if (mccadapriv->role == MCC_ROLE_MAX)
  2660. continue;
  2661. if (mccadapriv) {
  2662. u8 p2p_ps_mode = iface->wdinfo.p2p_ps_mode;
  2663. RTW_PRINT_SEL(sel, "adapter mcc info:\n");
  2664. RTW_PRINT_SEL(sel, "ifname:%s\n", ADPT_ARG(iface));
  2665. RTW_PRINT_SEL(sel, "order:%d\n", mccadapriv->order);
  2666. RTW_PRINT_SEL(sel, "duration:%d\n", mccadapriv->mcc_duration);
  2667. RTW_PRINT_SEL(sel, "target tx bytes:%d\n", mccadapriv->mcc_target_tx_bytes_to_port);
  2668. RTW_PRINT_SEL(sel, "current TP:%d\n", mccadapriv->mcc_tp);
  2669. RTW_PRINT_SEL(sel, "mgmt queue macid:%d\n", mccadapriv->mgmt_queue_macid);
  2670. RTW_PRINT_SEL(sel, "macid bitmap:0x%02x\n", mccadapriv->mcc_macid_bitmap);
  2671. RTW_PRINT_SEL(sel, "P2P NoA:%s\n\n", p2p_ps_mode == P2P_PS_NOA ? "enable":"disable");
  2672. RTW_PRINT_SEL(sel, "registry data:\n");
  2673. RTW_PRINT_SEL(sel, "ap target tx TP(BW:20M):%d Mbps\n", regpriv->rtw_mcc_ap_bw20_target_tx_tp);
  2674. RTW_PRINT_SEL(sel, "ap target tx TP(BW:40M):%d Mbps\n", regpriv->rtw_mcc_ap_bw40_target_tx_tp);
  2675. RTW_PRINT_SEL(sel, "ap target tx TP(BW:80M):%d Mbps\n", regpriv->rtw_mcc_ap_bw80_target_tx_tp);
  2676. RTW_PRINT_SEL(sel, "sta target tx TP(BW:20M):%d Mbps\n", regpriv->rtw_mcc_sta_bw20_target_tx_tp);
  2677. RTW_PRINT_SEL(sel, "sta target tx TP(BW:40M ):%d Mbps\n", regpriv->rtw_mcc_sta_bw40_target_tx_tp);
  2678. RTW_PRINT_SEL(sel, "sta target tx TP(BW:80M):%d Mbps\n", regpriv->rtw_mcc_sta_bw80_target_tx_tp);
  2679. RTW_PRINT_SEL(sel, "single tx criteria:%d Mbps\n", regpriv->rtw_mcc_single_tx_cri);
  2680. RTW_PRINT_SEL(sel, "HW TSF=0x%llx\n", tsf[mccadapriv->order]);
  2681. if (MLME_IS_GO(iface))
  2682. rtw_hal_mcc_dump_noa_content(sel, iface);
  2683. RTW_PRINT_SEL(sel, "**********************************************\n");
  2684. }
  2685. }
  2686. RTW_PRINT_SEL(sel, "------------------------------------------\n");
  2687. RTW_PRINT_SEL(sel, "policy index:%d\n", mccobjpriv->policy_index);
  2688. RTW_PRINT_SEL(sel, "------------------------------------------\n");
  2689. RTW_PRINT_SEL(sel, "define data:\n");
  2690. RTW_PRINT_SEL(sel, "ap target tx TP(BW:20M):%d Mbps\n", MCC_AP_BW20_TARGET_TX_TP);
  2691. RTW_PRINT_SEL(sel, "ap target tx TP(BW:40M):%d Mbps\n", MCC_AP_BW40_TARGET_TX_TP);
  2692. RTW_PRINT_SEL(sel, "ap target tx TP(BW:80M):%d Mbps\n", MCC_AP_BW80_TARGET_TX_TP);
  2693. RTW_PRINT_SEL(sel, "sta target tx TP(BW:20M):%d Mbps\n", MCC_STA_BW20_TARGET_TX_TP);
  2694. RTW_PRINT_SEL(sel, "sta target tx TP(BW:40M):%d Mbps\n", MCC_STA_BW40_TARGET_TX_TP);
  2695. RTW_PRINT_SEL(sel, "sta target tx TP(BW:80M):%d Mbps\n", MCC_STA_BW80_TARGET_TX_TP);
  2696. RTW_PRINT_SEL(sel, "single tx criteria:%d Mbps\n", MCC_SINGLE_TX_CRITERIA);
  2697. RTW_PRINT_SEL(sel, "------------------------------------------\n");
  2698. }
  2699. inline void update_mcc_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib)
  2700. {
  2701. if (MCC_EN(padapter)) {
  2702. if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
  2703. /* use QSLT_MGNT to check mgnt queue or bcn queue */
  2704. if (pattrib->qsel == QSLT_MGNT) {
  2705. pattrib->mac_id = padapter->mcc_adapterpriv.mgmt_queue_macid;
  2706. pattrib->qsel = QSLT_VO;
  2707. }
  2708. }
  2709. }
  2710. }
  2711. inline u8 rtw_hal_mcc_link_status_chk(_adapter *padapter, const char *msg)
  2712. {
  2713. u8 ret = _TRUE, i = 0;
  2714. struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
  2715. _adapter *iface;
  2716. struct mlme_ext_priv *mlmeext;
  2717. if (MCC_EN(padapter)) {
  2718. if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) {
  2719. for (i = 0; i < dvobj->iface_nums; i++) {
  2720. iface = dvobj->padapters[i];
  2721. mlmeext = &iface->mlmeextpriv;
  2722. if (mlmeext_scan_state(mlmeext) != SCAN_DISABLE) {
  2723. #ifdef DBG_EXPIRATION_CHK
  2724. RTW_INFO(FUNC_ADPT_FMT" don't enter %s under scan for MCC mode\n", FUNC_ADPT_ARG(padapter), msg);
  2725. #endif
  2726. ret = _FALSE;
  2727. goto exit;
  2728. }
  2729. }
  2730. }
  2731. }
  2732. exit:
  2733. return ret;
  2734. }
  2735. void rtw_hal_mcc_issue_null_data(_adapter *padapter, u8 chbw_allow, u8 ps_mode)
  2736. {
  2737. struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
  2738. _adapter *iface = NULL;
  2739. systime start = rtw_get_current_time();
  2740. u8 i = 0;
  2741. if (!MCC_EN(padapter))
  2742. return;
  2743. if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
  2744. return;
  2745. if (chbw_allow == _TRUE)
  2746. return;
  2747. for (i = 0; i < dvobj->iface_nums; i++) {
  2748. iface = dvobj->padapters[i];
  2749. /* issue null data to inform ap station will leave */
  2750. if (is_client_associated_to_ap(iface)) {
  2751. struct mlme_ext_priv *mlmeext = &iface->mlmeextpriv;
  2752. struct mlme_ext_info *mlmeextinfo = &mlmeext->mlmext_info;
  2753. u8 ch = mlmeext->cur_channel;
  2754. u8 bw = mlmeext->cur_bwmode;
  2755. u8 offset = mlmeext->cur_ch_offset;
  2756. struct sta_info *sta = rtw_get_stainfo(&iface->stapriv, get_my_bssid(&(mlmeextinfo->network)));
  2757. if (!sta)
  2758. continue;
  2759. set_channel_bwmode(iface, ch, offset, bw);
  2760. if (ps_mode)
  2761. rtw_hal_macid_sleep(iface, sta->cmn.mac_id);
  2762. else
  2763. rtw_hal_macid_wakeup(iface, sta->cmn.mac_id);
  2764. issue_nulldata(iface, NULL, ps_mode, 3, 50);
  2765. }
  2766. }
  2767. RTW_INFO("%s(%d ms)\n", __func__, rtw_get_passing_time_ms(start));
  2768. }
  2769. u8 *rtw_hal_mcc_append_go_p2p_ie(PADAPTER padapter, u8 *pframe, u32 *len)
  2770. {
  2771. struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
  2772. if (!MCC_EN(padapter))
  2773. return pframe;
  2774. if (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
  2775. return pframe;
  2776. if (pmccadapriv->p2p_go_noa_ie_len == 0)
  2777. return pframe;
  2778. _rtw_memcpy(pframe, pmccadapriv->p2p_go_noa_ie, pmccadapriv->p2p_go_noa_ie_len);
  2779. *len = *len + pmccadapriv->p2p_go_noa_ie_len;
  2780. return pframe + pmccadapriv->p2p_go_noa_ie_len;
  2781. }
  2782. void rtw_hal_dump_mcc_policy_table(void *sel)
  2783. {
  2784. u8 idx = 0;
  2785. RTW_PRINT_SEL(sel, "duration\t,tsf sync offset\t,start time offset\t,interval\t,guard offset0\t,guard offset1\n");
  2786. for (idx = 0; idx < mcc_max_policy_num; idx ++) {
  2787. RTW_PRINT_SEL(sel, "%d\t\t,%d\t\t\t,%d\t\t\t,%d\t\t,%d\t\t,%d\n"
  2788. , mcc_switch_channel_policy_table[idx][MCC_DURATION_IDX]
  2789. , mcc_switch_channel_policy_table[idx][MCC_TSF_SYNC_OFFSET_IDX]
  2790. , mcc_switch_channel_policy_table[idx][MCC_START_TIME_OFFSET_IDX]
  2791. , mcc_switch_channel_policy_table[idx][MCC_INTERVAL_IDX]
  2792. , mcc_switch_channel_policy_table[idx][MCC_GUARD_OFFSET0_IDX]
  2793. , mcc_switch_channel_policy_table[idx][MCC_GUARD_OFFSET1_IDX]);
  2794. }
  2795. }
  2796. void rtw_hal_mcc_update_macid_bitmap(PADAPTER padapter, int mac_id, u8 add)
  2797. {
  2798. struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
  2799. if (!MCC_EN(padapter))
  2800. return;
  2801. if (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
  2802. return;
  2803. if (pmccadapriv->role == MCC_ROLE_GC || pmccadapriv->role == MCC_ROLE_STA)
  2804. return;
  2805. if (mac_id < 0) {
  2806. RTW_WARN("%s: mac_id < 0(%d)\n", __func__, mac_id);
  2807. return;
  2808. }
  2809. RTW_INFO(ADPT_FMT" %s macid=%d, ori mcc_macid_bitmap=0x%08x\n"
  2810. , ADPT_ARG(padapter), add ? "add" : "clear"
  2811. , mac_id, pmccadapriv->mcc_macid_bitmap);
  2812. if (add)
  2813. pmccadapriv->mcc_macid_bitmap |= BIT(mac_id);
  2814. else
  2815. pmccadapriv->mcc_macid_bitmap &= ~(BIT(mac_id));
  2816. rtw_hal_set_mcc_macid_cmd(padapter);
  2817. }
  2818. void rtw_hal_mcc_process_noa(PADAPTER padapter)
  2819. {
  2820. struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
  2821. struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
  2822. struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
  2823. if (!MCC_EN(padapter))
  2824. return;
  2825. if (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
  2826. return;
  2827. if (!MLME_IS_GC(padapter))
  2828. return;
  2829. switch(pwdinfo->p2p_ps_mode) {
  2830. case P2P_PS_NONE:
  2831. RTW_INFO("[MCC] Disable NoA under MCC\n");
  2832. rtw_hal_mcc_update_parameter(padapter, _TRUE);
  2833. break;
  2834. case P2P_PS_NOA:
  2835. RTW_INFO("[MCC] Enable NoA under MCC\n");
  2836. break;
  2837. default:
  2838. break;
  2839. }
  2840. }
  2841. void rtw_hal_mcc_parameter_init(PADAPTER padapter)
  2842. {
  2843. if (!padapter->registrypriv.en_mcc)
  2844. return;
  2845. if (is_primary_adapter(padapter)) {
  2846. SET_MCC_EN_FLAG(padapter, padapter->registrypriv.en_mcc);
  2847. SET_MCC_DURATION(padapter, padapter->registrypriv.rtw_mcc_duration);
  2848. SET_MCC_RUNTIME_DURATION(padapter, padapter->registrypriv.rtw_mcc_enable_runtime_duration);
  2849. }
  2850. }
  2851. u8 rtw_set_mcc_duration_hdl(PADAPTER adapter, u8 type, const u8 *val)
  2852. {
  2853. struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
  2854. struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
  2855. _adapter *iface = NULL;
  2856. u8 duration = 50;
  2857. u8 ret = _SUCCESS, noa_enable = _FALSE, i = 0;
  2858. if (!mccobjpriv->enable_runtime_duration)
  2859. goto exit;
  2860. #ifdef CONFIG_P2P_PS
  2861. /* check noa enable or not */
  2862. for (i = 0; i < dvobj->iface_nums; i++) {
  2863. iface = dvobj->padapters[i];
  2864. if (iface->wdinfo.p2p_ps_mode == P2P_PS_NOA) {
  2865. noa_enable = _TRUE;
  2866. break;
  2867. }
  2868. }
  2869. #endif /* CONFIG_P2P_PS */
  2870. if (type == MCC_DURATION_MAPPING) {
  2871. switch (*val) {
  2872. /* 0 = fair scheduling */
  2873. case 0:
  2874. mccobjpriv->duration= 40;
  2875. mccobjpriv->policy_index = 2;
  2876. mccobjpriv->mchan_sched_mode = MCC_FAIR_SCHEDULE;
  2877. break;
  2878. /* 1 = favor STA */
  2879. case 1:
  2880. mccobjpriv->duration= 70;
  2881. mccobjpriv->policy_index = 1;
  2882. mccobjpriv->mchan_sched_mode = MCC_FAVOE_STA;
  2883. break;
  2884. /* 2 = favor P2P*/
  2885. case 2:
  2886. default:
  2887. mccobjpriv->duration= 30;
  2888. mccobjpriv->policy_index = 0;
  2889. mccobjpriv->mchan_sched_mode = MCC_FAVOE_P2P;
  2890. break;
  2891. }
  2892. } else {
  2893. mccobjpriv->duration = *val;
  2894. rtw_hal_mcc_update_policy_table(adapter);
  2895. }
  2896. /* only update sw parameter under MCC
  2897. it will be force update during */
  2898. if (noa_enable)
  2899. goto exit;
  2900. if (rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC))
  2901. rtw_hal_mcc_update_parameter(adapter, _TRUE);
  2902. exit:
  2903. return ret;
  2904. }
  2905. u8 rtw_set_mcc_duration_cmd(_adapter *adapter, u8 type, u8 val)
  2906. {
  2907. struct cmd_obj *cmdobj;
  2908. struct drvextra_cmd_parm *pdrvextra_cmd_parm;
  2909. struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
  2910. u8 *mcc_duration = NULL;
  2911. u8 res = _FAIL;
  2912. cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
  2913. if (cmdobj == NULL)
  2914. goto exit;
  2915. pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
  2916. if (pdrvextra_cmd_parm == NULL) {
  2917. rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
  2918. goto exit;
  2919. }
  2920. mcc_duration = rtw_zmalloc(sizeof(u8));
  2921. if (mcc_duration == NULL) {
  2922. rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
  2923. rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));
  2924. res = _FAIL;
  2925. goto exit;
  2926. }
  2927. pdrvextra_cmd_parm->ec_id = MCC_SET_DURATION_WK_CID;
  2928. pdrvextra_cmd_parm->type = type;
  2929. pdrvextra_cmd_parm->size = 1;
  2930. pdrvextra_cmd_parm->pbuf = mcc_duration;
  2931. _rtw_memcpy(mcc_duration, &val, 1);
  2932. init_h2fwcmd_w_parm_no_rsp(cmdobj, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
  2933. res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
  2934. exit:
  2935. return res;
  2936. }
  2937. #endif /* CONFIG_MCC_MODE */