hal_com_phycfg.c 158 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2007 - 2017 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. *****************************************************************************/
  15. #define _HAL_COM_PHYCFG_C_
  16. #include <drv_types.h>
  17. #include <hal_data.h>
  18. #define PG_TXPWR_1PATH_BYTE_NUM_2G 18
  19. #define PG_TXPWR_BASE_BYTE_NUM_2G 11
  20. #define PG_TXPWR_1PATH_BYTE_NUM_5G 24
  21. #define PG_TXPWR_BASE_BYTE_NUM_5G 14
  22. #define PG_TXPWR_MSB_DIFF_S4BIT(_pg_v) (((_pg_v) & 0xf0) >> 4)
  23. #define PG_TXPWR_LSB_DIFF_S4BIT(_pg_v) ((_pg_v) & 0x0f)
  24. #define PG_TXPWR_MSB_DIFF_TO_S8BIT(_pg_v) ((PG_TXPWR_MSB_DIFF_S4BIT(_pg_v) & BIT3) ? (PG_TXPWR_MSB_DIFF_S4BIT(_pg_v) | 0xF0) : PG_TXPWR_MSB_DIFF_S4BIT(_pg_v))
  25. #define PG_TXPWR_LSB_DIFF_TO_S8BIT(_pg_v) ((PG_TXPWR_LSB_DIFF_S4BIT(_pg_v) & BIT3) ? (PG_TXPWR_LSB_DIFF_S4BIT(_pg_v) | 0xF0) : PG_TXPWR_LSB_DIFF_S4BIT(_pg_v))
  26. #define IS_PG_TXPWR_BASE_INVALID(hal_spec, _base) ((_base) > hal_spec->txgi_max)
  27. #define IS_PG_TXPWR_DIFF_INVALID(_diff) ((_diff) > 7 || (_diff) < -8)
  28. #define PG_TXPWR_INVALID_BASE 255
  29. #define PG_TXPWR_INVALID_DIFF 8
  30. #if !IS_PG_TXPWR_DIFF_INVALID(PG_TXPWR_INVALID_DIFF)
  31. #error "PG_TXPWR_DIFF definition has problem"
  32. #endif
  33. #define PG_TXPWR_SRC_PG_DATA 0
  34. #define PG_TXPWR_SRC_IC_DEF 1
  35. #define PG_TXPWR_SRC_DEF 2
  36. #define PG_TXPWR_SRC_NUM 3
  37. const char *const _pg_txpwr_src_str[] = {
  38. "PG_DATA",
  39. "IC_DEF",
  40. "DEF",
  41. "UNKNOWN"
  42. };
  43. #define pg_txpwr_src_str(src) (((src) >= PG_TXPWR_SRC_NUM) ? _pg_txpwr_src_str[PG_TXPWR_SRC_NUM] : _pg_txpwr_src_str[(src)])
  44. #ifndef DBG_PG_TXPWR_READ
  45. #define DBG_PG_TXPWR_READ 0
  46. #endif
  47. #if DBG_PG_TXPWR_READ
  48. static void dump_pg_txpwr_info_2g(void *sel, TxPowerInfo24G *txpwr_info, u8 rfpath_num, u8 max_tx_cnt)
  49. {
  50. int path, group, tx_idx;
  51. RTW_PRINT_SEL(sel, "2.4G\n");
  52. RTW_PRINT_SEL(sel, "CCK-1T base:\n");
  53. RTW_PRINT_SEL(sel, "%4s ", "");
  54. for (group = 0; group < MAX_CHNL_GROUP_24G; group++)
  55. _RTW_PRINT_SEL(sel, "G%02d ", group);
  56. _RTW_PRINT_SEL(sel, "\n");
  57. for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
  58. RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
  59. for (group = 0; group < MAX_CHNL_GROUP_24G; group++)
  60. _RTW_PRINT_SEL(sel, "%3u ", txpwr_info->IndexCCK_Base[path][group]);
  61. _RTW_PRINT_SEL(sel, "\n");
  62. }
  63. RTW_PRINT_SEL(sel, "\n");
  64. RTW_PRINT_SEL(sel, "CCK diff:\n");
  65. RTW_PRINT_SEL(sel, "%4s ", "");
  66. for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
  67. _RTW_PRINT_SEL(sel, "%dT ", path + 1);
  68. _RTW_PRINT_SEL(sel, "\n");
  69. for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
  70. RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
  71. for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
  72. _RTW_PRINT_SEL(sel, "%2d ", txpwr_info->CCK_Diff[path][tx_idx]);
  73. _RTW_PRINT_SEL(sel, "\n");
  74. }
  75. RTW_PRINT_SEL(sel, "\n");
  76. RTW_PRINT_SEL(sel, "BW40-1S base:\n");
  77. RTW_PRINT_SEL(sel, "%4s ", "");
  78. for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++)
  79. _RTW_PRINT_SEL(sel, "G%02d ", group);
  80. _RTW_PRINT_SEL(sel, "\n");
  81. for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
  82. RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
  83. for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++)
  84. _RTW_PRINT_SEL(sel, "%3u ", txpwr_info->IndexBW40_Base[path][group]);
  85. _RTW_PRINT_SEL(sel, "\n");
  86. }
  87. RTW_PRINT_SEL(sel, "\n");
  88. RTW_PRINT_SEL(sel, "OFDM diff:\n");
  89. RTW_PRINT_SEL(sel, "%4s ", "");
  90. for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
  91. _RTW_PRINT_SEL(sel, "%dT ", path + 1);
  92. _RTW_PRINT_SEL(sel, "\n");
  93. for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
  94. RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
  95. for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
  96. _RTW_PRINT_SEL(sel, "%2d ", txpwr_info->OFDM_Diff[path][tx_idx]);
  97. _RTW_PRINT_SEL(sel, "\n");
  98. }
  99. RTW_PRINT_SEL(sel, "\n");
  100. RTW_PRINT_SEL(sel, "BW20 diff:\n");
  101. RTW_PRINT_SEL(sel, "%4s ", "");
  102. for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
  103. _RTW_PRINT_SEL(sel, "%dS ", path + 1);
  104. _RTW_PRINT_SEL(sel, "\n");
  105. for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
  106. RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
  107. for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
  108. _RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW20_Diff[path][tx_idx]);
  109. _RTW_PRINT_SEL(sel, "\n");
  110. }
  111. RTW_PRINT_SEL(sel, "\n");
  112. RTW_PRINT_SEL(sel, "BW40 diff:\n");
  113. RTW_PRINT_SEL(sel, "%4s ", "");
  114. for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
  115. _RTW_PRINT_SEL(sel, "%dS ", path + 1);
  116. _RTW_PRINT_SEL(sel, "\n");
  117. for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
  118. RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
  119. for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
  120. _RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW40_Diff[path][tx_idx]);
  121. _RTW_PRINT_SEL(sel, "\n");
  122. }
  123. RTW_PRINT_SEL(sel, "\n");
  124. }
  125. static void dump_pg_txpwr_info_5g(void *sel, TxPowerInfo5G *txpwr_info, u8 rfpath_num, u8 max_tx_cnt)
  126. {
  127. int path, group, tx_idx;
  128. RTW_PRINT_SEL(sel, "5G\n");
  129. RTW_PRINT_SEL(sel, "BW40-1S base:\n");
  130. RTW_PRINT_SEL(sel, "%4s ", "");
  131. for (group = 0; group < MAX_CHNL_GROUP_5G; group++)
  132. _RTW_PRINT_SEL(sel, "G%02d ", group);
  133. _RTW_PRINT_SEL(sel, "\n");
  134. for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
  135. RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
  136. for (group = 0; group < MAX_CHNL_GROUP_5G; group++)
  137. _RTW_PRINT_SEL(sel, "%3u ", txpwr_info->IndexBW40_Base[path][group]);
  138. _RTW_PRINT_SEL(sel, "\n");
  139. }
  140. RTW_PRINT_SEL(sel, "\n");
  141. RTW_PRINT_SEL(sel, "OFDM diff:\n");
  142. RTW_PRINT_SEL(sel, "%4s ", "");
  143. for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
  144. _RTW_PRINT_SEL(sel, "%dT ", path + 1);
  145. _RTW_PRINT_SEL(sel, "\n");
  146. for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
  147. RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
  148. for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
  149. _RTW_PRINT_SEL(sel, "%2d ", txpwr_info->OFDM_Diff[path][tx_idx]);
  150. _RTW_PRINT_SEL(sel, "\n");
  151. }
  152. RTW_PRINT_SEL(sel, "\n");
  153. RTW_PRINT_SEL(sel, "BW20 diff:\n");
  154. RTW_PRINT_SEL(sel, "%4s ", "");
  155. for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
  156. _RTW_PRINT_SEL(sel, "%dS ", path + 1);
  157. _RTW_PRINT_SEL(sel, "\n");
  158. for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
  159. RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
  160. for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
  161. _RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW20_Diff[path][tx_idx]);
  162. _RTW_PRINT_SEL(sel, "\n");
  163. }
  164. RTW_PRINT_SEL(sel, "\n");
  165. RTW_PRINT_SEL(sel, "BW40 diff:\n");
  166. RTW_PRINT_SEL(sel, "%4s ", "");
  167. for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
  168. _RTW_PRINT_SEL(sel, "%dS ", path + 1);
  169. _RTW_PRINT_SEL(sel, "\n");
  170. for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
  171. RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
  172. for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
  173. _RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW40_Diff[path][tx_idx]);
  174. _RTW_PRINT_SEL(sel, "\n");
  175. }
  176. RTW_PRINT_SEL(sel, "\n");
  177. RTW_PRINT_SEL(sel, "BW80 diff:\n");
  178. RTW_PRINT_SEL(sel, "%4s ", "");
  179. for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
  180. _RTW_PRINT_SEL(sel, "%dS ", path + 1);
  181. _RTW_PRINT_SEL(sel, "\n");
  182. for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
  183. RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
  184. for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
  185. _RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW80_Diff[path][tx_idx]);
  186. _RTW_PRINT_SEL(sel, "\n");
  187. }
  188. RTW_PRINT_SEL(sel, "\n");
  189. RTW_PRINT_SEL(sel, "BW160 diff:\n");
  190. RTW_PRINT_SEL(sel, "%4s ", "");
  191. for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
  192. _RTW_PRINT_SEL(sel, "%dS ", path + 1);
  193. _RTW_PRINT_SEL(sel, "\n");
  194. for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
  195. RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
  196. for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
  197. _RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW160_Diff[path][tx_idx]);
  198. _RTW_PRINT_SEL(sel, "\n");
  199. }
  200. RTW_PRINT_SEL(sel, "\n");
  201. }
  202. #endif /* DBG_PG_TXPWR_READ */
  203. const struct map_t pg_txpwr_def_info =
  204. MAP_ENT(0xB8, 1, 0xFF
  205. , MAPSEG_ARRAY_ENT(0x10, 168,
  206. 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE, 0xEE, 0xEE,
  207. 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
  208. 0x04, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,
  209. 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A,
  210. 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x04, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
  211. 0xEE, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24,
  212. 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
  213. 0x2A, 0x2A, 0x2A, 0x2A, 0x04, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D,
  214. 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
  215. 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x04, 0xEE,
  216. 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE)
  217. );
  218. #ifdef CONFIG_RTL8188E
  219. static const struct map_t rtl8188e_pg_txpwr_def_info =
  220. MAP_ENT(0xB8, 1, 0xFF
  221. , MAPSEG_ARRAY_ENT(0x10, 12,
  222. 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24)
  223. );
  224. #endif
  225. #ifdef CONFIG_RTL8188F
  226. static const struct map_t rtl8188f_pg_txpwr_def_info =
  227. MAP_ENT(0xB8, 1, 0xFF
  228. , MAPSEG_ARRAY_ENT(0x10, 12,
  229. 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x27, 0x27, 0x27, 0x27, 0x27, 0x24)
  230. );
  231. #endif
  232. #ifdef CONFIG_RTL8188GTV
  233. static const struct map_t rtl8188gtv_pg_txpwr_def_info =
  234. MAP_ENT(0xB8, 1, 0xFF
  235. , MAPSEG_ARRAY_ENT(0x10, 12,
  236. 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x27, 0x27, 0x27, 0x27, 0x27, 0x24)
  237. );
  238. #endif
  239. #ifdef CONFIG_RTL8723B
  240. static const struct map_t rtl8723b_pg_txpwr_def_info =
  241. MAP_ENT(0xB8, 2, 0xFF
  242. , MAPSEG_ARRAY_ENT(0x10, 12,
  243. 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0xE0)
  244. , MAPSEG_ARRAY_ENT(0x3A, 12,
  245. 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0xE0)
  246. );
  247. #endif
  248. #ifdef CONFIG_RTL8703B
  249. static const struct map_t rtl8703b_pg_txpwr_def_info =
  250. MAP_ENT(0xB8, 1, 0xFF
  251. , MAPSEG_ARRAY_ENT(0x10, 12,
  252. 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02)
  253. );
  254. #endif
  255. #ifdef CONFIG_RTL8723D
  256. static const struct map_t rtl8723d_pg_txpwr_def_info =
  257. MAP_ENT(0xB8, 2, 0xFF
  258. , MAPSEG_ARRAY_ENT(0x10, 12,
  259. 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02)
  260. , MAPSEG_ARRAY_ENT(0x3A, 12,
  261. 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x21, 0x21, 0x21, 0x21, 0x21, 0x02)
  262. );
  263. #endif
  264. #ifdef CONFIG_RTL8192E
  265. static const struct map_t rtl8192e_pg_txpwr_def_info =
  266. MAP_ENT(0xB8, 2, 0xFF
  267. , MAPSEG_ARRAY_ENT(0x10, 14,
  268. 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE)
  269. , MAPSEG_ARRAY_ENT(0x3A, 14,
  270. 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE)
  271. );
  272. #endif
  273. #ifdef CONFIG_RTL8821A
  274. static const struct map_t rtl8821a_pg_txpwr_def_info =
  275. MAP_ENT(0xB8, 1, 0xFF
  276. , MAPSEG_ARRAY_ENT(0x10, 39,
  277. 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xFF, 0xFF, 0xFF, 0xFF,
  278. 0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
  279. 0x04, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00)
  280. );
  281. #endif
  282. #ifdef CONFIG_RTL8821C
  283. static const struct map_t rtl8821c_pg_txpwr_def_info =
  284. MAP_ENT(0xB8, 1, 0xFF
  285. , MAPSEG_ARRAY_ENT(0x10, 54,
  286. 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xFF, 0xFF, 0xFF, 0xFF,
  287. 0xFF, 0xFF, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28,
  288. 0x02, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xEC, 0xFF, 0xFF, 0xFF, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,
  289. 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02)
  290. );
  291. #endif
  292. #ifdef CONFIG_RTL8710B
  293. static const struct map_t rtl8710b_pg_txpwr_def_info =
  294. MAP_ENT(0xC8, 1, 0xFF
  295. , MAPSEG_ARRAY_ENT(0x20, 12,
  296. 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x20)
  297. );
  298. #endif
  299. #ifdef CONFIG_RTL8812A
  300. static const struct map_t rtl8812a_pg_txpwr_def_info =
  301. MAP_ENT(0xB8, 1, 0xFF
  302. , MAPSEG_ARRAY_ENT(0x10, 82,
  303. 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xFF, 0xFF,
  304. 0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
  305. 0x02, 0xEE, 0xFF, 0xFF, 0xEE, 0xFF, 0x00, 0xEE, 0xFF, 0xFF, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,
  306. 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xFF, 0xFF, 0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A,
  307. 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE, 0xFF, 0xFF, 0xEE, 0xFF,
  308. 0x00, 0xEE)
  309. );
  310. #endif
  311. #ifdef CONFIG_RTL8822B
  312. static const struct map_t rtl8822b_pg_txpwr_def_info =
  313. MAP_ENT(0xB8, 1, 0xFF
  314. , MAPSEG_ARRAY_ENT(0x10, 82,
  315. 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xFF, 0xFF,
  316. 0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
  317. 0x02, 0xEE, 0xFF, 0xFF, 0xEE, 0xFF, 0xEC, 0xEC, 0xFF, 0xFF, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,
  318. 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xFF, 0xFF, 0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A,
  319. 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE, 0xFF, 0xFF, 0xEE, 0xFF,
  320. 0xEC, 0xEC)
  321. );
  322. #endif
  323. #ifdef CONFIG_RTL8814A
  324. static const struct map_t rtl8814a_pg_txpwr_def_info =
  325. MAP_ENT(0xB8, 1, 0xFF
  326. , MAPSEG_ARRAY_ENT(0x10, 168,
  327. 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xEE, 0xEE,
  328. 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
  329. 0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x00, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,
  330. 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A,
  331. 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
  332. 0x00, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02,
  333. 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
  334. 0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x00, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D,
  335. 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
  336. 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE,
  337. 0xEE, 0xEE, 0xEE, 0xEE, 0x00, 0xEE, 0xEE, 0xEE)
  338. );
  339. #endif
  340. #ifdef CONFIG_RTL8192F/*use 8192F default,no document*/
  341. static const struct map_t rtl8192f_pg_txpwr_def_info =
  342. MAP_ENT(0xB8, 2, 0xFF
  343. , MAPSEG_ARRAY_ENT(0x10, 14,
  344. 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE)
  345. , MAPSEG_ARRAY_ENT(0x3A, 14,
  346. 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE)
  347. );
  348. #endif
  349. const struct map_t *hal_pg_txpwr_def_info(_adapter *adapter)
  350. {
  351. u8 interface_type = 0;
  352. const struct map_t *map = NULL;
  353. interface_type = rtw_get_intf_type(adapter);
  354. switch (rtw_get_chip_type(adapter)) {
  355. #ifdef CONFIG_RTL8723B
  356. case RTL8723B:
  357. map = &rtl8723b_pg_txpwr_def_info;
  358. break;
  359. #endif
  360. #ifdef CONFIG_RTL8703B
  361. case RTL8703B:
  362. map = &rtl8703b_pg_txpwr_def_info;
  363. break;
  364. #endif
  365. #ifdef CONFIG_RTL8723D
  366. case RTL8723D:
  367. map = &rtl8723d_pg_txpwr_def_info;
  368. break;
  369. #endif
  370. #ifdef CONFIG_RTL8188E
  371. case RTL8188E:
  372. map = &rtl8188e_pg_txpwr_def_info;
  373. break;
  374. #endif
  375. #ifdef CONFIG_RTL8188F
  376. case RTL8188F:
  377. map = &rtl8188f_pg_txpwr_def_info;
  378. break;
  379. #endif
  380. #ifdef CONFIG_RTL8188GTV
  381. case RTL8188GTV:
  382. map = &rtl8188gtv_pg_txpwr_def_info;
  383. break;
  384. #endif
  385. #ifdef CONFIG_RTL8812A
  386. case RTL8812:
  387. map = &rtl8812a_pg_txpwr_def_info;
  388. break;
  389. #endif
  390. #ifdef CONFIG_RTL8821A
  391. case RTL8821:
  392. map = &rtl8821a_pg_txpwr_def_info;
  393. break;
  394. #endif
  395. #ifdef CONFIG_RTL8192E
  396. case RTL8192E:
  397. map = &rtl8192e_pg_txpwr_def_info;
  398. break;
  399. #endif
  400. #ifdef CONFIG_RTL8814A
  401. case RTL8814A:
  402. map = &rtl8814a_pg_txpwr_def_info;
  403. break;
  404. #endif
  405. #ifdef CONFIG_RTL8822B
  406. case RTL8822B:
  407. map = &rtl8822b_pg_txpwr_def_info;
  408. break;
  409. #endif
  410. #ifdef CONFIG_RTL8821C
  411. case RTL8821C:
  412. map = &rtl8821c_pg_txpwr_def_info;
  413. break;
  414. #endif
  415. #ifdef CONFIG_RTL8710B
  416. case RTL8710B:
  417. map = &rtl8710b_pg_txpwr_def_info;
  418. break;
  419. #endif
  420. #ifdef CONFIG_RTL8192F
  421. case RTL8192F:
  422. map = &rtl8192f_pg_txpwr_def_info;
  423. break;
  424. #endif
  425. }
  426. if (map == NULL) {
  427. RTW_ERR("%s: unknown chip_type:%u\n"
  428. , __func__, rtw_get_chip_type(adapter));
  429. rtw_warn_on(1);
  430. }
  431. return map;
  432. }
  433. static u8 hal_chk_pg_txpwr_info_2g(_adapter *adapter, TxPowerInfo24G *pwr_info)
  434. {
  435. struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
  436. u8 path, group, tx_idx;
  437. if (pwr_info == NULL || !hal_chk_band_cap(adapter, BAND_CAP_2G))
  438. return _SUCCESS;
  439. for (path = 0; path < MAX_RF_PATH; path++) {
  440. if (!HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path))
  441. continue;
  442. for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
  443. if (IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexCCK_Base[path][group])
  444. || IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexBW40_Base[path][group]))
  445. return _FAIL;
  446. }
  447. for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
  448. if (!HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx))
  449. continue;
  450. if (IS_PG_TXPWR_DIFF_INVALID(pwr_info->CCK_Diff[path][tx_idx])
  451. || IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx])
  452. || IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])
  453. || IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW40_Diff[path][tx_idx]))
  454. return _FAIL;
  455. }
  456. }
  457. return _SUCCESS;
  458. }
  459. static u8 hal_chk_pg_txpwr_info_5g(_adapter *adapter, TxPowerInfo5G *pwr_info)
  460. {
  461. #ifdef CONFIG_IEEE80211_BAND_5GHZ
  462. struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
  463. u8 path, group, tx_idx;
  464. if (pwr_info == NULL || !hal_chk_band_cap(adapter, BAND_CAP_5G))
  465. return _SUCCESS;
  466. for (path = 0; path < MAX_RF_PATH; path++) {
  467. if (!HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path))
  468. continue;
  469. for (group = 0; group < MAX_CHNL_GROUP_5G; group++)
  470. if (IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexBW40_Base[path][group]))
  471. return _FAIL;
  472. for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
  473. if (!HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx))
  474. continue;
  475. if (IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx])
  476. || IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])
  477. || IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW40_Diff[path][tx_idx])
  478. || IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW80_Diff[path][tx_idx])
  479. || IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW160_Diff[path][tx_idx]))
  480. return _FAIL;
  481. }
  482. }
  483. #endif /* CONFIG_IEEE80211_BAND_5GHZ */
  484. return _SUCCESS;
  485. }
  486. static inline void hal_init_pg_txpwr_info_2g(_adapter *adapter, TxPowerInfo24G *pwr_info)
  487. {
  488. struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
  489. u8 path, group, tx_idx;
  490. if (pwr_info == NULL)
  491. return;
  492. _rtw_memset(pwr_info, 0, sizeof(TxPowerInfo24G));
  493. /* init with invalid value */
  494. for (path = 0; path < MAX_RF_PATH; path++) {
  495. for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
  496. pwr_info->IndexCCK_Base[path][group] = PG_TXPWR_INVALID_BASE;
  497. pwr_info->IndexBW40_Base[path][group] = PG_TXPWR_INVALID_BASE;
  498. }
  499. for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
  500. pwr_info->CCK_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
  501. pwr_info->OFDM_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
  502. pwr_info->BW20_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
  503. pwr_info->BW40_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
  504. }
  505. }
  506. /* init for dummy base and diff */
  507. for (path = 0; path < MAX_RF_PATH; path++) {
  508. if (!HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path))
  509. break;
  510. /* 2.4G BW40 base has 1 less group than CCK base*/
  511. pwr_info->IndexBW40_Base[path][MAX_CHNL_GROUP_24G - 1] = 0;
  512. /* dummy diff */
  513. pwr_info->CCK_Diff[path][0] = 0; /* 2.4G CCK-1TX */
  514. pwr_info->BW40_Diff[path][0] = 0; /* 2.4G BW40-1S */
  515. }
  516. }
  517. static inline void hal_init_pg_txpwr_info_5g(_adapter *adapter, TxPowerInfo5G *pwr_info)
  518. {
  519. #ifdef CONFIG_IEEE80211_BAND_5GHZ
  520. struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
  521. u8 path, group, tx_idx;
  522. if (pwr_info == NULL)
  523. return;
  524. _rtw_memset(pwr_info, 0, sizeof(TxPowerInfo5G));
  525. /* init with invalid value */
  526. for (path = 0; path < MAX_RF_PATH; path++) {
  527. for (group = 0; group < MAX_CHNL_GROUP_5G; group++)
  528. pwr_info->IndexBW40_Base[path][group] = PG_TXPWR_INVALID_BASE;
  529. for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
  530. pwr_info->OFDM_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
  531. pwr_info->BW20_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
  532. pwr_info->BW40_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
  533. pwr_info->BW80_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
  534. pwr_info->BW160_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
  535. }
  536. }
  537. for (path = 0; path < MAX_RF_PATH; path++) {
  538. if (!HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path))
  539. break;
  540. /* dummy diff */
  541. pwr_info->BW40_Diff[path][0] = 0; /* 5G BW40-1S */
  542. }
  543. #endif /* CONFIG_IEEE80211_BAND_5GHZ */
  544. }
  545. #if DBG_PG_TXPWR_READ
  546. #define LOAD_PG_TXPWR_WARN_COND(_txpwr_src) 1
  547. #else
  548. #define LOAD_PG_TXPWR_WARN_COND(_txpwr_src) (_txpwr_src > PG_TXPWR_SRC_PG_DATA)
  549. #endif
  550. u16 hal_load_pg_txpwr_info_path_2g(
  551. _adapter *adapter,
  552. TxPowerInfo24G *pwr_info,
  553. u32 path,
  554. u8 txpwr_src,
  555. const struct map_t *txpwr_map,
  556. u16 pg_offset)
  557. {
  558. struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
  559. u16 offset = pg_offset;
  560. u8 group, tx_idx;
  561. u8 val;
  562. u8 tmp_base;
  563. s8 tmp_diff;
  564. if (pwr_info == NULL || !hal_chk_band_cap(adapter, BAND_CAP_2G)) {
  565. offset += PG_TXPWR_1PATH_BYTE_NUM_2G;
  566. goto exit;
  567. }
  568. if (DBG_PG_TXPWR_READ)
  569. RTW_INFO("%s [%c] offset:0x%03x\n", __func__, rf_path_char(path), offset);
  570. for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
  571. if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path)) {
  572. tmp_base = map_read8(txpwr_map, offset);
  573. if (!IS_PG_TXPWR_BASE_INVALID(hal_spec, tmp_base)
  574. && IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexCCK_Base[path][group])
  575. ) {
  576. pwr_info->IndexCCK_Base[path][group] = tmp_base;
  577. if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
  578. RTW_INFO("[%c] 2G G%02d CCK-1T base:%u from %s\n", rf_path_char(path), group, tmp_base, pg_txpwr_src_str(txpwr_src));
  579. }
  580. }
  581. offset++;
  582. }
  583. for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++) {
  584. if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path)) {
  585. tmp_base = map_read8(txpwr_map, offset);
  586. if (!IS_PG_TXPWR_BASE_INVALID(hal_spec, tmp_base)
  587. && IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexBW40_Base[path][group])
  588. ) {
  589. pwr_info->IndexBW40_Base[path][group] = tmp_base;
  590. if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
  591. RTW_INFO("[%c] 2G G%02d BW40-1S base:%u from %s\n", rf_path_char(path), group, tmp_base, pg_txpwr_src_str(txpwr_src));
  592. }
  593. }
  594. offset++;
  595. }
  596. for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
  597. if (tx_idx == 0) {
  598. if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) {
  599. val = map_read8(txpwr_map, offset);
  600. tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
  601. if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
  602. && IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])
  603. ) {
  604. pwr_info->BW20_Diff[path][tx_idx] = tmp_diff;
  605. if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
  606. RTW_INFO("[%c] 2G BW20-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
  607. }
  608. tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
  609. if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
  610. && IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx])
  611. ) {
  612. pwr_info->OFDM_Diff[path][tx_idx] = tmp_diff;
  613. if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
  614. RTW_INFO("[%c] 2G OFDM-%dT diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
  615. }
  616. }
  617. offset++;
  618. } else {
  619. if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) {
  620. val = map_read8(txpwr_map, offset);
  621. tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
  622. if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
  623. && IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW40_Diff[path][tx_idx])
  624. ) {
  625. pwr_info->BW40_Diff[path][tx_idx] = tmp_diff;
  626. if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
  627. RTW_INFO("[%c] 2G BW40-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
  628. }
  629. tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
  630. if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
  631. && IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])
  632. ) {
  633. pwr_info->BW20_Diff[path][tx_idx] = tmp_diff;
  634. if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
  635. RTW_INFO("[%c] 2G BW20-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
  636. }
  637. }
  638. offset++;
  639. if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) {
  640. val = map_read8(txpwr_map, offset);
  641. tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
  642. if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
  643. && IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx])
  644. ) {
  645. pwr_info->OFDM_Diff[path][tx_idx] = tmp_diff;
  646. if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
  647. RTW_INFO("[%c] 2G OFDM-%dT diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
  648. }
  649. tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
  650. if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
  651. && IS_PG_TXPWR_DIFF_INVALID(pwr_info->CCK_Diff[path][tx_idx])
  652. ) {
  653. pwr_info->CCK_Diff[path][tx_idx] = tmp_diff;
  654. if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
  655. RTW_INFO("[%c] 2G CCK-%dT diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
  656. }
  657. }
  658. offset++;
  659. }
  660. }
  661. if (offset != pg_offset + PG_TXPWR_1PATH_BYTE_NUM_2G) {
  662. RTW_ERR("%s parse %d bytes != %d\n", __func__, offset - pg_offset, PG_TXPWR_1PATH_BYTE_NUM_2G);
  663. rtw_warn_on(1);
  664. }
  665. exit:
  666. return offset;
  667. }
  668. u16 hal_load_pg_txpwr_info_path_5g(
  669. _adapter *adapter,
  670. TxPowerInfo5G *pwr_info,
  671. u32 path,
  672. u8 txpwr_src,
  673. const struct map_t *txpwr_map,
  674. u16 pg_offset)
  675. {
  676. struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
  677. u16 offset = pg_offset;
  678. u8 group, tx_idx;
  679. u8 val;
  680. u8 tmp_base;
  681. s8 tmp_diff;
  682. #ifdef CONFIG_IEEE80211_BAND_5GHZ
  683. if (pwr_info == NULL || !hal_chk_band_cap(adapter, BAND_CAP_5G))
  684. #endif
  685. {
  686. offset += PG_TXPWR_1PATH_BYTE_NUM_5G;
  687. goto exit;
  688. }
  689. #ifdef CONFIG_IEEE80211_BAND_5GHZ
  690. if (DBG_PG_TXPWR_READ)
  691. RTW_INFO("%s[%c] eaddr:0x%03x\n", __func__, rf_path_char(path), offset);
  692. for (group = 0; group < MAX_CHNL_GROUP_5G; group++) {
  693. if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path)) {
  694. tmp_base = map_read8(txpwr_map, offset);
  695. if (!IS_PG_TXPWR_BASE_INVALID(hal_spec, tmp_base)
  696. && IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexBW40_Base[path][group])
  697. ) {
  698. pwr_info->IndexBW40_Base[path][group] = tmp_base;
  699. if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
  700. RTW_INFO("[%c] 5G G%02d BW40-1S base:%u from %s\n", rf_path_char(path), group, tmp_base, pg_txpwr_src_str(txpwr_src));
  701. }
  702. }
  703. offset++;
  704. }
  705. for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
  706. if (tx_idx == 0) {
  707. if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) {
  708. val = map_read8(txpwr_map, offset);
  709. tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
  710. if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
  711. && IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])
  712. ) {
  713. pwr_info->BW20_Diff[path][tx_idx] = tmp_diff;
  714. if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
  715. RTW_INFO("[%c] 5G BW20-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
  716. }
  717. tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
  718. if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
  719. && IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx])
  720. ) {
  721. pwr_info->OFDM_Diff[path][tx_idx] = tmp_diff;
  722. if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
  723. RTW_INFO("[%c] 5G OFDM-%dT diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
  724. }
  725. }
  726. offset++;
  727. } else {
  728. if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) {
  729. val = map_read8(txpwr_map, offset);
  730. tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
  731. if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
  732. && IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW40_Diff[path][tx_idx])
  733. ) {
  734. pwr_info->BW40_Diff[path][tx_idx] = tmp_diff;
  735. if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
  736. RTW_INFO("[%c] 5G BW40-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
  737. }
  738. tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
  739. if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
  740. && IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])
  741. ) {
  742. pwr_info->BW20_Diff[path][tx_idx] = tmp_diff;
  743. if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
  744. RTW_INFO("[%c] 5G BW20-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
  745. }
  746. }
  747. offset++;
  748. }
  749. }
  750. /* OFDM diff 2T ~ 3T */
  751. if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, 1)) {
  752. val = map_read8(txpwr_map, offset);
  753. tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
  754. if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
  755. && IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][1])
  756. ) {
  757. pwr_info->OFDM_Diff[path][1] = tmp_diff;
  758. if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
  759. RTW_INFO("[%c] 5G OFDM-%dT diff:%d from %s\n", rf_path_char(path), 2, tmp_diff, pg_txpwr_src_str(txpwr_src));
  760. }
  761. if (HAL_SPEC_CHK_TX_CNT(hal_spec, 2)) {
  762. tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
  763. if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
  764. && IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][2])
  765. ) {
  766. pwr_info->OFDM_Diff[path][2] = tmp_diff;
  767. if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
  768. RTW_INFO("[%c] 5G OFDM-%dT diff:%d from %s\n", rf_path_char(path), 3, tmp_diff, pg_txpwr_src_str(txpwr_src));
  769. }
  770. }
  771. }
  772. offset++;
  773. /* OFDM diff 4T */
  774. if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, 3)) {
  775. val = map_read8(txpwr_map, offset);
  776. tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
  777. if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
  778. && IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][3])
  779. ) {
  780. pwr_info->OFDM_Diff[path][3] = tmp_diff;
  781. if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
  782. RTW_INFO("[%c] 5G OFDM-%dT diff:%d from %s\n", rf_path_char(path), 4, tmp_diff, pg_txpwr_src_str(txpwr_src));
  783. }
  784. }
  785. offset++;
  786. for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
  787. if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) {
  788. val = map_read8(txpwr_map, offset);
  789. tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
  790. if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
  791. && IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW80_Diff[path][tx_idx])
  792. ) {
  793. pwr_info->BW80_Diff[path][tx_idx] = tmp_diff;
  794. if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
  795. RTW_INFO("[%c] 5G BW80-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
  796. }
  797. tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
  798. if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
  799. && IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW160_Diff[path][tx_idx])
  800. ) {
  801. pwr_info->BW160_Diff[path][tx_idx] = tmp_diff;
  802. if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
  803. RTW_INFO("[%c] 5G BW160-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
  804. }
  805. }
  806. offset++;
  807. }
  808. if (offset != pg_offset + PG_TXPWR_1PATH_BYTE_NUM_5G) {
  809. RTW_ERR("%s parse %d bytes != %d\n", __func__, offset - pg_offset, PG_TXPWR_1PATH_BYTE_NUM_5G);
  810. rtw_warn_on(1);
  811. }
  812. #endif /* #ifdef CONFIG_IEEE80211_BAND_5GHZ */
  813. exit:
  814. return offset;
  815. }
  816. void hal_load_pg_txpwr_info(
  817. _adapter *adapter,
  818. TxPowerInfo24G *pwr_info_2g,
  819. TxPowerInfo5G *pwr_info_5g,
  820. u8 *pg_data,
  821. BOOLEAN AutoLoadFail
  822. )
  823. {
  824. struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
  825. u8 path;
  826. u16 pg_offset;
  827. u8 txpwr_src = PG_TXPWR_SRC_PG_DATA;
  828. struct map_t pg_data_map = MAP_ENT(184, 1, 0xFF, MAPSEG_PTR_ENT(0x00, 184, pg_data));
  829. const struct map_t *txpwr_map = NULL;
  830. /* init with invalid value and some dummy base and diff */
  831. hal_init_pg_txpwr_info_2g(adapter, pwr_info_2g);
  832. hal_init_pg_txpwr_info_5g(adapter, pwr_info_5g);
  833. select_src:
  834. pg_offset = hal_spec->pg_txpwr_saddr;
  835. switch (txpwr_src) {
  836. case PG_TXPWR_SRC_PG_DATA:
  837. txpwr_map = &pg_data_map;
  838. break;
  839. case PG_TXPWR_SRC_IC_DEF:
  840. txpwr_map = hal_pg_txpwr_def_info(adapter);
  841. break;
  842. case PG_TXPWR_SRC_DEF:
  843. default:
  844. txpwr_map = &pg_txpwr_def_info;
  845. break;
  846. };
  847. if (txpwr_map == NULL)
  848. goto end_parse;
  849. for (path = 0; path < MAX_RF_PATH ; path++) {
  850. if (!HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && !HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path))
  851. break;
  852. pg_offset = hal_load_pg_txpwr_info_path_2g(adapter, pwr_info_2g, path, txpwr_src, txpwr_map, pg_offset);
  853. pg_offset = hal_load_pg_txpwr_info_path_5g(adapter, pwr_info_5g, path, txpwr_src, txpwr_map, pg_offset);
  854. }
  855. if (hal_chk_pg_txpwr_info_2g(adapter, pwr_info_2g) == _SUCCESS
  856. && hal_chk_pg_txpwr_info_5g(adapter, pwr_info_5g) == _SUCCESS)
  857. goto exit;
  858. end_parse:
  859. txpwr_src++;
  860. if (txpwr_src < PG_TXPWR_SRC_NUM)
  861. goto select_src;
  862. if (hal_chk_pg_txpwr_info_2g(adapter, pwr_info_2g) != _SUCCESS
  863. || hal_chk_pg_txpwr_info_5g(adapter, pwr_info_5g) != _SUCCESS)
  864. rtw_warn_on(1);
  865. exit:
  866. #if DBG_PG_TXPWR_READ
  867. if (pwr_info_2g)
  868. dump_pg_txpwr_info_2g(RTW_DBGDUMP, pwr_info_2g, 4, 4);
  869. if (pwr_info_5g)
  870. dump_pg_txpwr_info_5g(RTW_DBGDUMP, pwr_info_5g, 4, 4);
  871. #endif
  872. return;
  873. }
  874. #ifdef CONFIG_EFUSE_CONFIG_FILE
  875. #define EFUSE_POWER_INDEX_INVALID 0xFF
  876. static u8 _check_phy_efuse_tx_power_info_valid(u8 *pg_data, int base_len, u16 pg_offset)
  877. {
  878. int ff_cnt = 0;
  879. int i;
  880. for (i = 0; i < base_len; i++) {
  881. if (*(pg_data + pg_offset + i) == 0xFF)
  882. ff_cnt++;
  883. }
  884. if (ff_cnt == 0)
  885. return _TRUE;
  886. else if (ff_cnt == base_len)
  887. return _FALSE;
  888. else
  889. return EFUSE_POWER_INDEX_INVALID;
  890. }
  891. int check_phy_efuse_tx_power_info_valid(_adapter *adapter)
  892. {
  893. struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
  894. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
  895. u8 *pg_data = hal_data->efuse_eeprom_data;
  896. u16 pg_offset = hal_spec->pg_txpwr_saddr;
  897. u8 path;
  898. u8 valid_2g_path_bmp = 0;
  899. #ifdef CONFIG_IEEE80211_BAND_5GHZ
  900. u8 valid_5g_path_bmp = 0;
  901. #endif
  902. int result = _FALSE;
  903. for (path = 0; path < MAX_RF_PATH; path++) {
  904. u8 ret = _FALSE;
  905. if (!HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && !HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path))
  906. break;
  907. if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path)) {
  908. ret = _check_phy_efuse_tx_power_info_valid(pg_data, PG_TXPWR_BASE_BYTE_NUM_2G, pg_offset);
  909. if (ret == _TRUE)
  910. valid_2g_path_bmp |= BIT(path);
  911. else if (ret == EFUSE_POWER_INDEX_INVALID)
  912. return _FALSE;
  913. }
  914. pg_offset += PG_TXPWR_1PATH_BYTE_NUM_2G;
  915. #ifdef CONFIG_IEEE80211_BAND_5GHZ
  916. if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path)) {
  917. ret = _check_phy_efuse_tx_power_info_valid(pg_data, PG_TXPWR_BASE_BYTE_NUM_5G, pg_offset);
  918. if (ret == _TRUE)
  919. valid_5g_path_bmp |= BIT(path);
  920. else if (ret == EFUSE_POWER_INDEX_INVALID)
  921. return _FALSE;
  922. }
  923. #endif
  924. pg_offset += PG_TXPWR_1PATH_BYTE_NUM_5G;
  925. }
  926. if ((hal_chk_band_cap(adapter, BAND_CAP_2G) && valid_2g_path_bmp)
  927. #ifdef CONFIG_IEEE80211_BAND_5GHZ
  928. || (hal_chk_band_cap(adapter, BAND_CAP_5G) && valid_5g_path_bmp)
  929. #endif
  930. )
  931. return _TRUE;
  932. return _FALSE;
  933. }
  934. #endif /* CONFIG_EFUSE_CONFIG_FILE */
  935. void hal_load_txpwr_info(
  936. _adapter *adapter,
  937. TxPowerInfo24G *pwr_info_2g,
  938. TxPowerInfo5G *pwr_info_5g,
  939. u8 *pg_data
  940. )
  941. {
  942. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
  943. struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
  944. u8 max_tx_cnt = hal_spec->max_tx_cnt;
  945. u8 rfpath, ch_idx, group, tx_idx;
  946. /* load from pg data (or default value) */
  947. hal_load_pg_txpwr_info(adapter, pwr_info_2g, pwr_info_5g, pg_data, _FALSE);
  948. /* transform to hal_data */
  949. for (rfpath = 0; rfpath < MAX_RF_PATH; rfpath++) {
  950. if (!pwr_info_2g || !HAL_SPEC_CHK_RF_PATH_2G(hal_spec, rfpath))
  951. goto bypass_2g;
  952. /* 2.4G base */
  953. for (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++) {
  954. u8 cck_group;
  955. if (rtw_get_ch_group(ch_idx + 1, &group, &cck_group) != BAND_ON_2_4G)
  956. continue;
  957. hal_data->Index24G_CCK_Base[rfpath][ch_idx] = pwr_info_2g->IndexCCK_Base[rfpath][cck_group];
  958. hal_data->Index24G_BW40_Base[rfpath][ch_idx] = pwr_info_2g->IndexBW40_Base[rfpath][group];
  959. }
  960. /* 2.4G diff */
  961. for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
  962. if (tx_idx >= max_tx_cnt)
  963. break;
  964. hal_data->CCK_24G_Diff[rfpath][tx_idx] = pwr_info_2g->CCK_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
  965. hal_data->OFDM_24G_Diff[rfpath][tx_idx] = pwr_info_2g->OFDM_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
  966. hal_data->BW20_24G_Diff[rfpath][tx_idx] = pwr_info_2g->BW20_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
  967. hal_data->BW40_24G_Diff[rfpath][tx_idx] = pwr_info_2g->BW40_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
  968. }
  969. bypass_2g:
  970. ;
  971. #ifdef CONFIG_IEEE80211_BAND_5GHZ
  972. if (!pwr_info_5g || !HAL_SPEC_CHK_RF_PATH_5G(hal_spec, rfpath))
  973. goto bypass_5g;
  974. /* 5G base */
  975. for (ch_idx = 0; ch_idx < CENTER_CH_5G_ALL_NUM; ch_idx++) {
  976. if (rtw_get_ch_group(center_ch_5g_all[ch_idx], &group, NULL) != BAND_ON_5G)
  977. continue;
  978. hal_data->Index5G_BW40_Base[rfpath][ch_idx] = pwr_info_5g->IndexBW40_Base[rfpath][group];
  979. }
  980. for (ch_idx = 0 ; ch_idx < CENTER_CH_5G_80M_NUM; ch_idx++) {
  981. u8 upper, lower;
  982. if (rtw_get_ch_group(center_ch_5g_80m[ch_idx], &group, NULL) != BAND_ON_5G)
  983. continue;
  984. upper = pwr_info_5g->IndexBW40_Base[rfpath][group];
  985. lower = pwr_info_5g->IndexBW40_Base[rfpath][group + 1];
  986. hal_data->Index5G_BW80_Base[rfpath][ch_idx] = (upper + lower) / 2;
  987. }
  988. /* 5G diff */
  989. for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
  990. if (tx_idx >= max_tx_cnt)
  991. break;
  992. hal_data->OFDM_5G_Diff[rfpath][tx_idx] = pwr_info_5g->OFDM_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
  993. hal_data->BW20_5G_Diff[rfpath][tx_idx] = pwr_info_5g->BW20_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
  994. hal_data->BW40_5G_Diff[rfpath][tx_idx] = pwr_info_5g->BW40_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
  995. hal_data->BW80_5G_Diff[rfpath][tx_idx] = pwr_info_5g->BW80_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
  996. }
  997. bypass_5g:
  998. ;
  999. #endif /* CONFIG_IEEE80211_BAND_5GHZ */
  1000. }
  1001. }
  1002. void dump_hal_txpwr_info_2g(void *sel, _adapter *adapter, u8 rfpath_num, u8 max_tx_cnt)
  1003. {
  1004. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
  1005. int path, ch_idx, tx_idx;
  1006. RTW_PRINT_SEL(sel, "2.4G\n");
  1007. RTW_PRINT_SEL(sel, "CCK-1T base:\n");
  1008. RTW_PRINT_SEL(sel, "%4s ", "");
  1009. for (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++)
  1010. _RTW_PRINT_SEL(sel, "%2d ", center_ch_2g[ch_idx]);
  1011. _RTW_PRINT_SEL(sel, "\n");
  1012. for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
  1013. RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
  1014. for (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++)
  1015. _RTW_PRINT_SEL(sel, "%2u ", hal_data->Index24G_CCK_Base[path][ch_idx]);
  1016. _RTW_PRINT_SEL(sel, "\n");
  1017. }
  1018. RTW_PRINT_SEL(sel, "\n");
  1019. RTW_PRINT_SEL(sel, "CCK diff:\n");
  1020. RTW_PRINT_SEL(sel, "%4s ", "");
  1021. for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
  1022. _RTW_PRINT_SEL(sel, "%dT ", tx_idx + 1);
  1023. _RTW_PRINT_SEL(sel, "\n");
  1024. for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
  1025. RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
  1026. for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
  1027. _RTW_PRINT_SEL(sel, "%2d ", hal_data->CCK_24G_Diff[path][tx_idx]);
  1028. _RTW_PRINT_SEL(sel, "\n");
  1029. }
  1030. RTW_PRINT_SEL(sel, "\n");
  1031. RTW_PRINT_SEL(sel, "BW40-1S base:\n");
  1032. RTW_PRINT_SEL(sel, "%4s ", "");
  1033. for (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++)
  1034. _RTW_PRINT_SEL(sel, "%2d ", center_ch_2g[ch_idx]);
  1035. _RTW_PRINT_SEL(sel, "\n");
  1036. for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
  1037. RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
  1038. for (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++)
  1039. _RTW_PRINT_SEL(sel, "%2u ", hal_data->Index24G_BW40_Base[path][ch_idx]);
  1040. _RTW_PRINT_SEL(sel, "\n");
  1041. }
  1042. RTW_PRINT_SEL(sel, "\n");
  1043. RTW_PRINT_SEL(sel, "OFDM diff:\n");
  1044. RTW_PRINT_SEL(sel, "%4s ", "");
  1045. for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
  1046. _RTW_PRINT_SEL(sel, "%dT ", tx_idx + 1);
  1047. _RTW_PRINT_SEL(sel, "\n");
  1048. for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
  1049. RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
  1050. for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
  1051. _RTW_PRINT_SEL(sel, "%2d ", hal_data->OFDM_24G_Diff[path][tx_idx]);
  1052. _RTW_PRINT_SEL(sel, "\n");
  1053. }
  1054. RTW_PRINT_SEL(sel, "\n");
  1055. RTW_PRINT_SEL(sel, "BW20 diff:\n");
  1056. RTW_PRINT_SEL(sel, "%4s ", "");
  1057. for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
  1058. _RTW_PRINT_SEL(sel, "%dS ", tx_idx + 1);
  1059. _RTW_PRINT_SEL(sel, "\n");
  1060. for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
  1061. RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
  1062. for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
  1063. _RTW_PRINT_SEL(sel, "%2d ", hal_data->BW20_24G_Diff[path][tx_idx]);
  1064. _RTW_PRINT_SEL(sel, "\n");
  1065. }
  1066. RTW_PRINT_SEL(sel, "\n");
  1067. RTW_PRINT_SEL(sel, "BW40 diff:\n");
  1068. RTW_PRINT_SEL(sel, "%4s ", "");
  1069. for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
  1070. _RTW_PRINT_SEL(sel, "%dS ", tx_idx + 1);
  1071. _RTW_PRINT_SEL(sel, "\n");
  1072. for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
  1073. RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
  1074. for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
  1075. _RTW_PRINT_SEL(sel, "%2d ", hal_data->BW40_24G_Diff[path][tx_idx]);
  1076. _RTW_PRINT_SEL(sel, "\n");
  1077. }
  1078. RTW_PRINT_SEL(sel, "\n");
  1079. }
  1080. void dump_hal_txpwr_info_5g(void *sel, _adapter *adapter, u8 rfpath_num, u8 max_tx_cnt)
  1081. {
  1082. #ifdef CONFIG_IEEE80211_BAND_5GHZ
  1083. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
  1084. int path, ch_idx, tx_idx;
  1085. u8 dump_section = 0;
  1086. u8 ch_idx_s = 0;
  1087. RTW_PRINT_SEL(sel, "5G\n");
  1088. RTW_PRINT_SEL(sel, "BW40-1S base:\n");
  1089. do {
  1090. #define DUMP_5G_BW40_BASE_SECTION_NUM 3
  1091. u8 end[DUMP_5G_BW40_BASE_SECTION_NUM] = {64, 144, 177};
  1092. RTW_PRINT_SEL(sel, "%4s ", "");
  1093. for (ch_idx = ch_idx_s; ch_idx < CENTER_CH_5G_ALL_NUM; ch_idx++) {
  1094. _RTW_PRINT_SEL(sel, "%3d ", center_ch_5g_all[ch_idx]);
  1095. if (end[dump_section] == center_ch_5g_all[ch_idx])
  1096. break;
  1097. }
  1098. _RTW_PRINT_SEL(sel, "\n");
  1099. for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
  1100. RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
  1101. for (ch_idx = ch_idx_s; ch_idx < CENTER_CH_5G_ALL_NUM; ch_idx++) {
  1102. _RTW_PRINT_SEL(sel, "%3u ", hal_data->Index5G_BW40_Base[path][ch_idx]);
  1103. if (end[dump_section] == center_ch_5g_all[ch_idx])
  1104. break;
  1105. }
  1106. _RTW_PRINT_SEL(sel, "\n");
  1107. }
  1108. RTW_PRINT_SEL(sel, "\n");
  1109. ch_idx_s = ch_idx + 1;
  1110. dump_section++;
  1111. if (dump_section >= DUMP_5G_BW40_BASE_SECTION_NUM)
  1112. break;
  1113. } while (1);
  1114. RTW_PRINT_SEL(sel, "BW80-1S base:\n");
  1115. RTW_PRINT_SEL(sel, "%4s ", "");
  1116. for (ch_idx = 0; ch_idx < CENTER_CH_5G_80M_NUM; ch_idx++)
  1117. _RTW_PRINT_SEL(sel, "%3d ", center_ch_5g_80m[ch_idx]);
  1118. _RTW_PRINT_SEL(sel, "\n");
  1119. for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
  1120. RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
  1121. for (ch_idx = 0; ch_idx < CENTER_CH_5G_80M_NUM; ch_idx++)
  1122. _RTW_PRINT_SEL(sel, "%3u ", hal_data->Index5G_BW80_Base[path][ch_idx]);
  1123. _RTW_PRINT_SEL(sel, "\n");
  1124. }
  1125. RTW_PRINT_SEL(sel, "\n");
  1126. RTW_PRINT_SEL(sel, "OFDM diff:\n");
  1127. RTW_PRINT_SEL(sel, "%4s ", "");
  1128. for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
  1129. _RTW_PRINT_SEL(sel, "%dT ", tx_idx + 1);
  1130. _RTW_PRINT_SEL(sel, "\n");
  1131. for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
  1132. RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
  1133. for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
  1134. _RTW_PRINT_SEL(sel, "%2d ", hal_data->OFDM_5G_Diff[path][tx_idx]);
  1135. _RTW_PRINT_SEL(sel, "\n");
  1136. }
  1137. RTW_PRINT_SEL(sel, "\n");
  1138. RTW_PRINT_SEL(sel, "BW20 diff:\n");
  1139. RTW_PRINT_SEL(sel, "%4s ", "");
  1140. for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
  1141. _RTW_PRINT_SEL(sel, "%dS ", tx_idx + 1);
  1142. _RTW_PRINT_SEL(sel, "\n");
  1143. for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
  1144. RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
  1145. for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
  1146. _RTW_PRINT_SEL(sel, "%2d ", hal_data->BW20_5G_Diff[path][tx_idx]);
  1147. _RTW_PRINT_SEL(sel, "\n");
  1148. }
  1149. RTW_PRINT_SEL(sel, "\n");
  1150. RTW_PRINT_SEL(sel, "BW40 diff:\n");
  1151. RTW_PRINT_SEL(sel, "%4s ", "");
  1152. for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
  1153. _RTW_PRINT_SEL(sel, "%dS ", tx_idx + 1);
  1154. _RTW_PRINT_SEL(sel, "\n");
  1155. for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
  1156. RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
  1157. for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
  1158. _RTW_PRINT_SEL(sel, "%2d ", hal_data->BW40_5G_Diff[path][tx_idx]);
  1159. _RTW_PRINT_SEL(sel, "\n");
  1160. }
  1161. RTW_PRINT_SEL(sel, "\n");
  1162. RTW_PRINT_SEL(sel, "BW80 diff:\n");
  1163. RTW_PRINT_SEL(sel, "%4s ", "");
  1164. for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
  1165. _RTW_PRINT_SEL(sel, "%dS ", tx_idx + 1);
  1166. _RTW_PRINT_SEL(sel, "\n");
  1167. for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
  1168. RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
  1169. for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
  1170. _RTW_PRINT_SEL(sel, "%2d ", hal_data->BW80_5G_Diff[path][tx_idx]);
  1171. _RTW_PRINT_SEL(sel, "\n");
  1172. }
  1173. RTW_PRINT_SEL(sel, "\n");
  1174. #endif /* CONFIG_IEEE80211_BAND_5GHZ */
  1175. }
  1176. /*
  1177. * rtw_regsty_get_target_tx_power -
  1178. *
  1179. * Return dBm or -1 for undefined
  1180. */
  1181. s8 rtw_regsty_get_target_tx_power(
  1182. IN PADAPTER Adapter,
  1183. IN u8 Band,
  1184. IN u8 RfPath,
  1185. IN RATE_SECTION RateSection
  1186. )
  1187. {
  1188. struct registry_priv *regsty = adapter_to_regsty(Adapter);
  1189. s8 value = 0;
  1190. if (RfPath > RF_PATH_D) {
  1191. RTW_PRINT("%s invalid RfPath:%d\n", __func__, RfPath);
  1192. return -1;
  1193. }
  1194. if (Band != BAND_ON_2_4G
  1195. #ifdef CONFIG_IEEE80211_BAND_5GHZ
  1196. && Band != BAND_ON_5G
  1197. #endif
  1198. ) {
  1199. RTW_PRINT("%s invalid Band:%d\n", __func__, Band);
  1200. return -1;
  1201. }
  1202. if (RateSection >= RATE_SECTION_NUM
  1203. #ifdef CONFIG_IEEE80211_BAND_5GHZ
  1204. || (Band == BAND_ON_5G && RateSection == CCK)
  1205. #endif
  1206. ) {
  1207. RTW_PRINT("%s invalid RateSection:%d in Band:%d, RfPath:%d\n", __func__
  1208. , RateSection, Band, RfPath);
  1209. return -1;
  1210. }
  1211. if (Band == BAND_ON_2_4G)
  1212. value = regsty->target_tx_pwr_2g[RfPath][RateSection];
  1213. #ifdef CONFIG_IEEE80211_BAND_5GHZ
  1214. else /* BAND_ON_5G */
  1215. value = regsty->target_tx_pwr_5g[RfPath][RateSection - 1];
  1216. #endif
  1217. return value;
  1218. }
  1219. bool rtw_regsty_chk_target_tx_power_valid(_adapter *adapter)
  1220. {
  1221. struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
  1222. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
  1223. int path, tx_num, band, rs;
  1224. s8 target;
  1225. for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
  1226. if (!hal_is_band_support(adapter, band))
  1227. continue;
  1228. for (path = 0; path < RF_PATH_MAX; path++) {
  1229. if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
  1230. break;
  1231. for (rs = 0; rs < RATE_SECTION_NUM; rs++) {
  1232. tx_num = rate_section_to_tx_num(rs);
  1233. if (tx_num >= hal_spec->tx_nss_num)
  1234. continue;
  1235. if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
  1236. continue;
  1237. if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter))
  1238. continue;
  1239. target = rtw_regsty_get_target_tx_power(adapter, band, path, rs);
  1240. if (target == -1) {
  1241. RTW_PRINT("%s return _FALSE for band:%d, path:%d, rs:%d, t:%d\n", __func__, band, path, rs, target);
  1242. return _FALSE;
  1243. }
  1244. }
  1245. }
  1246. }
  1247. return _TRUE;
  1248. }
  1249. /*
  1250. * PHY_GetTxPowerByRateBase -
  1251. *
  1252. * Return value in unit of TX Gain Index
  1253. */
  1254. u8
  1255. PHY_GetTxPowerByRateBase(
  1256. IN PADAPTER Adapter,
  1257. IN u8 Band,
  1258. IN u8 RfPath,
  1259. IN RATE_SECTION RateSection
  1260. )
  1261. {
  1262. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
  1263. u8 value = 0;
  1264. if (RfPath > RF_PATH_D) {
  1265. RTW_PRINT("%s invalid RfPath:%d\n", __func__, RfPath);
  1266. return 0;
  1267. }
  1268. if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {
  1269. RTW_PRINT("%s invalid Band:%d\n", __func__, Band);
  1270. return 0;
  1271. }
  1272. if (RateSection >= RATE_SECTION_NUM
  1273. || (Band == BAND_ON_5G && RateSection == CCK)
  1274. ) {
  1275. RTW_PRINT("%s invalid RateSection:%d in Band:%d, RfPath:%d\n", __func__
  1276. , RateSection, Band, RfPath);
  1277. return 0;
  1278. }
  1279. if (Band == BAND_ON_2_4G)
  1280. value = pHalData->TxPwrByRateBase2_4G[RfPath][RateSection];
  1281. else /* BAND_ON_5G */
  1282. value = pHalData->TxPwrByRateBase5G[RfPath][RateSection - 1];
  1283. return value;
  1284. }
  1285. VOID
  1286. phy_SetTxPowerByRateBase(
  1287. IN PADAPTER Adapter,
  1288. IN u8 Band,
  1289. IN u8 RfPath,
  1290. IN RATE_SECTION RateSection,
  1291. IN u8 Value
  1292. )
  1293. {
  1294. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
  1295. if (RfPath > RF_PATH_D) {
  1296. RTW_PRINT("%s invalid RfPath:%d\n", __func__, RfPath);
  1297. return;
  1298. }
  1299. if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {
  1300. RTW_PRINT("%s invalid Band:%d\n", __func__, Band);
  1301. return;
  1302. }
  1303. if (RateSection >= RATE_SECTION_NUM
  1304. || (Band == BAND_ON_5G && RateSection == CCK)
  1305. ) {
  1306. RTW_PRINT("%s invalid RateSection:%d in %sG, RfPath:%d\n", __func__
  1307. , RateSection, (Band == BAND_ON_2_4G) ? "2.4" : "5", RfPath);
  1308. return;
  1309. }
  1310. if (Band == BAND_ON_2_4G)
  1311. pHalData->TxPwrByRateBase2_4G[RfPath][RateSection] = Value;
  1312. else /* BAND_ON_5G */
  1313. pHalData->TxPwrByRateBase5G[RfPath][RateSection - 1] = Value;
  1314. }
  1315. static inline BOOLEAN phy_is_txpwr_by_rate_undefined_of_band_path(_adapter *adapter, u8 band, u8 path)
  1316. {
  1317. struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
  1318. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
  1319. u8 rate_idx = 0;
  1320. for (rate_idx = 0; rate_idx < TX_PWR_BY_RATE_NUM_RATE; rate_idx++) {
  1321. if (hal_data->TxPwrByRateOffset[band][path][rate_idx] != 0)
  1322. goto exit;
  1323. }
  1324. exit:
  1325. return rate_idx >= TX_PWR_BY_RATE_NUM_RATE ? _TRUE : _FALSE;
  1326. }
  1327. static inline void phy_txpwr_by_rate_duplicate_band_path(_adapter *adapter, u8 band, u8 s_path, u8 t_path)
  1328. {
  1329. struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
  1330. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
  1331. u8 rate_idx = 0;
  1332. for (rate_idx = 0; rate_idx < TX_PWR_BY_RATE_NUM_RATE; rate_idx++)
  1333. hal_data->TxPwrByRateOffset[band][t_path][rate_idx] = hal_data->TxPwrByRateOffset[band][s_path][rate_idx];
  1334. }
  1335. static void phy_txpwr_by_rate_chk_for_path_dup(_adapter *adapter)
  1336. {
  1337. struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
  1338. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
  1339. u8 band, path;
  1340. s8 src_path;
  1341. for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++)
  1342. for (path = RF_PATH_A; path < RF_PATH_MAX; path++)
  1343. hal_data->txpwr_by_rate_undefined_band_path[band][path] = 0;
  1344. for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
  1345. if (!hal_is_band_support(adapter, band))
  1346. continue;
  1347. for (path = RF_PATH_A; path < RF_PATH_MAX; path++) {
  1348. if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
  1349. continue;
  1350. if (phy_is_txpwr_by_rate_undefined_of_band_path(adapter, band, path))
  1351. hal_data->txpwr_by_rate_undefined_band_path[band][path] = 1;
  1352. }
  1353. }
  1354. for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
  1355. if (!hal_is_band_support(adapter, band))
  1356. continue;
  1357. src_path = -1;
  1358. for (path = RF_PATH_A; path < RF_PATH_MAX; path++) {
  1359. if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
  1360. continue;
  1361. /* find src */
  1362. if (src_path == -1 && hal_data->txpwr_by_rate_undefined_band_path[band][path] == 0)
  1363. src_path = path;
  1364. }
  1365. if (src_path == -1) {
  1366. RTW_ERR("%s all power by rate undefined\n", __func__);
  1367. continue;
  1368. }
  1369. for (path = RF_PATH_A; path < RF_PATH_MAX; path++) {
  1370. if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
  1371. continue;
  1372. /* duplicate src to undefined one */
  1373. if (hal_data->txpwr_by_rate_undefined_band_path[band][path] == 1) {
  1374. RTW_INFO("%s duplicate %s [%c] to [%c]\n", __func__
  1375. , band_str(band), rf_path_char(src_path), rf_path_char(path));
  1376. phy_txpwr_by_rate_duplicate_band_path(adapter, band, src_path, path);
  1377. }
  1378. }
  1379. }
  1380. }
  1381. VOID
  1382. phy_StoreTxPowerByRateBase(
  1383. IN PADAPTER pAdapter
  1384. )
  1385. {
  1386. struct hal_spec_t *hal_spec = GET_HAL_SPEC(pAdapter);
  1387. struct registry_priv *regsty = adapter_to_regsty(pAdapter);
  1388. u8 rate_sec_base[RATE_SECTION_NUM] = {
  1389. MGN_11M,
  1390. MGN_54M,
  1391. MGN_MCS7,
  1392. MGN_MCS15,
  1393. MGN_MCS23,
  1394. MGN_MCS31,
  1395. MGN_VHT1SS_MCS7,
  1396. MGN_VHT2SS_MCS7,
  1397. MGN_VHT3SS_MCS7,
  1398. MGN_VHT4SS_MCS7,
  1399. };
  1400. u8 band, path, rs, tx_num, base, index;
  1401. for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
  1402. if (!hal_is_band_support(pAdapter, band))
  1403. continue;
  1404. for (path = RF_PATH_A; path < RF_PATH_MAX; path++) {
  1405. if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
  1406. break;
  1407. for (rs = 0; rs < RATE_SECTION_NUM; rs++) {
  1408. tx_num = rate_section_to_tx_num(rs);
  1409. if (tx_num >= hal_spec->tx_nss_num)
  1410. continue;
  1411. if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
  1412. continue;
  1413. if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter))
  1414. continue;
  1415. if (regsty->target_tx_pwr_valid == _TRUE)
  1416. base = hal_spec->txgi_pdbm * rtw_regsty_get_target_tx_power(pAdapter, band, path, rs);
  1417. else
  1418. base = _PHY_GetTxPowerByRate(pAdapter, band, path, rate_sec_base[rs]);
  1419. phy_SetTxPowerByRateBase(pAdapter, band, path, rs, base);
  1420. }
  1421. }
  1422. }
  1423. }
  1424. static u8 get_val_from_dhex(u32 dhex, u8 i)
  1425. {
  1426. return (((dhex >> (i * 8 + 4)) & 0xF)) * 10 + ((dhex >> (i * 8)) & 0xF);
  1427. }
  1428. static u8 get_val_from_hex(u32 hex, u8 i)
  1429. {
  1430. return (hex >> (i * 8)) & 0xFF;
  1431. }
  1432. VOID
  1433. PHY_GetRateValuesOfTxPowerByRate(
  1434. IN PADAPTER pAdapter,
  1435. IN u32 RegAddr,
  1436. IN u32 BitMask,
  1437. IN u32 Value,
  1438. OUT u8 *Rate,
  1439. OUT s8 *PwrByRateVal,
  1440. OUT u8 *RateNum
  1441. )
  1442. {
  1443. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
  1444. struct hal_spec_t *hal_spec = GET_HAL_SPEC(pAdapter);
  1445. struct dm_struct *pDM_Odm = &pHalData->odmpriv;
  1446. u8 index = 0, i = 0;
  1447. u8 (*get_val)(u32, u8);
  1448. if (hal_spec->txgi_pdbm == 2)
  1449. get_val = get_val_from_dhex;
  1450. else
  1451. get_val = get_val_from_hex;
  1452. switch (RegAddr) {
  1453. case rTxAGC_A_Rate18_06:
  1454. case rTxAGC_B_Rate18_06:
  1455. Rate[0] = MGN_6M;
  1456. Rate[1] = MGN_9M;
  1457. Rate[2] = MGN_12M;
  1458. Rate[3] = MGN_18M;
  1459. for (i = 0; i < 4; ++i)
  1460. PwrByRateVal[i] = (s8)get_val(Value, i);
  1461. *RateNum = 4;
  1462. break;
  1463. case rTxAGC_A_Rate54_24:
  1464. case rTxAGC_B_Rate54_24:
  1465. Rate[0] = MGN_24M;
  1466. Rate[1] = MGN_36M;
  1467. Rate[2] = MGN_48M;
  1468. Rate[3] = MGN_54M;
  1469. for (i = 0; i < 4; ++i)
  1470. PwrByRateVal[i] = (s8)get_val(Value, i);
  1471. *RateNum = 4;
  1472. break;
  1473. case rTxAGC_A_CCK1_Mcs32:
  1474. Rate[0] = MGN_1M;
  1475. PwrByRateVal[0] = (s8)get_val(Value, 1);
  1476. *RateNum = 1;
  1477. break;
  1478. case rTxAGC_B_CCK11_A_CCK2_11:
  1479. if (BitMask == 0xffffff00) {
  1480. Rate[0] = MGN_2M;
  1481. Rate[1] = MGN_5_5M;
  1482. Rate[2] = MGN_11M;
  1483. for (i = 1; i < 4; ++i)
  1484. PwrByRateVal[i - 1] = (s8)get_val(Value, i);
  1485. *RateNum = 3;
  1486. } else if (BitMask == 0x000000ff) {
  1487. Rate[0] = MGN_11M;
  1488. PwrByRateVal[0] = (s8)get_val(Value, 0);
  1489. *RateNum = 1;
  1490. }
  1491. break;
  1492. case rTxAGC_A_Mcs03_Mcs00:
  1493. case rTxAGC_B_Mcs03_Mcs00:
  1494. Rate[0] = MGN_MCS0;
  1495. Rate[1] = MGN_MCS1;
  1496. Rate[2] = MGN_MCS2;
  1497. Rate[3] = MGN_MCS3;
  1498. for (i = 0; i < 4; ++i)
  1499. PwrByRateVal[i] = (s8)get_val(Value, i);
  1500. *RateNum = 4;
  1501. break;
  1502. case rTxAGC_A_Mcs07_Mcs04:
  1503. case rTxAGC_B_Mcs07_Mcs04:
  1504. Rate[0] = MGN_MCS4;
  1505. Rate[1] = MGN_MCS5;
  1506. Rate[2] = MGN_MCS6;
  1507. Rate[3] = MGN_MCS7;
  1508. for (i = 0; i < 4; ++i)
  1509. PwrByRateVal[i] = (s8)get_val(Value, i);
  1510. *RateNum = 4;
  1511. break;
  1512. case rTxAGC_A_Mcs11_Mcs08:
  1513. case rTxAGC_B_Mcs11_Mcs08:
  1514. Rate[0] = MGN_MCS8;
  1515. Rate[1] = MGN_MCS9;
  1516. Rate[2] = MGN_MCS10;
  1517. Rate[3] = MGN_MCS11;
  1518. for (i = 0; i < 4; ++i)
  1519. PwrByRateVal[i] = (s8)get_val(Value, i);
  1520. *RateNum = 4;
  1521. break;
  1522. case rTxAGC_A_Mcs15_Mcs12:
  1523. case rTxAGC_B_Mcs15_Mcs12:
  1524. Rate[0] = MGN_MCS12;
  1525. Rate[1] = MGN_MCS13;
  1526. Rate[2] = MGN_MCS14;
  1527. Rate[3] = MGN_MCS15;
  1528. for (i = 0; i < 4; ++i)
  1529. PwrByRateVal[i] = (s8)get_val(Value, i);
  1530. *RateNum = 4;
  1531. break;
  1532. case rTxAGC_B_CCK1_55_Mcs32:
  1533. Rate[0] = MGN_1M;
  1534. Rate[1] = MGN_2M;
  1535. Rate[2] = MGN_5_5M;
  1536. for (i = 1; i < 4; ++i)
  1537. PwrByRateVal[i - 1] = (s8)get_val(Value, i);
  1538. *RateNum = 3;
  1539. break;
  1540. case 0xC20:
  1541. case 0xE20:
  1542. case 0x1820:
  1543. case 0x1a20:
  1544. Rate[0] = MGN_1M;
  1545. Rate[1] = MGN_2M;
  1546. Rate[2] = MGN_5_5M;
  1547. Rate[3] = MGN_11M;
  1548. for (i = 0; i < 4; ++i)
  1549. PwrByRateVal[i] = (s8)get_val(Value, i);
  1550. *RateNum = 4;
  1551. break;
  1552. case 0xC24:
  1553. case 0xE24:
  1554. case 0x1824:
  1555. case 0x1a24:
  1556. Rate[0] = MGN_6M;
  1557. Rate[1] = MGN_9M;
  1558. Rate[2] = MGN_12M;
  1559. Rate[3] = MGN_18M;
  1560. for (i = 0; i < 4; ++i)
  1561. PwrByRateVal[i] = (s8)get_val(Value, i);
  1562. *RateNum = 4;
  1563. break;
  1564. case 0xC28:
  1565. case 0xE28:
  1566. case 0x1828:
  1567. case 0x1a28:
  1568. Rate[0] = MGN_24M;
  1569. Rate[1] = MGN_36M;
  1570. Rate[2] = MGN_48M;
  1571. Rate[3] = MGN_54M;
  1572. for (i = 0; i < 4; ++i)
  1573. PwrByRateVal[i] = (s8)get_val(Value, i);
  1574. *RateNum = 4;
  1575. break;
  1576. case 0xC2C:
  1577. case 0xE2C:
  1578. case 0x182C:
  1579. case 0x1a2C:
  1580. Rate[0] = MGN_MCS0;
  1581. Rate[1] = MGN_MCS1;
  1582. Rate[2] = MGN_MCS2;
  1583. Rate[3] = MGN_MCS3;
  1584. for (i = 0; i < 4; ++i)
  1585. PwrByRateVal[i] = (s8)get_val(Value, i);
  1586. *RateNum = 4;
  1587. break;
  1588. case 0xC30:
  1589. case 0xE30:
  1590. case 0x1830:
  1591. case 0x1a30:
  1592. Rate[0] = MGN_MCS4;
  1593. Rate[1] = MGN_MCS5;
  1594. Rate[2] = MGN_MCS6;
  1595. Rate[3] = MGN_MCS7;
  1596. for (i = 0; i < 4; ++i)
  1597. PwrByRateVal[i] = (s8)get_val(Value, i);
  1598. *RateNum = 4;
  1599. break;
  1600. case 0xC34:
  1601. case 0xE34:
  1602. case 0x1834:
  1603. case 0x1a34:
  1604. Rate[0] = MGN_MCS8;
  1605. Rate[1] = MGN_MCS9;
  1606. Rate[2] = MGN_MCS10;
  1607. Rate[3] = MGN_MCS11;
  1608. for (i = 0; i < 4; ++i)
  1609. PwrByRateVal[i] = (s8)get_val(Value, i);
  1610. *RateNum = 4;
  1611. break;
  1612. case 0xC38:
  1613. case 0xE38:
  1614. case 0x1838:
  1615. case 0x1a38:
  1616. Rate[0] = MGN_MCS12;
  1617. Rate[1] = MGN_MCS13;
  1618. Rate[2] = MGN_MCS14;
  1619. Rate[3] = MGN_MCS15;
  1620. for (i = 0; i < 4; ++i)
  1621. PwrByRateVal[i] = (s8)get_val(Value, i);
  1622. *RateNum = 4;
  1623. break;
  1624. case 0xC3C:
  1625. case 0xE3C:
  1626. case 0x183C:
  1627. case 0x1a3C:
  1628. Rate[0] = MGN_VHT1SS_MCS0;
  1629. Rate[1] = MGN_VHT1SS_MCS1;
  1630. Rate[2] = MGN_VHT1SS_MCS2;
  1631. Rate[3] = MGN_VHT1SS_MCS3;
  1632. for (i = 0; i < 4; ++i)
  1633. PwrByRateVal[i] = (s8)get_val(Value, i);
  1634. *RateNum = 4;
  1635. break;
  1636. case 0xC40:
  1637. case 0xE40:
  1638. case 0x1840:
  1639. case 0x1a40:
  1640. Rate[0] = MGN_VHT1SS_MCS4;
  1641. Rate[1] = MGN_VHT1SS_MCS5;
  1642. Rate[2] = MGN_VHT1SS_MCS6;
  1643. Rate[3] = MGN_VHT1SS_MCS7;
  1644. for (i = 0; i < 4; ++i)
  1645. PwrByRateVal[i] = (s8)get_val(Value, i);
  1646. *RateNum = 4;
  1647. break;
  1648. case 0xC44:
  1649. case 0xE44:
  1650. case 0x1844:
  1651. case 0x1a44:
  1652. Rate[0] = MGN_VHT1SS_MCS8;
  1653. Rate[1] = MGN_VHT1SS_MCS9;
  1654. Rate[2] = MGN_VHT2SS_MCS0;
  1655. Rate[3] = MGN_VHT2SS_MCS1;
  1656. for (i = 0; i < 4; ++i)
  1657. PwrByRateVal[i] = (s8)get_val(Value, i);
  1658. *RateNum = 4;
  1659. break;
  1660. case 0xC48:
  1661. case 0xE48:
  1662. case 0x1848:
  1663. case 0x1a48:
  1664. Rate[0] = MGN_VHT2SS_MCS2;
  1665. Rate[1] = MGN_VHT2SS_MCS3;
  1666. Rate[2] = MGN_VHT2SS_MCS4;
  1667. Rate[3] = MGN_VHT2SS_MCS5;
  1668. for (i = 0; i < 4; ++i)
  1669. PwrByRateVal[i] = (s8)get_val(Value, i);
  1670. *RateNum = 4;
  1671. break;
  1672. case 0xC4C:
  1673. case 0xE4C:
  1674. case 0x184C:
  1675. case 0x1a4C:
  1676. Rate[0] = MGN_VHT2SS_MCS6;
  1677. Rate[1] = MGN_VHT2SS_MCS7;
  1678. Rate[2] = MGN_VHT2SS_MCS8;
  1679. Rate[3] = MGN_VHT2SS_MCS9;
  1680. for (i = 0; i < 4; ++i)
  1681. PwrByRateVal[i] = (s8)get_val(Value, i);
  1682. *RateNum = 4;
  1683. break;
  1684. case 0xCD8:
  1685. case 0xED8:
  1686. case 0x18D8:
  1687. case 0x1aD8:
  1688. Rate[0] = MGN_MCS16;
  1689. Rate[1] = MGN_MCS17;
  1690. Rate[2] = MGN_MCS18;
  1691. Rate[3] = MGN_MCS19;
  1692. for (i = 0; i < 4; ++i)
  1693. PwrByRateVal[i] = (s8)get_val(Value, i);
  1694. *RateNum = 4;
  1695. break;
  1696. case 0xCDC:
  1697. case 0xEDC:
  1698. case 0x18DC:
  1699. case 0x1aDC:
  1700. Rate[0] = MGN_MCS20;
  1701. Rate[1] = MGN_MCS21;
  1702. Rate[2] = MGN_MCS22;
  1703. Rate[3] = MGN_MCS23;
  1704. for (i = 0; i < 4; ++i)
  1705. PwrByRateVal[i] = (s8)get_val(Value, i);
  1706. *RateNum = 4;
  1707. break;
  1708. case 0xCE0:
  1709. case 0xEE0:
  1710. case 0x18E0:
  1711. case 0x1aE0:
  1712. Rate[0] = MGN_VHT3SS_MCS0;
  1713. Rate[1] = MGN_VHT3SS_MCS1;
  1714. Rate[2] = MGN_VHT3SS_MCS2;
  1715. Rate[3] = MGN_VHT3SS_MCS3;
  1716. for (i = 0; i < 4; ++i)
  1717. PwrByRateVal[i] = (s8)get_val(Value, i);
  1718. *RateNum = 4;
  1719. break;
  1720. case 0xCE4:
  1721. case 0xEE4:
  1722. case 0x18E4:
  1723. case 0x1aE4:
  1724. Rate[0] = MGN_VHT3SS_MCS4;
  1725. Rate[1] = MGN_VHT3SS_MCS5;
  1726. Rate[2] = MGN_VHT3SS_MCS6;
  1727. Rate[3] = MGN_VHT3SS_MCS7;
  1728. for (i = 0; i < 4; ++i)
  1729. PwrByRateVal[i] = (s8)get_val(Value, i);
  1730. *RateNum = 4;
  1731. break;
  1732. case 0xCE8:
  1733. case 0xEE8:
  1734. case 0x18E8:
  1735. case 0x1aE8:
  1736. Rate[0] = MGN_VHT3SS_MCS8;
  1737. Rate[1] = MGN_VHT3SS_MCS9;
  1738. for (i = 0; i < 2; ++i)
  1739. PwrByRateVal[i] = (s8)get_val(Value, i);
  1740. *RateNum = 2;
  1741. break;
  1742. default:
  1743. RTW_PRINT("Invalid RegAddr 0x%x in %s()\n", RegAddr, __func__);
  1744. break;
  1745. };
  1746. }
  1747. void
  1748. PHY_StoreTxPowerByRateNew(
  1749. IN PADAPTER pAdapter,
  1750. IN u32 Band,
  1751. IN u32 RfPath,
  1752. IN u32 RegAddr,
  1753. IN u32 BitMask,
  1754. IN u32 Data
  1755. )
  1756. {
  1757. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
  1758. u8 i = 0, rates[4] = {0}, rateNum = 0;
  1759. s8 PwrByRateVal[4] = {0};
  1760. PHY_GetRateValuesOfTxPowerByRate(pAdapter, RegAddr, BitMask, Data, rates, PwrByRateVal, &rateNum);
  1761. if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {
  1762. RTW_PRINT("Invalid Band %d\n", Band);
  1763. return;
  1764. }
  1765. if (RfPath > RF_PATH_D) {
  1766. RTW_PRINT("Invalid RfPath %d\n", RfPath);
  1767. return;
  1768. }
  1769. for (i = 0; i < rateNum; ++i) {
  1770. u8 rate_idx = PHY_GetRateIndexOfTxPowerByRate(rates[i]);
  1771. pHalData->TxPwrByRateOffset[Band][RfPath][rate_idx] = PwrByRateVal[i];
  1772. }
  1773. }
  1774. VOID
  1775. PHY_InitTxPowerByRate(
  1776. IN PADAPTER pAdapter
  1777. )
  1778. {
  1779. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
  1780. u8 band = 0, rfPath = 0, rate = 0, i = 0, j = 0;
  1781. for (band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band)
  1782. for (rfPath = 0; rfPath < TX_PWR_BY_RATE_NUM_RF; ++rfPath)
  1783. for (rate = 0; rate < TX_PWR_BY_RATE_NUM_RATE; ++rate)
  1784. pHalData->TxPwrByRateOffset[band][rfPath][rate] = 0;
  1785. }
  1786. VOID
  1787. phy_store_tx_power_by_rate(
  1788. IN PADAPTER pAdapter,
  1789. IN u32 Band,
  1790. IN u32 RfPath,
  1791. IN u32 TxNum,
  1792. IN u32 RegAddr,
  1793. IN u32 BitMask,
  1794. IN u32 Data
  1795. )
  1796. {
  1797. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
  1798. struct dm_struct *pDM_Odm = &pHalData->odmpriv;
  1799. if (pDM_Odm->phy_reg_pg_version > 0)
  1800. PHY_StoreTxPowerByRateNew(pAdapter, Band, RfPath, RegAddr, BitMask, Data);
  1801. else
  1802. RTW_INFO("Invalid PHY_REG_PG.txt version %d\n", pDM_Odm->phy_reg_pg_version);
  1803. }
  1804. VOID
  1805. phy_ConvertTxPowerByRateInDbmToRelativeValues(
  1806. IN PADAPTER pAdapter
  1807. )
  1808. {
  1809. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
  1810. u8 base = 0, i = 0, value = 0,
  1811. band = 0, path = 0, index = 0,
  1812. startIndex = 0, endIndex = 0;
  1813. u8 cckRates[4] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M},
  1814. ofdmRates[8] = {MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M},
  1815. mcs0_7Rates[8] = {MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7},
  1816. mcs8_15Rates[8] = {MGN_MCS8, MGN_MCS9, MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14, MGN_MCS15},
  1817. mcs16_23Rates[8] = {MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19, MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23},
  1818. vht1ssRates[10] = {MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4,
  1819. MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9},
  1820. vht2ssRates[10] = {MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4,
  1821. MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9},
  1822. vht3ssRates[10] = {MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4,
  1823. MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9};
  1824. /* RTW_INFO("===>PHY_ConvertTxPowerByRateInDbmToRelativeValues()\n" ); */
  1825. for (band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band) {
  1826. for (path = RF_PATH_A; path <= RF_PATH_D; ++path) {
  1827. /* CCK */
  1828. if (band == BAND_ON_2_4G) {
  1829. base = PHY_GetTxPowerByRateBase(pAdapter, band, path, CCK);
  1830. for (i = 0; i < sizeof(cckRates); ++i) {
  1831. value = PHY_GetTxPowerByRate(pAdapter, band, path, cckRates[i]);
  1832. PHY_SetTxPowerByRate(pAdapter, band, path, cckRates[i], value - base);
  1833. }
  1834. }
  1835. /* OFDM */
  1836. base = PHY_GetTxPowerByRateBase(pAdapter, band, path, OFDM);
  1837. for (i = 0; i < sizeof(ofdmRates); ++i) {
  1838. value = PHY_GetTxPowerByRate(pAdapter, band, path, ofdmRates[i]);
  1839. PHY_SetTxPowerByRate(pAdapter, band, path, ofdmRates[i], value - base);
  1840. }
  1841. /* HT MCS0~7 */
  1842. base = PHY_GetTxPowerByRateBase(pAdapter, band, path, HT_1SS);
  1843. for (i = 0; i < sizeof(mcs0_7Rates); ++i) {
  1844. value = PHY_GetTxPowerByRate(pAdapter, band, path, mcs0_7Rates[i]);
  1845. PHY_SetTxPowerByRate(pAdapter, band, path, mcs0_7Rates[i], value - base);
  1846. }
  1847. /* HT MCS8~15 */
  1848. base = PHY_GetTxPowerByRateBase(pAdapter, band, path, HT_2SS);
  1849. for (i = 0; i < sizeof(mcs8_15Rates); ++i) {
  1850. value = PHY_GetTxPowerByRate(pAdapter, band, path, mcs8_15Rates[i]);
  1851. PHY_SetTxPowerByRate(pAdapter, band, path, mcs8_15Rates[i], value - base);
  1852. }
  1853. /* HT MCS16~23 */
  1854. base = PHY_GetTxPowerByRateBase(pAdapter, band, path, HT_3SS);
  1855. for (i = 0; i < sizeof(mcs16_23Rates); ++i) {
  1856. value = PHY_GetTxPowerByRate(pAdapter, band, path, mcs16_23Rates[i]);
  1857. PHY_SetTxPowerByRate(pAdapter, band, path, mcs16_23Rates[i], value - base);
  1858. }
  1859. /* VHT 1SS */
  1860. base = PHY_GetTxPowerByRateBase(pAdapter, band, path, VHT_1SS);
  1861. for (i = 0; i < sizeof(vht1ssRates); ++i) {
  1862. value = PHY_GetTxPowerByRate(pAdapter, band, path, vht1ssRates[i]);
  1863. PHY_SetTxPowerByRate(pAdapter, band, path, vht1ssRates[i], value - base);
  1864. }
  1865. /* VHT 2SS */
  1866. base = PHY_GetTxPowerByRateBase(pAdapter, band, path, VHT_2SS);
  1867. for (i = 0; i < sizeof(vht2ssRates); ++i) {
  1868. value = PHY_GetTxPowerByRate(pAdapter, band, path, vht2ssRates[i]);
  1869. PHY_SetTxPowerByRate(pAdapter, band, path, vht2ssRates[i], value - base);
  1870. }
  1871. /* VHT 3SS */
  1872. base = PHY_GetTxPowerByRateBase(pAdapter, band, path, VHT_3SS);
  1873. for (i = 0; i < sizeof(vht3ssRates); ++i) {
  1874. value = PHY_GetTxPowerByRate(pAdapter, band, path, vht3ssRates[i]);
  1875. PHY_SetTxPowerByRate(pAdapter, band, path, vht3ssRates[i], value - base);
  1876. }
  1877. }
  1878. }
  1879. /* RTW_INFO("<===PHY_ConvertTxPowerByRateInDbmToRelativeValues()\n" ); */
  1880. }
  1881. /*
  1882. * This function must be called if the value in the PHY_REG_PG.txt(or header)
  1883. * is exact dBm values
  1884. */
  1885. VOID
  1886. PHY_TxPowerByRateConfiguration(
  1887. IN PADAPTER pAdapter
  1888. )
  1889. {
  1890. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
  1891. phy_txpwr_by_rate_chk_for_path_dup(pAdapter);
  1892. phy_StoreTxPowerByRateBase(pAdapter);
  1893. phy_ConvertTxPowerByRateInDbmToRelativeValues(pAdapter);
  1894. }
  1895. VOID
  1896. phy_set_tx_power_index_by_rate_section(
  1897. IN PADAPTER pAdapter,
  1898. IN enum rf_path RFPath,
  1899. IN u8 Channel,
  1900. IN u8 RateSection
  1901. )
  1902. {
  1903. PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
  1904. if (RateSection >= RATE_SECTION_NUM) {
  1905. RTW_INFO("Invalid RateSection %d in %s", RateSection, __func__);
  1906. rtw_warn_on(1);
  1907. goto exit;
  1908. }
  1909. if (RateSection == CCK && pHalData->current_band_type != BAND_ON_2_4G)
  1910. goto exit;
  1911. PHY_SetTxPowerIndexByRateArray(pAdapter, RFPath, pHalData->current_channel_bw, Channel,
  1912. rates_by_sections[RateSection].rates, rates_by_sections[RateSection].rate_num);
  1913. exit:
  1914. return;
  1915. }
  1916. BOOLEAN
  1917. phy_GetChnlIndex(
  1918. IN u8 Channel,
  1919. OUT u8 *ChannelIdx
  1920. )
  1921. {
  1922. u8 i = 0;
  1923. BOOLEAN bIn24G = _TRUE;
  1924. if (Channel <= 14) {
  1925. bIn24G = _TRUE;
  1926. *ChannelIdx = Channel - 1;
  1927. } else {
  1928. bIn24G = _FALSE;
  1929. for (i = 0; i < CENTER_CH_5G_ALL_NUM; ++i) {
  1930. if (center_ch_5g_all[i] == Channel) {
  1931. *ChannelIdx = i;
  1932. return bIn24G;
  1933. }
  1934. }
  1935. }
  1936. return bIn24G;
  1937. }
  1938. u8
  1939. PHY_GetTxPowerIndexBase(
  1940. IN PADAPTER pAdapter,
  1941. IN enum rf_path RFPath,
  1942. IN u8 Rate,
  1943. u8 ntx_idx,
  1944. IN enum channel_width BandWidth,
  1945. IN u8 Channel,
  1946. OUT PBOOLEAN bIn24G
  1947. )
  1948. {
  1949. PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
  1950. struct dm_struct *pDM_Odm = &pHalData->odmpriv;
  1951. u8 i = 0; /* default set to 1S */
  1952. u8 txPower = 0;
  1953. u8 chnlIdx = (Channel - 1);
  1954. if (HAL_IsLegalChannel(pAdapter, Channel) == _FALSE) {
  1955. chnlIdx = 0;
  1956. RTW_INFO("Illegal channel!!\n");
  1957. }
  1958. *bIn24G = phy_GetChnlIndex(Channel, &chnlIdx);
  1959. if (0)
  1960. RTW_INFO("[%s] Channel Index: %d\n", (*bIn24G ? "2.4G" : "5G"), chnlIdx);
  1961. if (*bIn24G) {
  1962. if (IS_CCK_RATE(Rate)) {
  1963. /* CCK-nTX */
  1964. txPower = pHalData->Index24G_CCK_Base[RFPath][chnlIdx];
  1965. txPower += pHalData->CCK_24G_Diff[RFPath][RF_1TX];
  1966. if (ntx_idx >= RF_2TX)
  1967. txPower += pHalData->CCK_24G_Diff[RFPath][RF_2TX];
  1968. if (ntx_idx >= RF_3TX)
  1969. txPower += pHalData->CCK_24G_Diff[RFPath][RF_3TX];
  1970. if (ntx_idx >= RF_4TX)
  1971. txPower += pHalData->CCK_24G_Diff[RFPath][RF_4TX];
  1972. goto exit;
  1973. }
  1974. txPower = pHalData->Index24G_BW40_Base[RFPath][chnlIdx];
  1975. /* OFDM-nTX */
  1976. if ((MGN_6M <= Rate && Rate <= MGN_54M) && !IS_CCK_RATE(Rate)) {
  1977. txPower += pHalData->OFDM_24G_Diff[RFPath][RF_1TX];
  1978. if (ntx_idx >= RF_2TX)
  1979. txPower += pHalData->OFDM_24G_Diff[RFPath][RF_2TX];
  1980. if (ntx_idx >= RF_3TX)
  1981. txPower += pHalData->OFDM_24G_Diff[RFPath][RF_3TX];
  1982. if (ntx_idx >= RF_4TX)
  1983. txPower += pHalData->OFDM_24G_Diff[RFPath][RF_4TX];
  1984. goto exit;
  1985. }
  1986. /* BW20-nS */
  1987. if (BandWidth == CHANNEL_WIDTH_20) {
  1988. if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
  1989. txPower += pHalData->BW20_24G_Diff[RFPath][RF_1TX];
  1990. if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
  1991. txPower += pHalData->BW20_24G_Diff[RFPath][RF_2TX];
  1992. if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
  1993. txPower += pHalData->BW20_24G_Diff[RFPath][RF_3TX];
  1994. if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
  1995. txPower += pHalData->BW20_24G_Diff[RFPath][RF_4TX];
  1996. goto exit;
  1997. }
  1998. /* BW40-nS */
  1999. if (BandWidth == CHANNEL_WIDTH_40) {
  2000. if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
  2001. txPower += pHalData->BW40_24G_Diff[RFPath][RF_1TX];
  2002. if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
  2003. txPower += pHalData->BW40_24G_Diff[RFPath][RF_2TX];
  2004. if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
  2005. txPower += pHalData->BW40_24G_Diff[RFPath][RF_3TX];
  2006. if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
  2007. txPower += pHalData->BW40_24G_Diff[RFPath][RF_4TX];
  2008. goto exit;
  2009. }
  2010. /* Willis suggest adopt BW 40M power index while in BW 80 mode */
  2011. if (BandWidth == CHANNEL_WIDTH_80) {
  2012. if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
  2013. txPower += pHalData->BW40_24G_Diff[RFPath][RF_1TX];
  2014. if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
  2015. txPower += pHalData->BW40_24G_Diff[RFPath][RF_2TX];
  2016. if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
  2017. txPower += pHalData->BW40_24G_Diff[RFPath][RF_3TX];
  2018. if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
  2019. txPower += pHalData->BW40_24G_Diff[RFPath][RF_4TX];
  2020. goto exit;
  2021. }
  2022. }
  2023. #ifdef CONFIG_IEEE80211_BAND_5GHZ
  2024. else {
  2025. if (Rate >= MGN_6M)
  2026. txPower = pHalData->Index5G_BW40_Base[RFPath][chnlIdx];
  2027. else {
  2028. RTW_INFO("===>PHY_GetTxPowerIndexBase: INVALID Rate(0x%02x).\n", Rate);
  2029. goto exit;
  2030. }
  2031. /* OFDM-nTX */
  2032. if ((MGN_6M <= Rate && Rate <= MGN_54M) && !IS_CCK_RATE(Rate)) {
  2033. txPower += pHalData->OFDM_5G_Diff[RFPath][RF_1TX];
  2034. if (ntx_idx >= RF_2TX)
  2035. txPower += pHalData->OFDM_5G_Diff[RFPath][RF_2TX];
  2036. if (ntx_idx >= RF_3TX)
  2037. txPower += pHalData->OFDM_5G_Diff[RFPath][RF_3TX];
  2038. if (ntx_idx >= RF_4TX)
  2039. txPower += pHalData->OFDM_5G_Diff[RFPath][RF_4TX];
  2040. goto exit;
  2041. }
  2042. /* BW20-nS */
  2043. if (BandWidth == CHANNEL_WIDTH_20) {
  2044. if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
  2045. txPower += pHalData->BW20_5G_Diff[RFPath][RF_1TX];
  2046. if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
  2047. txPower += pHalData->BW20_5G_Diff[RFPath][RF_2TX];
  2048. if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
  2049. txPower += pHalData->BW20_5G_Diff[RFPath][RF_3TX];
  2050. if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
  2051. txPower += pHalData->BW20_5G_Diff[RFPath][RF_4TX];
  2052. goto exit;
  2053. }
  2054. /* BW40-nS */
  2055. if (BandWidth == CHANNEL_WIDTH_40) {
  2056. if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
  2057. txPower += pHalData->BW40_5G_Diff[RFPath][RF_1TX];
  2058. if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
  2059. txPower += pHalData->BW40_5G_Diff[RFPath][RF_2TX];
  2060. if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
  2061. txPower += pHalData->BW40_5G_Diff[RFPath][RF_3TX];
  2062. if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
  2063. txPower += pHalData->BW40_5G_Diff[RFPath][RF_4TX];
  2064. goto exit;
  2065. }
  2066. /* BW80-nS */
  2067. if (BandWidth == CHANNEL_WIDTH_80) {
  2068. /* get 80MHz cch index */
  2069. for (i = 0; i < CENTER_CH_5G_80M_NUM; ++i) {
  2070. if (center_ch_5g_80m[i] == Channel) {
  2071. chnlIdx = i;
  2072. break;
  2073. }
  2074. }
  2075. if (i >= CENTER_CH_5G_80M_NUM) {
  2076. #ifdef CONFIG_MP_INCLUDED
  2077. if (rtw_mp_mode_check(pAdapter) == _FALSE)
  2078. #endif
  2079. rtw_warn_on(1);
  2080. txPower = 0;
  2081. goto exit;
  2082. }
  2083. txPower = pHalData->Index5G_BW80_Base[RFPath][chnlIdx];
  2084. if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
  2085. txPower += + pHalData->BW80_5G_Diff[RFPath][RF_1TX];
  2086. if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
  2087. txPower += pHalData->BW80_5G_Diff[RFPath][RF_2TX];
  2088. if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
  2089. txPower += pHalData->BW80_5G_Diff[RFPath][RF_3TX];
  2090. if ((MGN_MCS23 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
  2091. txPower += pHalData->BW80_5G_Diff[RFPath][RF_4TX];
  2092. goto exit;
  2093. }
  2094. /* TODO: BW160-nS */
  2095. rtw_warn_on(1);
  2096. }
  2097. #endif /* CONFIG_IEEE80211_BAND_5GHZ */
  2098. exit:
  2099. return txPower;
  2100. }
  2101. s8
  2102. PHY_GetTxPowerTrackingOffset(
  2103. PADAPTER pAdapter,
  2104. enum rf_path RFPath,
  2105. u8 Rate
  2106. )
  2107. {
  2108. PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
  2109. struct dm_struct *pDM_Odm = &pHalData->odmpriv;
  2110. s8 offset = 0;
  2111. if (pDM_Odm->rf_calibrate_info.txpowertrack_control == _FALSE)
  2112. return offset;
  2113. if ((Rate == MGN_1M) || (Rate == MGN_2M) || (Rate == MGN_5_5M) || (Rate == MGN_11M)) {
  2114. offset = pDM_Odm->rf_calibrate_info.remnant_cck_swing_idx;
  2115. /*RTW_INFO("+Remnant_CCKSwingIdx = 0x%x\n", RFPath, Rate, pRFCalibrateInfo->Remnant_CCKSwingIdx);*/
  2116. } else {
  2117. offset = pDM_Odm->rf_calibrate_info.remnant_ofdm_swing_idx[RFPath];
  2118. /*RTW_INFO("+Remanant_OFDMSwingIdx[RFPath %u][Rate 0x%x] = 0x%x\n", RFPath, Rate, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath]); */
  2119. }
  2120. return offset;
  2121. }
  2122. /*The same as MRateToHwRate in hal_com.c*/
  2123. u8
  2124. PHY_GetRateIndexOfTxPowerByRate(
  2125. IN u8 Rate
  2126. )
  2127. {
  2128. u8 index = 0;
  2129. switch (Rate) {
  2130. case MGN_1M:
  2131. index = 0;
  2132. break;
  2133. case MGN_2M:
  2134. index = 1;
  2135. break;
  2136. case MGN_5_5M:
  2137. index = 2;
  2138. break;
  2139. case MGN_11M:
  2140. index = 3;
  2141. break;
  2142. case MGN_6M:
  2143. index = 4;
  2144. break;
  2145. case MGN_9M:
  2146. index = 5;
  2147. break;
  2148. case MGN_12M:
  2149. index = 6;
  2150. break;
  2151. case MGN_18M:
  2152. index = 7;
  2153. break;
  2154. case MGN_24M:
  2155. index = 8;
  2156. break;
  2157. case MGN_36M:
  2158. index = 9;
  2159. break;
  2160. case MGN_48M:
  2161. index = 10;
  2162. break;
  2163. case MGN_54M:
  2164. index = 11;
  2165. break;
  2166. case MGN_MCS0:
  2167. index = 12;
  2168. break;
  2169. case MGN_MCS1:
  2170. index = 13;
  2171. break;
  2172. case MGN_MCS2:
  2173. index = 14;
  2174. break;
  2175. case MGN_MCS3:
  2176. index = 15;
  2177. break;
  2178. case MGN_MCS4:
  2179. index = 16;
  2180. break;
  2181. case MGN_MCS5:
  2182. index = 17;
  2183. break;
  2184. case MGN_MCS6:
  2185. index = 18;
  2186. break;
  2187. case MGN_MCS7:
  2188. index = 19;
  2189. break;
  2190. case MGN_MCS8:
  2191. index = 20;
  2192. break;
  2193. case MGN_MCS9:
  2194. index = 21;
  2195. break;
  2196. case MGN_MCS10:
  2197. index = 22;
  2198. break;
  2199. case MGN_MCS11:
  2200. index = 23;
  2201. break;
  2202. case MGN_MCS12:
  2203. index = 24;
  2204. break;
  2205. case MGN_MCS13:
  2206. index = 25;
  2207. break;
  2208. case MGN_MCS14:
  2209. index = 26;
  2210. break;
  2211. case MGN_MCS15:
  2212. index = 27;
  2213. break;
  2214. case MGN_MCS16:
  2215. index = 28;
  2216. break;
  2217. case MGN_MCS17:
  2218. index = 29;
  2219. break;
  2220. case MGN_MCS18:
  2221. index = 30;
  2222. break;
  2223. case MGN_MCS19:
  2224. index = 31;
  2225. break;
  2226. case MGN_MCS20:
  2227. index = 32;
  2228. break;
  2229. case MGN_MCS21:
  2230. index = 33;
  2231. break;
  2232. case MGN_MCS22:
  2233. index = 34;
  2234. break;
  2235. case MGN_MCS23:
  2236. index = 35;
  2237. break;
  2238. case MGN_MCS24:
  2239. index = 36;
  2240. break;
  2241. case MGN_MCS25:
  2242. index = 37;
  2243. break;
  2244. case MGN_MCS26:
  2245. index = 38;
  2246. break;
  2247. case MGN_MCS27:
  2248. index = 39;
  2249. break;
  2250. case MGN_MCS28:
  2251. index = 40;
  2252. break;
  2253. case MGN_MCS29:
  2254. index = 41;
  2255. break;
  2256. case MGN_MCS30:
  2257. index = 42;
  2258. break;
  2259. case MGN_MCS31:
  2260. index = 43;
  2261. break;
  2262. case MGN_VHT1SS_MCS0:
  2263. index = 44;
  2264. break;
  2265. case MGN_VHT1SS_MCS1:
  2266. index = 45;
  2267. break;
  2268. case MGN_VHT1SS_MCS2:
  2269. index = 46;
  2270. break;
  2271. case MGN_VHT1SS_MCS3:
  2272. index = 47;
  2273. break;
  2274. case MGN_VHT1SS_MCS4:
  2275. index = 48;
  2276. break;
  2277. case MGN_VHT1SS_MCS5:
  2278. index = 49;
  2279. break;
  2280. case MGN_VHT1SS_MCS6:
  2281. index = 50;
  2282. break;
  2283. case MGN_VHT1SS_MCS7:
  2284. index = 51;
  2285. break;
  2286. case MGN_VHT1SS_MCS8:
  2287. index = 52;
  2288. break;
  2289. case MGN_VHT1SS_MCS9:
  2290. index = 53;
  2291. break;
  2292. case MGN_VHT2SS_MCS0:
  2293. index = 54;
  2294. break;
  2295. case MGN_VHT2SS_MCS1:
  2296. index = 55;
  2297. break;
  2298. case MGN_VHT2SS_MCS2:
  2299. index = 56;
  2300. break;
  2301. case MGN_VHT2SS_MCS3:
  2302. index = 57;
  2303. break;
  2304. case MGN_VHT2SS_MCS4:
  2305. index = 58;
  2306. break;
  2307. case MGN_VHT2SS_MCS5:
  2308. index = 59;
  2309. break;
  2310. case MGN_VHT2SS_MCS6:
  2311. index = 60;
  2312. break;
  2313. case MGN_VHT2SS_MCS7:
  2314. index = 61;
  2315. break;
  2316. case MGN_VHT2SS_MCS8:
  2317. index = 62;
  2318. break;
  2319. case MGN_VHT2SS_MCS9:
  2320. index = 63;
  2321. break;
  2322. case MGN_VHT3SS_MCS0:
  2323. index = 64;
  2324. break;
  2325. case MGN_VHT3SS_MCS1:
  2326. index = 65;
  2327. break;
  2328. case MGN_VHT3SS_MCS2:
  2329. index = 66;
  2330. break;
  2331. case MGN_VHT3SS_MCS3:
  2332. index = 67;
  2333. break;
  2334. case MGN_VHT3SS_MCS4:
  2335. index = 68;
  2336. break;
  2337. case MGN_VHT3SS_MCS5:
  2338. index = 69;
  2339. break;
  2340. case MGN_VHT3SS_MCS6:
  2341. index = 70;
  2342. break;
  2343. case MGN_VHT3SS_MCS7:
  2344. index = 71;
  2345. break;
  2346. case MGN_VHT3SS_MCS8:
  2347. index = 72;
  2348. break;
  2349. case MGN_VHT3SS_MCS9:
  2350. index = 73;
  2351. break;
  2352. case MGN_VHT4SS_MCS0:
  2353. index = 74;
  2354. break;
  2355. case MGN_VHT4SS_MCS1:
  2356. index = 75;
  2357. break;
  2358. case MGN_VHT4SS_MCS2:
  2359. index = 76;
  2360. break;
  2361. case MGN_VHT4SS_MCS3:
  2362. index = 77;
  2363. break;
  2364. case MGN_VHT4SS_MCS4:
  2365. index = 78;
  2366. break;
  2367. case MGN_VHT4SS_MCS5:
  2368. index = 79;
  2369. break;
  2370. case MGN_VHT4SS_MCS6:
  2371. index = 80;
  2372. break;
  2373. case MGN_VHT4SS_MCS7:
  2374. index = 81;
  2375. break;
  2376. case MGN_VHT4SS_MCS8:
  2377. index = 82;
  2378. break;
  2379. case MGN_VHT4SS_MCS9:
  2380. index = 83;
  2381. break;
  2382. default:
  2383. RTW_INFO("Invalid rate 0x%x in %s\n", Rate, __FUNCTION__);
  2384. break;
  2385. };
  2386. return index;
  2387. }
  2388. s8
  2389. _PHY_GetTxPowerByRate(
  2390. IN PADAPTER pAdapter,
  2391. IN u8 Band,
  2392. IN enum rf_path RFPath,
  2393. IN u8 Rate
  2394. )
  2395. {
  2396. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
  2397. s8 value = 0;
  2398. u8 rateIndex = PHY_GetRateIndexOfTxPowerByRate(Rate);
  2399. if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {
  2400. RTW_INFO("Invalid band %d in %s\n", Band, __func__);
  2401. goto exit;
  2402. }
  2403. if (RFPath > RF_PATH_D) {
  2404. RTW_INFO("Invalid RfPath %d in %s\n", RFPath, __func__);
  2405. goto exit;
  2406. }
  2407. if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE) {
  2408. RTW_INFO("Invalid RateIndex %d in %s\n", rateIndex, __func__);
  2409. goto exit;
  2410. }
  2411. value = pHalData->TxPwrByRateOffset[Band][RFPath][rateIndex];
  2412. exit:
  2413. return value;
  2414. }
  2415. s8
  2416. PHY_GetTxPowerByRate(
  2417. IN PADAPTER pAdapter,
  2418. IN u8 Band,
  2419. IN enum rf_path RFPath,
  2420. IN u8 Rate
  2421. )
  2422. {
  2423. if (!phy_is_tx_power_by_rate_needed(pAdapter))
  2424. return 0;
  2425. return _PHY_GetTxPowerByRate(pAdapter, Band, RFPath, Rate);
  2426. }
  2427. VOID
  2428. PHY_SetTxPowerByRate(
  2429. IN PADAPTER pAdapter,
  2430. IN u8 Band,
  2431. IN enum rf_path RFPath,
  2432. IN u8 Rate,
  2433. IN s8 Value
  2434. )
  2435. {
  2436. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
  2437. u8 rateIndex = PHY_GetRateIndexOfTxPowerByRate(Rate);
  2438. if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {
  2439. RTW_INFO("Invalid band %d in %s\n", Band, __FUNCTION__);
  2440. return;
  2441. }
  2442. if (RFPath > RF_PATH_D) {
  2443. RTW_INFO("Invalid RfPath %d in %s\n", RFPath, __FUNCTION__);
  2444. return;
  2445. }
  2446. if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE) {
  2447. RTW_INFO("Invalid RateIndex %d in %s\n", rateIndex, __FUNCTION__);
  2448. return;
  2449. }
  2450. pHalData->TxPwrByRateOffset[Band][RFPath][rateIndex] = Value;
  2451. }
  2452. u8 phy_check_under_survey_ch(_adapter *adapter)
  2453. {
  2454. struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
  2455. _adapter *iface;
  2456. struct mlme_ext_priv *mlmeext;
  2457. u8 ret = _FALSE;
  2458. int i;
  2459. for (i = 0; i < dvobj->iface_nums; i++) {
  2460. iface = dvobj->padapters[i];
  2461. if (!iface)
  2462. continue;
  2463. mlmeext = &iface->mlmeextpriv;
  2464. /* check scan state */
  2465. if (mlmeext_scan_state(mlmeext) != SCAN_DISABLE
  2466. && mlmeext_scan_state(mlmeext) != SCAN_COMPLETE
  2467. && mlmeext_scan_state(mlmeext) != SCAN_BACKING_OP) {
  2468. ret = _TRUE;
  2469. } else if (mlmeext_scan_state(mlmeext) == SCAN_BACKING_OP
  2470. && !mlmeext_chk_scan_backop_flags(mlmeext, SS_BACKOP_TX_RESUME)) {
  2471. ret = _TRUE;
  2472. }
  2473. }
  2474. return ret;
  2475. }
  2476. VOID
  2477. phy_set_tx_power_level_by_path(
  2478. IN PADAPTER Adapter,
  2479. IN u8 channel,
  2480. IN u8 path
  2481. )
  2482. {
  2483. PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
  2484. BOOLEAN bIsIn24G = (pHalData->current_band_type == BAND_ON_2_4G);
  2485. u8 under_survey_ch = phy_check_under_survey_ch(Adapter);
  2486. /* if ( pMgntInfo->RegNByteAccess == 0 ) */
  2487. {
  2488. if (bIsIn24G)
  2489. phy_set_tx_power_index_by_rate_section(Adapter, path, channel, CCK);
  2490. phy_set_tx_power_index_by_rate_section(Adapter, path, channel, OFDM);
  2491. if (!under_survey_ch) {
  2492. phy_set_tx_power_index_by_rate_section(Adapter, path, channel, HT_MCS0_MCS7);
  2493. if (IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter))
  2494. phy_set_tx_power_index_by_rate_section(Adapter, path, channel, VHT_1SSMCS0_1SSMCS9);
  2495. if (pHalData->NumTotalRFPath >= 2) {
  2496. phy_set_tx_power_index_by_rate_section(Adapter, path, channel, HT_MCS8_MCS15);
  2497. if (IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter))
  2498. phy_set_tx_power_index_by_rate_section(Adapter, path, channel, VHT_2SSMCS0_2SSMCS9);
  2499. if (IS_HARDWARE_TYPE_8814A(Adapter)) {
  2500. phy_set_tx_power_index_by_rate_section(Adapter, path, channel, HT_MCS16_MCS23);
  2501. phy_set_tx_power_index_by_rate_section(Adapter, path, channel, VHT_3SSMCS0_3SSMCS9);
  2502. }
  2503. }
  2504. }
  2505. }
  2506. }
  2507. #ifndef DBG_TX_POWER_IDX
  2508. #define DBG_TX_POWER_IDX 0
  2509. #endif
  2510. VOID
  2511. PHY_SetTxPowerIndexByRateArray(
  2512. IN PADAPTER pAdapter,
  2513. IN enum rf_path RFPath,
  2514. IN enum channel_width BandWidth,
  2515. IN u8 Channel,
  2516. IN u8 *Rates,
  2517. IN u8 RateArraySize
  2518. )
  2519. {
  2520. u32 powerIndex = 0;
  2521. int i = 0;
  2522. for (i = 0; i < RateArraySize; ++i) {
  2523. #if DBG_TX_POWER_IDX
  2524. struct txpwr_idx_comp tic;
  2525. powerIndex = rtw_hal_get_tx_power_index(pAdapter, RFPath, Rates[i], BandWidth, Channel, &tic);
  2526. RTW_INFO("TXPWR: [%c][%s]ch:%u, %s %uT, pwr_idx:%u = %u + (%d=%d:%d) + (%d) + (%d)\n"
  2527. , rf_path_char(RFPath), ch_width_str(BandWidth), Channel, MGN_RATE_STR(Rates[i]), tic.ntx_idx + 1
  2528. , powerIndex, tic.base, (tic.by_rate > tic.limit ? tic.limit : tic.by_rate), tic.by_rate, tic.limit, tic.tpt, tic.ebias);
  2529. #else
  2530. powerIndex = phy_get_tx_power_index(pAdapter, RFPath, Rates[i], BandWidth, Channel);
  2531. #endif
  2532. PHY_SetTxPowerIndex(pAdapter, powerIndex, RFPath, Rates[i]);
  2533. }
  2534. }
  2535. #ifdef CONFIG_TXPWR_LIMIT
  2536. const char *const _txpwr_lmt_rs_str[] = {
  2537. "CCK",
  2538. "OFDM",
  2539. "HT",
  2540. "VHT",
  2541. "UNKNOWN",
  2542. };
  2543. static s8
  2544. phy_GetChannelIndexOfTxPowerLimit(
  2545. IN u8 Band,
  2546. IN u8 Channel
  2547. )
  2548. {
  2549. s8 channelIndex = -1;
  2550. u8 i = 0;
  2551. if (Band == BAND_ON_2_4G)
  2552. channelIndex = Channel - 1;
  2553. else if (Band == BAND_ON_5G) {
  2554. for (i = 0; i < CENTER_CH_5G_ALL_NUM; ++i) {
  2555. if (center_ch_5g_all[i] == Channel)
  2556. channelIndex = i;
  2557. }
  2558. } else
  2559. RTW_PRINT("Invalid Band %d in %s\n", Band, __func__);
  2560. if (channelIndex == -1)
  2561. RTW_PRINT("Invalid Channel %d of Band %d in %s\n", Channel, Band, __func__);
  2562. return channelIndex;
  2563. }
  2564. static s8 phy_txpwr_ww_lmt_value(_adapter *adapter)
  2565. {
  2566. struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
  2567. if (hal_spec->txgi_max == 63)
  2568. return -63;
  2569. else if (hal_spec->txgi_max == 127)
  2570. return -128;
  2571. rtw_warn_on(1);
  2572. return -128;
  2573. }
  2574. /*
  2575. * return txpwr limit absolute value
  2576. * hsl_spec->txgi_max is returned when NO limit
  2577. */
  2578. s8 phy_get_txpwr_lmt_abs(
  2579. IN PADAPTER Adapter,
  2580. IN const char *regd_name,
  2581. IN BAND_TYPE Band,
  2582. IN enum channel_width bw,
  2583. u8 tlrs,
  2584. u8 ntx_idx,
  2585. u8 cch,
  2586. u8 lock
  2587. )
  2588. {
  2589. struct dvobj_priv *dvobj = adapter_to_dvobj(Adapter);
  2590. struct rf_ctl_t *rfctl = adapter_to_rfctl(Adapter);
  2591. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(Adapter);
  2592. struct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter);
  2593. struct txpwr_lmt_ent *ent = NULL;
  2594. _irqL irqL;
  2595. _list *cur, *head;
  2596. s8 ch_idx;
  2597. u8 is_ww_regd = 0;
  2598. s8 ww_lmt_val = phy_txpwr_ww_lmt_value(Adapter);
  2599. s8 lmt = hal_spec->txgi_max;
  2600. if ((Adapter->registrypriv.RegEnableTxPowerLimit == 2 && hal_data->EEPROMRegulatory != 1) ||
  2601. Adapter->registrypriv.RegEnableTxPowerLimit == 0)
  2602. goto exit;
  2603. if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {
  2604. RTW_ERR("%s invalid band:%u\n", __func__, Band);
  2605. rtw_warn_on(1);
  2606. goto exit;
  2607. }
  2608. if (Band == BAND_ON_5G && tlrs == TXPWR_LMT_RS_CCK) {
  2609. RTW_ERR("5G has no CCK\n");
  2610. goto exit;
  2611. }
  2612. if (lock)
  2613. _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
  2614. if (!regd_name) /* no regd_name specified, use currnet */
  2615. regd_name = rfctl->regd_name;
  2616. if (rfctl->txpwr_regd_num == 0
  2617. || strcmp(regd_name, regd_str(TXPWR_LMT_NONE)) == 0)
  2618. goto release_lock;
  2619. if (strcmp(regd_name, regd_str(TXPWR_LMT_WW)) == 0)
  2620. is_ww_regd = 1;
  2621. if (!is_ww_regd) {
  2622. ent = _rtw_txpwr_lmt_get_by_name(rfctl, regd_name);
  2623. if (!ent)
  2624. goto release_lock;
  2625. }
  2626. ch_idx = phy_GetChannelIndexOfTxPowerLimit(Band, cch);
  2627. if (ch_idx == -1)
  2628. goto release_lock;
  2629. if (Band == BAND_ON_2_4G) {
  2630. if (!is_ww_regd) {
  2631. lmt = ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx];
  2632. if (lmt != ww_lmt_val)
  2633. goto release_lock;
  2634. }
  2635. /* search for min value for WW regd or WW limit */
  2636. lmt = hal_spec->txgi_max;
  2637. head = &rfctl->txpwr_lmt_list;
  2638. cur = get_next(head);
  2639. while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
  2640. ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
  2641. cur = get_next(cur);
  2642. if (ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx] != ww_lmt_val)
  2643. lmt = rtw_min(lmt, ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx]);
  2644. }
  2645. }
  2646. #ifdef CONFIG_IEEE80211_BAND_5GHZ
  2647. else if (Band == BAND_ON_5G) {
  2648. if (!is_ww_regd) {
  2649. lmt = ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx];
  2650. if (lmt != ww_lmt_val)
  2651. goto release_lock;
  2652. }
  2653. /* search for min value for WW regd or WW limit */
  2654. lmt = hal_spec->txgi_max;
  2655. head = &rfctl->txpwr_lmt_list;
  2656. cur = get_next(head);
  2657. while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
  2658. ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
  2659. cur = get_next(cur);
  2660. if (ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx] != ww_lmt_val)
  2661. lmt = rtw_min(lmt, ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx]);
  2662. }
  2663. }
  2664. #endif
  2665. release_lock:
  2666. if (lock)
  2667. _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
  2668. exit:
  2669. return lmt;
  2670. }
  2671. /*
  2672. * return txpwr limit diff value
  2673. * hal_spec->txgi_max is returned when NO limit
  2674. */
  2675. inline s8 phy_get_txpwr_lmt(_adapter *adapter
  2676. , const char *regd_name
  2677. , BAND_TYPE band, enum channel_width bw
  2678. , u8 rfpath, u8 rs, u8 ntx_idx, u8 cch, u8 lock
  2679. )
  2680. {
  2681. struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
  2682. u8 tlrs;
  2683. s8 lmt = hal_spec->txgi_max;
  2684. if (IS_CCK_RATE_SECTION(rs))
  2685. tlrs = TXPWR_LMT_RS_CCK;
  2686. else if (IS_OFDM_RATE_SECTION(rs))
  2687. tlrs = TXPWR_LMT_RS_OFDM;
  2688. else if (IS_HT_RATE_SECTION(rs))
  2689. tlrs = TXPWR_LMT_RS_HT;
  2690. else if (IS_VHT_RATE_SECTION(rs))
  2691. tlrs = TXPWR_LMT_RS_VHT;
  2692. else {
  2693. RTW_ERR("%s invalid rs %u\n", __func__, rs);
  2694. rtw_warn_on(1);
  2695. goto exit;
  2696. }
  2697. lmt = phy_get_txpwr_lmt_abs(adapter, regd_name, band, bw, tlrs, ntx_idx, cch, lock);
  2698. if (lmt != hal_spec->txgi_max) {
  2699. /* return diff value */
  2700. lmt = lmt - PHY_GetTxPowerByRateBase(adapter, band, rfpath, rs);
  2701. }
  2702. exit:
  2703. return lmt;
  2704. }
  2705. /*
  2706. * May search for secondary channels for min limit
  2707. * return txpwr limit diff value
  2708. */
  2709. s8
  2710. PHY_GetTxPowerLimit(_adapter *adapter
  2711. , const char *regd_name
  2712. , BAND_TYPE band, enum channel_width bw
  2713. , u8 rfpath, u8 rate, u8 ntx_idx, u8 cch)
  2714. {
  2715. struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
  2716. struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
  2717. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
  2718. struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
  2719. BOOLEAN no_sc = _FALSE;
  2720. s8 tlrs = -1, rs = -1;
  2721. s8 lmt = hal_spec->txgi_max;
  2722. u8 tmp_cch = 0;
  2723. u8 tmp_bw;
  2724. u8 bw_bmp = 0;
  2725. s8 min_lmt = hal_spec->txgi_max;
  2726. u8 final_bw = bw, final_cch = cch;
  2727. _irqL irqL;
  2728. #ifdef CONFIG_MP_INCLUDED
  2729. /* MP mode channel don't use secondary channel */
  2730. if (rtw_mp_mode_check(adapter) == _TRUE)
  2731. no_sc = _TRUE;
  2732. #endif
  2733. if (IS_CCK_RATE(rate)) {
  2734. tlrs = TXPWR_LMT_RS_CCK;
  2735. rs = CCK;
  2736. } else if (IS_OFDM_RATE(rate)) {
  2737. tlrs = TXPWR_LMT_RS_OFDM;
  2738. rs = OFDM;
  2739. } else if (IS_HT_RATE(rate)) {
  2740. tlrs = TXPWR_LMT_RS_HT;
  2741. rs = HT_1SS + (IS_HT1SS_RATE(rate) ? 0 : IS_HT2SS_RATE(rate) ? 1 : IS_HT3SS_RATE(rate) ? 2 : IS_HT4SS_RATE(rate) ? 3 : 0);
  2742. } else if (IS_VHT_RATE(rate)) {
  2743. tlrs = TXPWR_LMT_RS_VHT;
  2744. rs = VHT_1SS + (IS_VHT1SS_RATE(rate) ? 0 : IS_VHT2SS_RATE(rate) ? 1 : IS_VHT3SS_RATE(rate) ? 2 : IS_VHT4SS_RATE(rate) ? 3 : 0);
  2745. } else {
  2746. RTW_ERR("%s invalid rate 0x%x\n", __func__, rate);
  2747. rtw_warn_on(1);
  2748. goto exit;
  2749. }
  2750. if (no_sc == _TRUE) {
  2751. /* use the input center channel and bandwidth directly */
  2752. tmp_cch = cch;
  2753. bw_bmp = ch_width_to_bw_cap(bw);
  2754. } else {
  2755. /*
  2756. * find the possible tx bandwidth bmp for this rate, and then will get center channel for each bandwidth
  2757. * if no possible tx bandwidth bmp, select valid bandwidth up to current RF bandwidth into bmp
  2758. */
  2759. if (tlrs == TXPWR_LMT_RS_CCK || tlrs == TXPWR_LMT_RS_OFDM)
  2760. bw_bmp = BW_CAP_20M; /* CCK, OFDM only BW 20M */
  2761. else if (tlrs == TXPWR_LMT_RS_HT) {
  2762. bw_bmp = rtw_get_tx_bw_bmp_of_ht_rate(dvobj, rate, bw);
  2763. if (bw_bmp == 0)
  2764. bw_bmp = ch_width_to_bw_cap(bw > CHANNEL_WIDTH_40 ? CHANNEL_WIDTH_40 : bw);
  2765. } else if (tlrs == TXPWR_LMT_RS_VHT) {
  2766. bw_bmp = rtw_get_tx_bw_bmp_of_vht_rate(dvobj, rate, bw);
  2767. if (bw_bmp == 0)
  2768. bw_bmp = ch_width_to_bw_cap(bw > CHANNEL_WIDTH_160 ? CHANNEL_WIDTH_160 : bw);
  2769. } else
  2770. rtw_warn_on(1);
  2771. }
  2772. if (bw_bmp == 0)
  2773. goto exit;
  2774. _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
  2775. /* loop for each possible tx bandwidth to find minimum limit */
  2776. for (tmp_bw = CHANNEL_WIDTH_20; tmp_bw <= bw; tmp_bw++) {
  2777. if (!(ch_width_to_bw_cap(tmp_bw) & bw_bmp))
  2778. continue;
  2779. if (no_sc == _FALSE) {
  2780. if (tmp_bw == CHANNEL_WIDTH_20)
  2781. tmp_cch = hal_data->cch_20;
  2782. else if (tmp_bw == CHANNEL_WIDTH_40)
  2783. tmp_cch = hal_data->cch_40;
  2784. else if (tmp_bw == CHANNEL_WIDTH_80)
  2785. tmp_cch = hal_data->cch_80;
  2786. else {
  2787. tmp_cch = 0;
  2788. rtw_warn_on(1);
  2789. }
  2790. }
  2791. lmt = phy_get_txpwr_lmt_abs(adapter, regd_name, band, tmp_bw, tlrs, ntx_idx, tmp_cch, 0);
  2792. if (min_lmt >= lmt) {
  2793. min_lmt = lmt;
  2794. final_cch = tmp_cch;
  2795. final_bw = tmp_bw;
  2796. }
  2797. }
  2798. _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
  2799. if (min_lmt != hal_spec->txgi_max) {
  2800. /* return diff value */
  2801. min_lmt = min_lmt - PHY_GetTxPowerByRateBase(adapter, band, rfpath, rs);
  2802. }
  2803. exit:
  2804. if (0) {
  2805. if (final_bw != bw && (IS_HT_RATE(rate) || IS_VHT_RATE(rate)))
  2806. RTW_INFO("%s min_lmt: %s ch%u -> %s ch%u\n"
  2807. , MGN_RATE_STR(rate)
  2808. , ch_width_str(bw), cch
  2809. , ch_width_str(final_bw), final_cch);
  2810. }
  2811. return min_lmt;
  2812. }
  2813. static void phy_txpwr_lmt_cck_ofdm_mt_chk(_adapter *adapter)
  2814. {
  2815. struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
  2816. struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
  2817. struct txpwr_lmt_ent *ent;
  2818. _list *cur, *head;
  2819. u8 channel, tlrs, ntx_idx;
  2820. rfctl->txpwr_lmt_2g_cck_ofdm_state = 0;
  2821. #ifdef CONFIG_IEEE80211_BAND_5GHZ
  2822. rfctl->txpwr_lmt_5g_cck_ofdm_state = 0;
  2823. #endif
  2824. head = &rfctl->txpwr_lmt_list;
  2825. cur = get_next(head);
  2826. while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
  2827. ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
  2828. cur = get_next(cur);
  2829. /* check 2G CCK, OFDM state*/
  2830. for (tlrs = TXPWR_LMT_RS_CCK; tlrs <= TXPWR_LMT_RS_OFDM; tlrs++) {
  2831. for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
  2832. for (channel = 0; channel < CENTER_CH_2G_NUM; ++channel) {
  2833. if (ent->lmt_2g[CHANNEL_WIDTH_20][tlrs][channel][ntx_idx] != hal_spec->txgi_max) {
  2834. if (tlrs == TXPWR_LMT_RS_CCK)
  2835. rfctl->txpwr_lmt_2g_cck_ofdm_state |= TXPWR_LMT_HAS_CCK_1T << ntx_idx;
  2836. else
  2837. rfctl->txpwr_lmt_2g_cck_ofdm_state |= TXPWR_LMT_HAS_OFDM_1T << ntx_idx;
  2838. break;
  2839. }
  2840. }
  2841. }
  2842. }
  2843. /* if 2G OFDM multi-TX is not defined, reference HT20 */
  2844. for (channel = 0; channel < CENTER_CH_2G_NUM; ++channel) {
  2845. for (ntx_idx = RF_2TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
  2846. if (rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx))
  2847. continue;
  2848. ent->lmt_2g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_OFDM][channel][ntx_idx] =
  2849. ent->lmt_2g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_HT][channel][ntx_idx];
  2850. }
  2851. }
  2852. #ifdef CONFIG_IEEE80211_BAND_5GHZ
  2853. /* check 5G OFDM state*/
  2854. for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
  2855. for (channel = 0; channel < CENTER_CH_5G_ALL_NUM; ++channel) {
  2856. if (ent->lmt_5g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_OFDM - 1][channel][ntx_idx] != hal_spec->txgi_max) {
  2857. rfctl->txpwr_lmt_5g_cck_ofdm_state |= TXPWR_LMT_HAS_OFDM_1T << ntx_idx;
  2858. break;
  2859. }
  2860. }
  2861. }
  2862. for (channel = 0; channel < CENTER_CH_5G_ALL_NUM; ++channel) {
  2863. for (ntx_idx = RF_2TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
  2864. if (rfctl->txpwr_lmt_5g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx))
  2865. continue;
  2866. /* if 5G OFDM multi-TX is not defined, reference HT20 */
  2867. ent->lmt_5g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_OFDM - 1][channel][ntx_idx] =
  2868. ent->lmt_5g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_HT - 1][channel][ntx_idx];
  2869. }
  2870. }
  2871. #endif /* CONFIG_IEEE80211_BAND_5GHZ */
  2872. }
  2873. }
  2874. #ifdef CONFIG_IEEE80211_BAND_5GHZ
  2875. static void phy_txpwr_lmt_cross_ref_ht_vht(_adapter *adapter)
  2876. {
  2877. struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
  2878. struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
  2879. struct txpwr_lmt_ent *ent;
  2880. _list *cur, *head;
  2881. u8 bw, channel, tlrs, ref_tlrs, ntx_idx;
  2882. int ht_ref_vht_5g_20_40 = 0;
  2883. int vht_ref_ht_5g_20_40 = 0;
  2884. int ht_has_ref_5g_20_40 = 0;
  2885. int vht_has_ref_5g_20_40 = 0;
  2886. rfctl->txpwr_lmt_5g_20_40_ref = 0;
  2887. head = &rfctl->txpwr_lmt_list;
  2888. cur = get_next(head);
  2889. while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
  2890. ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
  2891. cur = get_next(cur);
  2892. for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; ++bw) {
  2893. for (channel = 0; channel < CENTER_CH_5G_ALL_NUM; ++channel) {
  2894. for (tlrs = TXPWR_LMT_RS_HT; tlrs < TXPWR_LMT_RS_NUM; ++tlrs) {
  2895. /* 5G 20M 40M VHT and HT can cross reference */
  2896. if (bw == CHANNEL_WIDTH_20 || bw == CHANNEL_WIDTH_40) {
  2897. if (tlrs == TXPWR_LMT_RS_HT)
  2898. ref_tlrs = TXPWR_LMT_RS_VHT;
  2899. else if (tlrs == TXPWR_LMT_RS_VHT)
  2900. ref_tlrs = TXPWR_LMT_RS_HT;
  2901. else
  2902. continue;
  2903. for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
  2904. if (ent->lmt_5g[bw][ref_tlrs - 1][channel][ntx_idx] == hal_spec->txgi_max)
  2905. continue;
  2906. if (tlrs == TXPWR_LMT_RS_HT)
  2907. ht_has_ref_5g_20_40++;
  2908. else if (tlrs == TXPWR_LMT_RS_VHT)
  2909. vht_has_ref_5g_20_40++;
  2910. else
  2911. continue;
  2912. if (ent->lmt_5g[bw][tlrs - 1][channel][ntx_idx] != hal_spec->txgi_max)
  2913. continue;
  2914. if (tlrs == TXPWR_LMT_RS_HT && ref_tlrs == TXPWR_LMT_RS_VHT)
  2915. ht_ref_vht_5g_20_40++;
  2916. else if (tlrs == TXPWR_LMT_RS_VHT && ref_tlrs == TXPWR_LMT_RS_HT)
  2917. vht_ref_ht_5g_20_40++;
  2918. if (0)
  2919. RTW_INFO("reg:%s, bw:%u, ch:%u, %s-%uT ref %s-%uT\n"
  2920. , ent->regd_name, bw, channel
  2921. , txpwr_lmt_rs_str(tlrs), ntx_idx + 1
  2922. , txpwr_lmt_rs_str(ref_tlrs), ntx_idx + 1);
  2923. ent->lmt_5g[bw][tlrs - 1][channel][ntx_idx] =
  2924. ent->lmt_5g[bw][ref_tlrs - 1][channel][ntx_idx];
  2925. }
  2926. }
  2927. }
  2928. }
  2929. }
  2930. }
  2931. if (0) {
  2932. RTW_INFO("ht_ref_vht_5g_20_40:%d, ht_has_ref_5g_20_40:%d\n", ht_ref_vht_5g_20_40, ht_has_ref_5g_20_40);
  2933. RTW_INFO("vht_ref_ht_5g_20_40:%d, vht_has_ref_5g_20_40:%d\n", vht_ref_ht_5g_20_40, vht_has_ref_5g_20_40);
  2934. }
  2935. /* 5G 20M&40M HT all come from VHT*/
  2936. if (ht_ref_vht_5g_20_40 && ht_has_ref_5g_20_40 == ht_ref_vht_5g_20_40)
  2937. rfctl->txpwr_lmt_5g_20_40_ref |= TXPWR_LMT_REF_HT_FROM_VHT;
  2938. /* 5G 20M&40M VHT all come from HT*/
  2939. if (vht_ref_ht_5g_20_40 && vht_has_ref_5g_20_40 == vht_ref_ht_5g_20_40)
  2940. rfctl->txpwr_lmt_5g_20_40_ref |= TXPWR_LMT_REF_VHT_FROM_HT;
  2941. }
  2942. #endif /* CONFIG_IEEE80211_BAND_5GHZ */
  2943. #ifndef DBG_TXPWR_LMT_BAND_CHK
  2944. #define DBG_TXPWR_LMT_BAND_CHK 0
  2945. #endif
  2946. #if DBG_TXPWR_LMT_BAND_CHK
  2947. /* check if larger bandwidth limit is less than smaller bandwidth for HT & VHT rate */
  2948. void phy_txpwr_limit_bandwidth_chk(_adapter *adapter)
  2949. {
  2950. struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
  2951. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
  2952. struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
  2953. u8 band, bw, path, tlrs, ntx_idx, cch, offset, scch;
  2954. u8 ch_num, n, i;
  2955. for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
  2956. if (!hal_is_band_support(adapter, band))
  2957. continue;
  2958. for (bw = CHANNEL_WIDTH_40; bw <= CHANNEL_WIDTH_80; bw++) {
  2959. if (bw >= CHANNEL_WIDTH_160)
  2960. continue;
  2961. if (band == BAND_ON_2_4G && bw >= CHANNEL_WIDTH_80)
  2962. continue;
  2963. if (band == BAND_ON_2_4G)
  2964. ch_num = center_chs_2g_num(bw);
  2965. else
  2966. ch_num = center_chs_5g_num(bw);
  2967. if (ch_num == 0) {
  2968. rtw_warn_on(1);
  2969. break;
  2970. }
  2971. for (tlrs = TXPWR_LMT_RS_HT; tlrs < TXPWR_LMT_RS_NUM; tlrs++) {
  2972. if (band == BAND_ON_2_4G && tlrs == TXPWR_LMT_RS_VHT)
  2973. continue;
  2974. if (band == BAND_ON_5G && tlrs == TXPWR_LMT_RS_CCK)
  2975. continue;
  2976. if (bw > CHANNEL_WIDTH_20 && (tlrs == TXPWR_LMT_RS_CCK || tlrs == TXPWR_LMT_RS_OFDM))
  2977. continue;
  2978. if (bw > CHANNEL_WIDTH_40 && tlrs == TXPWR_LMT_RS_HT)
  2979. continue;
  2980. if (tlrs == TXPWR_LMT_RS_VHT && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter))
  2981. continue;
  2982. for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
  2983. struct txpwr_lmt_ent *ent;
  2984. _list *cur, *head;
  2985. if (ntx_idx >= hal_spec->tx_nss_num)
  2986. continue;
  2987. /* bypass CCK multi-TX is not defined */
  2988. if (tlrs == TXPWR_LMT_RS_CCK && ntx_idx > RF_1TX) {
  2989. if (band == BAND_ON_2_4G
  2990. && !(rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_CCK_1T << ntx_idx)))
  2991. continue;
  2992. }
  2993. /* bypass OFDM multi-TX is not defined */
  2994. if (tlrs == TXPWR_LMT_RS_OFDM && ntx_idx > RF_1TX) {
  2995. if (band == BAND_ON_2_4G
  2996. && !(rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx)))
  2997. continue;
  2998. #ifdef CONFIG_IEEE80211_BAND_5GHZ
  2999. if (band == BAND_ON_5G
  3000. && !(rfctl->txpwr_lmt_5g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx)))
  3001. continue;
  3002. #endif
  3003. }
  3004. /* bypass 5G 20M, 40M pure reference */
  3005. #ifdef CONFIG_IEEE80211_BAND_5GHZ
  3006. if (band == BAND_ON_5G && (bw == CHANNEL_WIDTH_20 || bw == CHANNEL_WIDTH_40)) {
  3007. if (rfctl->txpwr_lmt_5g_20_40_ref == TXPWR_LMT_REF_HT_FROM_VHT) {
  3008. if (tlrs == TXPWR_LMT_RS_HT)
  3009. continue;
  3010. } else if (rfctl->txpwr_lmt_5g_20_40_ref == TXPWR_LMT_REF_VHT_FROM_HT) {
  3011. if (tlrs == TXPWR_LMT_RS_VHT && bw <= CHANNEL_WIDTH_40)
  3012. continue;
  3013. }
  3014. }
  3015. #endif
  3016. for (n = 0; n < ch_num; n++) {
  3017. u8 cch_by_bw[3];
  3018. u8 offset_by_bw; /* bitmap, 0 for lower, 1 for upper */
  3019. u8 bw_pos;
  3020. s8 lmt[3];
  3021. if (band == BAND_ON_2_4G)
  3022. cch = center_chs_2g(bw, n);
  3023. else
  3024. cch = center_chs_5g(bw, n);
  3025. if (cch == 0) {
  3026. rtw_warn_on(1);
  3027. break;
  3028. }
  3029. _rtw_memset(cch_by_bw, 0, 3);
  3030. cch_by_bw[bw] = cch;
  3031. offset_by_bw = 0x01;
  3032. do {
  3033. for (bw_pos = bw; bw_pos >= CHANNEL_WIDTH_40; bw_pos--)
  3034. cch_by_bw[bw_pos - 1] = rtw_get_scch_by_cch_offset(cch_by_bw[bw_pos], bw_pos, offset_by_bw & BIT(bw_pos) ? HAL_PRIME_CHNL_OFFSET_UPPER : HAL_PRIME_CHNL_OFFSET_LOWER);
  3035. head = &rfctl->txpwr_lmt_list;
  3036. cur = get_next(head);
  3037. while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
  3038. ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
  3039. cur = get_next(cur);
  3040. for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--)
  3041. lmt[bw_pos] = phy_get_txpwr_lmt_abs(adapter, ent->regd_name, band, bw_pos, tlrs, ntx_idx, cch_by_bw[bw_pos], 0);
  3042. for (bw_pos = bw; bw_pos > CHANNEL_WIDTH_20; bw_pos--)
  3043. if (lmt[bw_pos] > lmt[bw_pos - 1])
  3044. break;
  3045. if (bw_pos == CHANNEL_WIDTH_20)
  3046. continue;
  3047. RTW_PRINT_SEL(RTW_DBGDUMP, "[%s][%s][%s][%uT][%-4s] cch:"
  3048. , band_str(band)
  3049. , ch_width_str(bw)
  3050. , txpwr_lmt_rs_str(tlrs)
  3051. , ntx_idx + 1
  3052. , ent->regd_name
  3053. );
  3054. for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--)
  3055. _RTW_PRINT_SEL(RTW_DBGDUMP, "%03u ", cch_by_bw[bw_pos]);
  3056. _RTW_PRINT_SEL(RTW_DBGDUMP, "limit:");
  3057. for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--) {
  3058. if (lmt[bw_pos] == hal_spec->txgi_max)
  3059. _RTW_PRINT_SEL(RTW_DBGDUMP, "N/A ");
  3060. else if (lmt[bw_pos] > -hal_spec->txgi_pdbm && lmt[bw_pos] < 0) /* -1 < value < 0 */
  3061. _RTW_PRINT_SEL(RTW_DBGDUMP, "-0.%d", (rtw_abs(lmt[bw_pos]) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);
  3062. else if (lmt[bw_pos] % hal_spec->txgi_pdbm)
  3063. _RTW_PRINT_SEL(RTW_DBGDUMP, "%2d.%d ", lmt[bw_pos] / hal_spec->txgi_pdbm, (rtw_abs(lmt[bw_pos]) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);
  3064. else
  3065. _RTW_PRINT_SEL(RTW_DBGDUMP, "%2d ", lmt[bw_pos] / hal_spec->txgi_pdbm);
  3066. }
  3067. _RTW_PRINT_SEL(RTW_DBGDUMP, "\n");
  3068. }
  3069. for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--)
  3070. lmt[bw_pos] = phy_get_txpwr_lmt_abs(adapter, regd_str(TXPWR_LMT_WW), band, bw_pos, tlrs, ntx_idx, cch_by_bw[bw_pos], 0);
  3071. for (bw_pos = bw; bw_pos > CHANNEL_WIDTH_20; bw_pos--)
  3072. if (lmt[bw_pos] > lmt[bw_pos - 1])
  3073. break;
  3074. if (bw_pos != CHANNEL_WIDTH_20) {
  3075. RTW_PRINT_SEL(RTW_DBGDUMP, "[%s][%s][%s][%uT][%-4s] cch:"
  3076. , band_str(band)
  3077. , ch_width_str(bw)
  3078. , txpwr_lmt_rs_str(tlrs)
  3079. , ntx_idx + 1
  3080. , regd_str(TXPWR_LMT_WW)
  3081. );
  3082. for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--)
  3083. _RTW_PRINT_SEL(RTW_DBGDUMP, "%03u ", cch_by_bw[bw_pos]);
  3084. _RTW_PRINT_SEL(RTW_DBGDUMP, "limit:");
  3085. for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--) {
  3086. if (lmt[bw_pos] == hal_spec->txgi_max)
  3087. _RTW_PRINT_SEL(RTW_DBGDUMP, "N/A ");
  3088. else if (lmt[bw_pos] > -hal_spec->txgi_pdbm && lmt[bw_pos] < 0) /* -1 < value < 0 */
  3089. _RTW_PRINT_SEL(RTW_DBGDUMP, "-0.%d", (rtw_abs(lmt[bw_pos]) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);
  3090. else if (lmt[bw_pos] % hal_spec->txgi_pdbm)
  3091. _RTW_PRINT_SEL(RTW_DBGDUMP, "%2d.%d ", lmt[bw_pos] / hal_spec->txgi_pdbm, (rtw_abs(lmt[bw_pos]) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);
  3092. else
  3093. _RTW_PRINT_SEL(RTW_DBGDUMP, "%2d ", lmt[bw_pos] / hal_spec->txgi_pdbm);
  3094. }
  3095. _RTW_PRINT_SEL(RTW_DBGDUMP, "\n");
  3096. }
  3097. offset_by_bw += 2;
  3098. if (offset_by_bw & BIT(bw + 1))
  3099. break;
  3100. } while (1); /* loop for all ch combinations */
  3101. } /* loop for center channels */
  3102. } /* loop fo each ntx_idx */
  3103. } /* loop for tlrs */
  3104. } /* loop for bandwidth */
  3105. } /* loop for band */
  3106. }
  3107. #endif /* DBG_TXPWR_LMT_BAND_CHK */
  3108. static void phy_txpwr_lmt_post_hdl(_adapter *adapter)
  3109. {
  3110. struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
  3111. _irqL irqL;
  3112. _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
  3113. #ifdef CONFIG_IEEE80211_BAND_5GHZ
  3114. if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter))
  3115. phy_txpwr_lmt_cross_ref_ht_vht(adapter);
  3116. #endif
  3117. phy_txpwr_lmt_cck_ofdm_mt_chk(adapter);
  3118. #if DBG_TXPWR_LMT_BAND_CHK
  3119. phy_txpwr_limit_bandwidth_chk(adapter);
  3120. #endif
  3121. _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
  3122. }
  3123. BOOLEAN
  3124. GetS1ByteIntegerFromStringInDecimal(
  3125. IN char *str,
  3126. IN OUT s8 *val
  3127. )
  3128. {
  3129. u8 negative = 0;
  3130. u16 i = 0;
  3131. *val = 0;
  3132. while (str[i] != '\0') {
  3133. if (i == 0 && (str[i] == '+' || str[i] == '-')) {
  3134. if (str[i] == '-')
  3135. negative = 1;
  3136. } else if (str[i] >= '0' && str[i] <= '9') {
  3137. *val *= 10;
  3138. *val += (str[i] - '0');
  3139. } else
  3140. return _FALSE;
  3141. ++i;
  3142. }
  3143. if (negative)
  3144. *val = -*val;
  3145. return _TRUE;
  3146. }
  3147. #endif /* CONFIG_TXPWR_LIMIT */
  3148. /*
  3149. * phy_set_tx_power_limit - Parsing TX power limit from phydm array, called by odm_ConfigBB_TXPWR_LMT_XXX in phydm
  3150. */
  3151. VOID
  3152. phy_set_tx_power_limit(
  3153. IN struct dm_struct *pDM_Odm,
  3154. IN u8 *Regulation,
  3155. IN u8 *Band,
  3156. IN u8 *Bandwidth,
  3157. IN u8 *RateSection,
  3158. IN u8 *ntx,
  3159. IN u8 *Channel,
  3160. IN u8 *PowerLimit
  3161. )
  3162. {
  3163. #ifdef CONFIG_TXPWR_LIMIT
  3164. PADAPTER Adapter = pDM_Odm->adapter;
  3165. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
  3166. struct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter);
  3167. u8 band = 0, bandwidth = 0, tlrs = 0, channel;
  3168. u8 ntx_idx;
  3169. s8 powerLimit = 0, prevPowerLimit, channelIndex;
  3170. s8 ww_lmt_val = phy_txpwr_ww_lmt_value(Adapter);
  3171. if (0)
  3172. RTW_INFO("Index of power limit table [regulation %s][band %s][bw %s][rate section %s][ntx %s][chnl %s][val %s]\n"
  3173. , Regulation, Band, Bandwidth, RateSection, ntx, Channel, PowerLimit);
  3174. if (GetU1ByteIntegerFromStringInDecimal((char *)Channel, &channel) == _FALSE
  3175. || GetS1ByteIntegerFromStringInDecimal((char *)PowerLimit, &powerLimit) == _FALSE
  3176. ) {
  3177. RTW_PRINT("Illegal index of power limit table [ch %s][val %s]\n", Channel, PowerLimit);
  3178. return;
  3179. }
  3180. if (powerLimit != ww_lmt_val) {
  3181. if (powerLimit < -hal_spec->txgi_max || powerLimit > hal_spec->txgi_max)
  3182. RTW_PRINT("Illegal power limit value [ch %s][val %s]\n", Channel, PowerLimit);
  3183. if (powerLimit > hal_spec->txgi_max)
  3184. powerLimit = hal_spec->txgi_max;
  3185. else if (powerLimit < -hal_spec->txgi_max)
  3186. powerLimit = ww_lmt_val + 1;
  3187. }
  3188. if (eqNByte(RateSection, (u8 *)("CCK"), 3))
  3189. tlrs = TXPWR_LMT_RS_CCK;
  3190. else if (eqNByte(RateSection, (u8 *)("OFDM"), 4))
  3191. tlrs = TXPWR_LMT_RS_OFDM;
  3192. else if (eqNByte(RateSection, (u8 *)("HT"), 2))
  3193. tlrs = TXPWR_LMT_RS_HT;
  3194. else if (eqNByte(RateSection, (u8 *)("VHT"), 3))
  3195. tlrs = TXPWR_LMT_RS_VHT;
  3196. else {
  3197. RTW_PRINT("Wrong rate section:%s\n", RateSection);
  3198. return;
  3199. }
  3200. if (eqNByte(ntx, (u8 *)("1T"), 2))
  3201. ntx_idx = RF_1TX;
  3202. else if (eqNByte(ntx, (u8 *)("2T"), 2))
  3203. ntx_idx = RF_2TX;
  3204. else if (eqNByte(ntx, (u8 *)("3T"), 2))
  3205. ntx_idx = RF_3TX;
  3206. else if (eqNByte(ntx, (u8 *)("4T"), 2))
  3207. ntx_idx = RF_4TX;
  3208. else {
  3209. RTW_PRINT("Wrong tx num:%s\n", ntx);
  3210. return;
  3211. }
  3212. if (eqNByte(Bandwidth, (u8 *)("20M"), 3))
  3213. bandwidth = CHANNEL_WIDTH_20;
  3214. else if (eqNByte(Bandwidth, (u8 *)("40M"), 3))
  3215. bandwidth = CHANNEL_WIDTH_40;
  3216. else if (eqNByte(Bandwidth, (u8 *)("80M"), 3))
  3217. bandwidth = CHANNEL_WIDTH_80;
  3218. else if (eqNByte(Bandwidth, (u8 *)("160M"), 4))
  3219. bandwidth = CHANNEL_WIDTH_160;
  3220. else {
  3221. RTW_PRINT("unknown bandwidth: %s\n", Bandwidth);
  3222. return;
  3223. }
  3224. if (eqNByte(Band, (u8 *)("2.4G"), 4)) {
  3225. band = BAND_ON_2_4G;
  3226. channelIndex = phy_GetChannelIndexOfTxPowerLimit(BAND_ON_2_4G, channel);
  3227. if (channelIndex == -1) {
  3228. RTW_PRINT("unsupported channel: %d at 2.4G\n", channel);
  3229. return;
  3230. }
  3231. if (bandwidth >= MAX_2_4G_BANDWIDTH_NUM) {
  3232. RTW_PRINT("unsupported bandwidth: %s at 2.4G\n", Bandwidth);
  3233. return;
  3234. }
  3235. rtw_txpwr_lmt_add(adapter_to_rfctl(Adapter), Regulation, band, bandwidth, tlrs, ntx_idx, channelIndex, powerLimit);
  3236. }
  3237. #ifdef CONFIG_IEEE80211_BAND_5GHZ
  3238. else if (eqNByte(Band, (u8 *)("5G"), 2)) {
  3239. band = BAND_ON_5G;
  3240. channelIndex = phy_GetChannelIndexOfTxPowerLimit(BAND_ON_5G, channel);
  3241. if (channelIndex == -1) {
  3242. RTW_PRINT("unsupported channel: %d at 5G\n", channel);
  3243. return;
  3244. }
  3245. rtw_txpwr_lmt_add(adapter_to_rfctl(Adapter), Regulation, band, bandwidth, tlrs, ntx_idx, channelIndex, powerLimit);
  3246. }
  3247. #endif
  3248. else {
  3249. RTW_PRINT("unknown/unsupported band:%s\n", Band);
  3250. return;
  3251. }
  3252. #endif
  3253. }
  3254. u8
  3255. phy_get_tx_power_index(
  3256. IN PADAPTER pAdapter,
  3257. IN enum rf_path RFPath,
  3258. IN u8 Rate,
  3259. IN enum channel_width BandWidth,
  3260. IN u8 Channel
  3261. )
  3262. {
  3263. return rtw_hal_get_tx_power_index(pAdapter, RFPath, Rate, BandWidth, Channel, NULL);
  3264. }
  3265. VOID
  3266. PHY_SetTxPowerIndex(
  3267. IN PADAPTER pAdapter,
  3268. IN u32 PowerIndex,
  3269. IN enum rf_path RFPath,
  3270. IN u8 Rate
  3271. )
  3272. {
  3273. rtw_hal_set_tx_power_index(pAdapter, PowerIndex, RFPath, Rate);
  3274. }
  3275. void dump_tx_power_idx_title(void *sel, _adapter *adapter)
  3276. {
  3277. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
  3278. u8 bw = hal_data->current_channel_bw;
  3279. RTW_PRINT_SEL(sel, "%s", ch_width_str(bw));
  3280. if (bw >= CHANNEL_WIDTH_80)
  3281. _RTW_PRINT_SEL(sel, ", cch80:%u", hal_data->cch_80);
  3282. if (bw >= CHANNEL_WIDTH_40)
  3283. _RTW_PRINT_SEL(sel, ", cch40:%u", hal_data->cch_40);
  3284. _RTW_PRINT_SEL(sel, ", cch20:%u\n", hal_data->cch_20);
  3285. RTW_PRINT_SEL(sel, "%-4s %-9s %2s %-3s %-4s %-3s %-4s %-4s %-3s %-5s\n"
  3286. , "path", "rate", "", "pwr", "base", "", "(byr", "lmt)", "tpt", "ebias");
  3287. }
  3288. void dump_tx_power_idx_by_path_rs(void *sel, _adapter *adapter, u8 rfpath, u8 rs)
  3289. {
  3290. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
  3291. struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
  3292. u8 power_idx;
  3293. struct txpwr_idx_comp tic;
  3294. u8 tx_num, i;
  3295. u8 band = hal_data->current_band_type;
  3296. u8 cch = hal_data->current_channel;
  3297. u8 bw = hal_data->current_channel_bw;
  3298. if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, rfpath))
  3299. return;
  3300. if (rs >= RATE_SECTION_NUM)
  3301. return;
  3302. tx_num = rate_section_to_tx_num(rs);
  3303. if (tx_num >= hal_spec->tx_nss_num || tx_num >= hal_spec->max_tx_cnt)
  3304. return;
  3305. if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
  3306. return;
  3307. if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter))
  3308. return;
  3309. for (i = 0; i < rates_by_sections[rs].rate_num; i++) {
  3310. power_idx = rtw_hal_get_tx_power_index(adapter, rfpath, rates_by_sections[rs].rates[i], bw, cch, &tic);
  3311. RTW_PRINT_SEL(sel, "%4c %9s %uT %3u %4u %3d (%3d %3d) %3d %5d\n"
  3312. , rf_path_char(rfpath), MGN_RATE_STR(rates_by_sections[rs].rates[i]), tic.ntx_idx + 1
  3313. , power_idx, tic.base, (tic.by_rate > tic.limit ? tic.limit : tic.by_rate), tic.by_rate, tic.limit, tic.tpt, tic.ebias);
  3314. }
  3315. }
  3316. void dump_tx_power_idx(void *sel, _adapter *adapter)
  3317. {
  3318. u8 rfpath, rs;
  3319. dump_tx_power_idx_title(sel, adapter);
  3320. for (rfpath = RF_PATH_A; rfpath < RF_PATH_MAX; rfpath++)
  3321. for (rs = CCK; rs < RATE_SECTION_NUM; rs++)
  3322. dump_tx_power_idx_by_path_rs(sel, adapter, rfpath, rs);
  3323. }
  3324. bool phy_is_tx_power_limit_needed(_adapter *adapter)
  3325. {
  3326. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
  3327. struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter));
  3328. #ifdef CONFIG_TXPWR_LIMIT
  3329. if (regsty->RegEnableTxPowerLimit == 1
  3330. || (regsty->RegEnableTxPowerLimit == 2 && hal_data->EEPROMRegulatory == 1))
  3331. return _TRUE;
  3332. #endif
  3333. return _FALSE;
  3334. }
  3335. bool phy_is_tx_power_by_rate_needed(_adapter *adapter)
  3336. {
  3337. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
  3338. struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter));
  3339. if (regsty->RegEnableTxPowerByRate == 1
  3340. || (regsty->RegEnableTxPowerByRate == 2 && hal_data->EEPROMRegulatory != 2))
  3341. return _TRUE;
  3342. return _FALSE;
  3343. }
  3344. int phy_load_tx_power_by_rate(_adapter *adapter, u8 chk_file)
  3345. {
  3346. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
  3347. struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter));
  3348. int ret = _FAIL;
  3349. hal_data->txpwr_by_rate_loaded = 0;
  3350. PHY_InitTxPowerByRate(adapter);
  3351. /* tx power limit is based on tx power by rate */
  3352. hal_data->txpwr_limit_loaded = 0;
  3353. #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
  3354. if (chk_file
  3355. && phy_ConfigBBWithPgParaFile(adapter, PHY_FILE_PHY_REG_PG) == _SUCCESS
  3356. ) {
  3357. hal_data->txpwr_by_rate_from_file = 1;
  3358. goto post_hdl;
  3359. }
  3360. #endif
  3361. #ifdef CONFIG_EMBEDDED_FWIMG
  3362. if (HAL_STATUS_SUCCESS == odm_config_bb_with_header_file(&hal_data->odmpriv, CONFIG_BB_PHY_REG_PG)) {
  3363. RTW_INFO("default power by rate loaded\n");
  3364. hal_data->txpwr_by_rate_from_file = 0;
  3365. goto post_hdl;
  3366. }
  3367. #endif
  3368. RTW_ERR("%s():Read Tx power by rate fail\n", __func__);
  3369. goto exit;
  3370. post_hdl:
  3371. if (hal_data->odmpriv.phy_reg_pg_value_type != PHY_REG_PG_EXACT_VALUE) {
  3372. rtw_warn_on(1);
  3373. goto exit;
  3374. }
  3375. PHY_TxPowerByRateConfiguration(adapter);
  3376. hal_data->txpwr_by_rate_loaded = 1;
  3377. ret = _SUCCESS;
  3378. exit:
  3379. return ret;
  3380. }
  3381. #ifdef CONFIG_TXPWR_LIMIT
  3382. int phy_load_tx_power_limit(_adapter *adapter, u8 chk_file)
  3383. {
  3384. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
  3385. struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter));
  3386. struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
  3387. int ret = _FAIL;
  3388. hal_data->txpwr_limit_loaded = 0;
  3389. rtw_regd_exc_list_free(rfctl);
  3390. rtw_txpwr_lmt_list_free(rfctl);
  3391. if (!hal_data->txpwr_by_rate_loaded && regsty->target_tx_pwr_valid != _TRUE) {
  3392. RTW_ERR("%s():Read Tx power limit before target tx power is specify\n", __func__);
  3393. goto exit;
  3394. }
  3395. #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
  3396. if (chk_file
  3397. && PHY_ConfigRFWithPowerLimitTableParaFile(adapter, PHY_FILE_TXPWR_LMT) == _SUCCESS
  3398. ) {
  3399. hal_data->txpwr_limit_from_file = 1;
  3400. goto post_hdl;
  3401. }
  3402. #endif
  3403. #ifdef CONFIG_EMBEDDED_FWIMG
  3404. if (odm_config_rf_with_header_file(&hal_data->odmpriv, CONFIG_RF_TXPWR_LMT, RF_PATH_A) == HAL_STATUS_SUCCESS) {
  3405. RTW_INFO("default power limit loaded\n");
  3406. hal_data->txpwr_limit_from_file = 0;
  3407. goto post_hdl;
  3408. }
  3409. #endif
  3410. RTW_ERR("%s():Read Tx power limit fail\n", __func__);
  3411. goto exit;
  3412. post_hdl:
  3413. phy_txpwr_lmt_post_hdl(adapter);
  3414. rtw_txpwr_init_regd(rfctl);
  3415. hal_data->txpwr_limit_loaded = 1;
  3416. ret = _SUCCESS;
  3417. exit:
  3418. return ret;
  3419. }
  3420. #endif /* CONFIG_TXPWR_LIMIT */
  3421. void phy_load_tx_power_ext_info(_adapter *adapter, u8 chk_file)
  3422. {
  3423. struct registry_priv *regsty = adapter_to_regsty(adapter);
  3424. /* check registy target tx power */
  3425. regsty->target_tx_pwr_valid = rtw_regsty_chk_target_tx_power_valid(adapter);
  3426. /* power by rate and limit */
  3427. if (phy_is_tx_power_by_rate_needed(adapter)
  3428. || (phy_is_tx_power_limit_needed(adapter) && regsty->target_tx_pwr_valid != _TRUE)
  3429. )
  3430. phy_load_tx_power_by_rate(adapter, chk_file);
  3431. #ifdef CONFIG_TXPWR_LIMIT
  3432. if (phy_is_tx_power_limit_needed(adapter))
  3433. phy_load_tx_power_limit(adapter, chk_file);
  3434. #endif
  3435. }
  3436. inline void phy_reload_tx_power_ext_info(_adapter *adapter)
  3437. {
  3438. phy_load_tx_power_ext_info(adapter, 1);
  3439. }
  3440. inline void phy_reload_default_tx_power_ext_info(_adapter *adapter)
  3441. {
  3442. phy_load_tx_power_ext_info(adapter, 0);
  3443. }
  3444. void dump_tx_power_ext_info(void *sel, _adapter *adapter)
  3445. {
  3446. struct registry_priv *regsty = adapter_to_regsty(adapter);
  3447. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
  3448. if (regsty->target_tx_pwr_valid == _TRUE)
  3449. RTW_PRINT_SEL(sel, "target_tx_power: from registry\n");
  3450. else if (phy_is_tx_power_by_rate_needed(adapter))
  3451. RTW_PRINT_SEL(sel, "target_tx_power: from power by rate\n");
  3452. else
  3453. RTW_PRINT_SEL(sel, "target_tx_power: unavailable\n");
  3454. RTW_PRINT_SEL(sel, "tx_power_by_rate: %s, %s, %s\n"
  3455. , phy_is_tx_power_by_rate_needed(adapter) ? "enabled" : "disabled"
  3456. , hal_data->txpwr_by_rate_loaded ? "loaded" : "unloaded"
  3457. , hal_data->txpwr_by_rate_from_file ? "file" : "default"
  3458. );
  3459. RTW_PRINT_SEL(sel, "tx_power_limit: %s, %s, %s\n"
  3460. , phy_is_tx_power_limit_needed(adapter) ? "enabled" : "disabled"
  3461. , hal_data->txpwr_limit_loaded ? "loaded" : "unloaded"
  3462. , hal_data->txpwr_limit_from_file ? "file" : "default"
  3463. );
  3464. }
  3465. void dump_target_tx_power(void *sel, _adapter *adapter)
  3466. {
  3467. struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
  3468. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
  3469. struct registry_priv *regsty = adapter_to_regsty(adapter);
  3470. int path, tx_num, band, rs;
  3471. u8 target;
  3472. for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
  3473. if (!hal_is_band_support(adapter, band))
  3474. continue;
  3475. for (path = 0; path < RF_PATH_MAX; path++) {
  3476. if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
  3477. break;
  3478. RTW_PRINT_SEL(sel, "[%s][%c]%s\n", band_str(band), rf_path_char(path)
  3479. , (regsty->target_tx_pwr_valid == _FALSE && hal_data->txpwr_by_rate_undefined_band_path[band][path]) ? "(dup)" : "");
  3480. for (rs = 0; rs < RATE_SECTION_NUM; rs++) {
  3481. tx_num = rate_section_to_tx_num(rs);
  3482. if (tx_num >= hal_spec->tx_nss_num)
  3483. continue;
  3484. if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
  3485. continue;
  3486. if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter))
  3487. continue;
  3488. target = PHY_GetTxPowerByRateBase(adapter, band, path, rs);
  3489. if (target % hal_spec->txgi_pdbm) {
  3490. _RTW_PRINT_SEL(sel, "%7s: %2d.%d\n", rate_section_str(rs)
  3491. , target / hal_spec->txgi_pdbm, (target % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);
  3492. } else {
  3493. _RTW_PRINT_SEL(sel, "%7s: %5d\n", rate_section_str(rs)
  3494. , target / hal_spec->txgi_pdbm);
  3495. }
  3496. }
  3497. }
  3498. }
  3499. exit:
  3500. return;
  3501. }
  3502. void dump_tx_power_by_rate(void *sel, _adapter *adapter)
  3503. {
  3504. struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
  3505. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
  3506. int path, tx_num, band, n, rs;
  3507. u8 rate_num, max_rate_num, base;
  3508. s8 by_rate_offset;
  3509. for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
  3510. if (!hal_is_band_support(adapter, band))
  3511. continue;
  3512. for (path = 0; path < RF_PATH_MAX; path++) {
  3513. if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
  3514. break;
  3515. RTW_PRINT_SEL(sel, "[%s][%c]%s\n", band_str(band), rf_path_char(path)
  3516. , hal_data->txpwr_by_rate_undefined_band_path[band][path] ? "(dup)" : "");
  3517. for (rs = 0; rs < RATE_SECTION_NUM; rs++) {
  3518. tx_num = rate_section_to_tx_num(rs);
  3519. if (tx_num >= hal_spec->tx_nss_num)
  3520. continue;
  3521. if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
  3522. continue;
  3523. if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter))
  3524. continue;
  3525. if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter))
  3526. max_rate_num = 10;
  3527. else
  3528. max_rate_num = 8;
  3529. rate_num = rate_section_rate_num(rs);
  3530. base = PHY_GetTxPowerByRateBase(adapter, band, path, rs);
  3531. RTW_PRINT_SEL(sel, "%7s: ", rate_section_str(rs));
  3532. /* dump power by rate in db */
  3533. for (n = rate_num - 1; n >= 0; n--) {
  3534. by_rate_offset = PHY_GetTxPowerByRate(adapter, band, path, rates_by_sections[rs].rates[n]);
  3535. if ((base + by_rate_offset) % hal_spec->txgi_pdbm) {
  3536. _RTW_PRINT_SEL(sel, "%2d.%d ", (base + by_rate_offset) / hal_spec->txgi_pdbm
  3537. , ((base + by_rate_offset) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);
  3538. } else
  3539. _RTW_PRINT_SEL(sel, "%5d ", (base + by_rate_offset) / hal_spec->txgi_pdbm);
  3540. }
  3541. for (n = 0; n < max_rate_num - rate_num; n++)
  3542. _RTW_PRINT_SEL(sel, "%5s ", "");
  3543. _RTW_PRINT_SEL(sel, "|");
  3544. /* dump power by rate in offset */
  3545. for (n = rate_num - 1; n >= 0; n--) {
  3546. by_rate_offset = PHY_GetTxPowerByRate(adapter, band, path, rates_by_sections[rs].rates[n]);
  3547. _RTW_PRINT_SEL(sel, "%3d ", by_rate_offset);
  3548. }
  3549. RTW_PRINT_SEL(sel, "\n");
  3550. }
  3551. }
  3552. }
  3553. }
  3554. /*
  3555. * phy file path is stored in global char array rtw_phy_para_file_path
  3556. * need to care about racing
  3557. */
  3558. int rtw_get_phy_file_path(_adapter *adapter, const char *file_name)
  3559. {
  3560. #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
  3561. struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
  3562. int len = 0;
  3563. if (file_name) {
  3564. len += snprintf(rtw_phy_para_file_path, PATH_LENGTH_MAX, "%s", rtw_phy_file_path);
  3565. #if defined(CONFIG_MULTIDRV) || defined(REALTEK_CONFIG_PATH_WITH_IC_NAME_FOLDER)
  3566. len += snprintf(rtw_phy_para_file_path + len, PATH_LENGTH_MAX - len, "%s/", hal_spec->ic_name);
  3567. #endif
  3568. len += snprintf(rtw_phy_para_file_path + len, PATH_LENGTH_MAX - len, "%s", file_name);
  3569. return _TRUE;
  3570. }
  3571. #endif
  3572. return _FALSE;
  3573. }
  3574. #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
  3575. int
  3576. phy_ConfigMACWithParaFile(
  3577. IN PADAPTER Adapter,
  3578. IN char *pFileName
  3579. )
  3580. {
  3581. PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
  3582. int rlen = 0, rtStatus = _FAIL;
  3583. char *szLine, *ptmp;
  3584. u32 u4bRegOffset, u4bRegValue, u4bMove;
  3585. if (!(Adapter->registrypriv.load_phy_file & LOAD_MAC_PARA_FILE))
  3586. return rtStatus;
  3587. _rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
  3588. if ((pHalData->mac_reg_len == 0) && (pHalData->mac_reg == NULL)) {
  3589. rtw_get_phy_file_path(Adapter, pFileName);
  3590. if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) {
  3591. rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
  3592. if (rlen > 0) {
  3593. rtStatus = _SUCCESS;
  3594. pHalData->mac_reg = rtw_zvmalloc(rlen);
  3595. if (pHalData->mac_reg) {
  3596. _rtw_memcpy(pHalData->mac_reg, pHalData->para_file_buf, rlen);
  3597. pHalData->mac_reg_len = rlen;
  3598. } else
  3599. RTW_INFO("%s mac_reg alloc fail !\n", __FUNCTION__);
  3600. }
  3601. }
  3602. } else {
  3603. if ((pHalData->mac_reg_len != 0) && (pHalData->mac_reg != NULL)) {
  3604. _rtw_memcpy(pHalData->para_file_buf, pHalData->mac_reg, pHalData->mac_reg_len);
  3605. rtStatus = _SUCCESS;
  3606. } else
  3607. RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__);
  3608. }
  3609. if (rtStatus == _SUCCESS) {
  3610. ptmp = pHalData->para_file_buf;
  3611. for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
  3612. if (!IsCommentString(szLine)) {
  3613. /* Get 1st hex value as register offset */
  3614. if (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) {
  3615. if (u4bRegOffset == 0xffff) {
  3616. /* Ending. */
  3617. break;
  3618. }
  3619. /* Get 2nd hex value as register value. */
  3620. szLine += u4bMove;
  3621. if (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove))
  3622. rtw_write8(Adapter, u4bRegOffset, (u8)u4bRegValue);
  3623. }
  3624. }
  3625. }
  3626. } else
  3627. RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName);
  3628. return rtStatus;
  3629. }
  3630. int
  3631. phy_ConfigBBWithParaFile(
  3632. IN PADAPTER Adapter,
  3633. IN char *pFileName,
  3634. IN u32 ConfigType
  3635. )
  3636. {
  3637. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
  3638. int rlen = 0, rtStatus = _FAIL;
  3639. char *szLine, *ptmp;
  3640. u32 u4bRegOffset, u4bRegValue, u4bMove;
  3641. char *pBuf = NULL;
  3642. u32 *pBufLen = NULL;
  3643. if (!(Adapter->registrypriv.load_phy_file & LOAD_BB_PARA_FILE))
  3644. return rtStatus;
  3645. switch (ConfigType) {
  3646. case CONFIG_BB_PHY_REG:
  3647. pBuf = pHalData->bb_phy_reg;
  3648. pBufLen = &pHalData->bb_phy_reg_len;
  3649. break;
  3650. case CONFIG_BB_AGC_TAB:
  3651. pBuf = pHalData->bb_agc_tab;
  3652. pBufLen = &pHalData->bb_agc_tab_len;
  3653. break;
  3654. default:
  3655. RTW_INFO("Unknown ConfigType!! %d\r\n", ConfigType);
  3656. break;
  3657. }
  3658. _rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
  3659. if ((pBufLen != NULL) && (*pBufLen == 0) && (pBuf == NULL)) {
  3660. rtw_get_phy_file_path(Adapter, pFileName);
  3661. if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) {
  3662. rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
  3663. if (rlen > 0) {
  3664. rtStatus = _SUCCESS;
  3665. pBuf = rtw_zvmalloc(rlen);
  3666. if (pBuf) {
  3667. _rtw_memcpy(pBuf, pHalData->para_file_buf, rlen);
  3668. *pBufLen = rlen;
  3669. switch (ConfigType) {
  3670. case CONFIG_BB_PHY_REG:
  3671. pHalData->bb_phy_reg = pBuf;
  3672. break;
  3673. case CONFIG_BB_AGC_TAB:
  3674. pHalData->bb_agc_tab = pBuf;
  3675. break;
  3676. }
  3677. } else
  3678. RTW_INFO("%s(): ConfigType %d alloc fail !\n", __FUNCTION__, ConfigType);
  3679. }
  3680. }
  3681. } else {
  3682. if ((pBufLen != NULL) && (*pBufLen != 0) && (pBuf != NULL)) {
  3683. _rtw_memcpy(pHalData->para_file_buf, pBuf, *pBufLen);
  3684. rtStatus = _SUCCESS;
  3685. } else
  3686. RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__);
  3687. }
  3688. if (rtStatus == _SUCCESS) {
  3689. ptmp = pHalData->para_file_buf;
  3690. for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
  3691. if (!IsCommentString(szLine)) {
  3692. /* Get 1st hex value as register offset. */
  3693. if (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) {
  3694. if (u4bRegOffset == 0xffff) {
  3695. /* Ending. */
  3696. break;
  3697. } else if (u4bRegOffset == 0xfe || u4bRegOffset == 0xffe) {
  3698. #ifdef CONFIG_LONG_DELAY_ISSUE
  3699. rtw_msleep_os(50);
  3700. #else
  3701. rtw_mdelay_os(50);
  3702. #endif
  3703. } else if (u4bRegOffset == 0xfd)
  3704. rtw_mdelay_os(5);
  3705. else if (u4bRegOffset == 0xfc)
  3706. rtw_mdelay_os(1);
  3707. else if (u4bRegOffset == 0xfb)
  3708. rtw_udelay_os(50);
  3709. else if (u4bRegOffset == 0xfa)
  3710. rtw_udelay_os(5);
  3711. else if (u4bRegOffset == 0xf9)
  3712. rtw_udelay_os(1);
  3713. /* Get 2nd hex value as register value. */
  3714. szLine += u4bMove;
  3715. if (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) {
  3716. /* RTW_INFO("[BB-ADDR]%03lX=%08lX\n", u4bRegOffset, u4bRegValue); */
  3717. phy_set_bb_reg(Adapter, u4bRegOffset, bMaskDWord, u4bRegValue);
  3718. if (u4bRegOffset == 0xa24)
  3719. pHalData->odmpriv.rf_calibrate_info.rega24 = u4bRegValue;
  3720. /* Add 1us delay between BB/RF register setting. */
  3721. rtw_udelay_os(1);
  3722. }
  3723. }
  3724. }
  3725. }
  3726. } else
  3727. RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName);
  3728. return rtStatus;
  3729. }
  3730. VOID
  3731. phy_DecryptBBPgParaFile(
  3732. PADAPTER Adapter,
  3733. char *buffer
  3734. )
  3735. {
  3736. u32 i = 0, j = 0;
  3737. u8 map[95] = {0};
  3738. u8 currentChar;
  3739. char *BufOfLines, *ptmp;
  3740. /* RTW_INFO("=====>phy_DecryptBBPgParaFile()\n"); */
  3741. /* 32 the ascii code of the first visable char, 126 the last one */
  3742. for (i = 0; i < 95; ++i)
  3743. map[i] = (u8)(94 - i);
  3744. ptmp = buffer;
  3745. i = 0;
  3746. for (BufOfLines = GetLineFromBuffer(ptmp); BufOfLines != NULL; BufOfLines = GetLineFromBuffer(ptmp)) {
  3747. /* RTW_INFO("Encrypted Line: %s\n", BufOfLines); */
  3748. for (j = 0; j < strlen(BufOfLines); ++j) {
  3749. currentChar = BufOfLines[j];
  3750. if (currentChar == '\0')
  3751. break;
  3752. currentChar -= (u8)((((i + j) * 3) % 128));
  3753. BufOfLines[j] = map[currentChar - 32] + 32;
  3754. }
  3755. /* RTW_INFO("Decrypted Line: %s\n", BufOfLines ); */
  3756. if (strlen(BufOfLines) != 0)
  3757. i++;
  3758. BufOfLines[strlen(BufOfLines)] = '\n';
  3759. }
  3760. }
  3761. #ifndef DBG_TXPWR_BY_RATE_FILE_PARSE
  3762. #define DBG_TXPWR_BY_RATE_FILE_PARSE 0
  3763. #endif
  3764. int
  3765. phy_ParseBBPgParaFile(
  3766. PADAPTER Adapter,
  3767. char *buffer
  3768. )
  3769. {
  3770. int rtStatus = _FAIL;
  3771. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
  3772. struct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter);
  3773. char *szLine, *ptmp;
  3774. u32 u4bRegOffset, u4bRegMask, u4bRegValue;
  3775. u32 u4bMove;
  3776. BOOLEAN firstLine = _TRUE;
  3777. u8 tx_num = 0;
  3778. u8 band = 0, rf_path = 0;
  3779. if (Adapter->registrypriv.RegDecryptCustomFile == 1)
  3780. phy_DecryptBBPgParaFile(Adapter, buffer);
  3781. ptmp = buffer;
  3782. for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
  3783. if (isAllSpaceOrTab(szLine, sizeof(*szLine)))
  3784. continue;
  3785. if (!IsCommentString(szLine)) {
  3786. /* Get header info (relative value or exact value) */
  3787. if (firstLine) {
  3788. if (eqNByte(szLine, (u8 *)("#[v1]"), 5))
  3789. pHalData->odmpriv.phy_reg_pg_version = szLine[3] - '0';
  3790. else {
  3791. RTW_ERR("The format in PHY_REG_PG are invalid %s\n", szLine);
  3792. goto exit;
  3793. }
  3794. if (eqNByte(szLine + 5, (u8 *)("[Exact]#"), 8)) {
  3795. pHalData->odmpriv.phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE;
  3796. firstLine = _FALSE;
  3797. continue;
  3798. } else {
  3799. RTW_ERR("The values in PHY_REG_PG are invalid %s\n", szLine);
  3800. goto exit;
  3801. }
  3802. }
  3803. if (pHalData->odmpriv.phy_reg_pg_version > 0) {
  3804. u32 index = 0, cnt = 0;
  3805. if (eqNByte(szLine, "0xffff", 6))
  3806. break;
  3807. if (!eqNByte("#[END]#", szLine, 7)) {
  3808. /* load the table label info */
  3809. if (szLine[0] == '#') {
  3810. index = 0;
  3811. if (eqNByte(szLine, "#[2.4G]" , 7)) {
  3812. band = BAND_ON_2_4G;
  3813. index += 8;
  3814. } else if (eqNByte(szLine, "#[5G]", 5)) {
  3815. band = BAND_ON_5G;
  3816. index += 6;
  3817. } else {
  3818. RTW_ERR("Invalid band %s in PHY_REG_PG.txt\n", szLine);
  3819. goto exit;
  3820. }
  3821. rf_path = szLine[index] - 'A';
  3822. if (DBG_TXPWR_BY_RATE_FILE_PARSE)
  3823. RTW_INFO(" Table label Band %d, RfPath %d\n", band, rf_path );
  3824. } else { /* load rows of tables */
  3825. if (szLine[1] == '1')
  3826. tx_num = RF_1TX;
  3827. else if (szLine[1] == '2')
  3828. tx_num = RF_2TX;
  3829. else if (szLine[1] == '3')
  3830. tx_num = RF_3TX;
  3831. else if (szLine[1] == '4')
  3832. tx_num = RF_4TX;
  3833. else {
  3834. RTW_ERR("Invalid row in PHY_REG_PG.txt '%c'(%d)\n", szLine[1], szLine[1]);
  3835. goto exit;
  3836. }
  3837. while (szLine[index] != ']')
  3838. ++index;
  3839. ++index;/* skip ] */
  3840. /* Get 2nd hex value as register offset. */
  3841. szLine += index;
  3842. if (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove))
  3843. szLine += u4bMove;
  3844. else
  3845. goto exit;
  3846. /* Get 2nd hex value as register mask. */
  3847. if (GetHexValueFromString(szLine, &u4bRegMask, &u4bMove))
  3848. szLine += u4bMove;
  3849. else
  3850. goto exit;
  3851. if (pHalData->odmpriv.phy_reg_pg_value_type == PHY_REG_PG_EXACT_VALUE) {
  3852. u32 combineValue = 0;
  3853. u8 integer = 0, fraction = 0;
  3854. if (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove))
  3855. szLine += u4bMove;
  3856. else
  3857. goto exit;
  3858. integer *= hal_spec->txgi_pdbm;
  3859. integer += ((u16)fraction * (u16)hal_spec->txgi_pdbm) / 100;
  3860. if (hal_spec->txgi_pdbm == 2)
  3861. combineValue |= (((integer / 10) << 4) + (integer % 10));
  3862. else
  3863. combineValue |= integer;
  3864. if (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove))
  3865. szLine += u4bMove;
  3866. else
  3867. goto exit;
  3868. integer *= hal_spec->txgi_pdbm;
  3869. integer += ((u16)fraction * (u16)hal_spec->txgi_pdbm) / 100;
  3870. combineValue <<= 8;
  3871. if (hal_spec->txgi_pdbm == 2)
  3872. combineValue |= (((integer / 10) << 4) + (integer % 10));
  3873. else
  3874. combineValue |= integer;
  3875. if (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove))
  3876. szLine += u4bMove;
  3877. else
  3878. goto exit;
  3879. integer *= hal_spec->txgi_pdbm;
  3880. integer += ((u16)fraction * (u16)hal_spec->txgi_pdbm) / 100;
  3881. combineValue <<= 8;
  3882. if (hal_spec->txgi_pdbm == 2)
  3883. combineValue |= (((integer / 10) << 4) + (integer % 10));
  3884. else
  3885. combineValue |= integer;
  3886. if (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove))
  3887. szLine += u4bMove;
  3888. else
  3889. goto exit;
  3890. integer *= hal_spec->txgi_pdbm;
  3891. integer += ((u16)fraction * (u16)hal_spec->txgi_pdbm) / 100;
  3892. combineValue <<= 8;
  3893. if (hal_spec->txgi_pdbm == 2)
  3894. combineValue |= (((integer / 10) << 4) + (integer % 10));
  3895. else
  3896. combineValue |= integer;
  3897. phy_store_tx_power_by_rate(Adapter, band, rf_path, tx_num, u4bRegOffset, u4bRegMask, combineValue);
  3898. if (DBG_TXPWR_BY_RATE_FILE_PARSE)
  3899. RTW_INFO("addr:0x%3x mask:0x%08x %dTx = 0x%08x\n", u4bRegOffset, u4bRegMask, tx_num, combineValue);
  3900. }
  3901. }
  3902. }
  3903. }
  3904. }
  3905. }
  3906. rtStatus = _SUCCESS;
  3907. exit:
  3908. RTW_INFO("%s return %d\n", __func__, rtStatus);
  3909. return rtStatus;
  3910. }
  3911. int
  3912. phy_ConfigBBWithPgParaFile(
  3913. IN PADAPTER Adapter,
  3914. IN const char *pFileName)
  3915. {
  3916. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
  3917. int rlen = 0, rtStatus = _FAIL;
  3918. if (!(Adapter->registrypriv.load_phy_file & LOAD_BB_PG_PARA_FILE))
  3919. return rtStatus;
  3920. _rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
  3921. if (pHalData->bb_phy_reg_pg == NULL) {
  3922. rtw_get_phy_file_path(Adapter, pFileName);
  3923. if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) {
  3924. rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
  3925. if (rlen > 0) {
  3926. rtStatus = _SUCCESS;
  3927. pHalData->bb_phy_reg_pg = rtw_zvmalloc(rlen);
  3928. if (pHalData->bb_phy_reg_pg) {
  3929. _rtw_memcpy(pHalData->bb_phy_reg_pg, pHalData->para_file_buf, rlen);
  3930. pHalData->bb_phy_reg_pg_len = rlen;
  3931. } else
  3932. RTW_INFO("%s bb_phy_reg_pg alloc fail !\n", __FUNCTION__);
  3933. }
  3934. }
  3935. } else {
  3936. if ((pHalData->bb_phy_reg_pg_len != 0) && (pHalData->bb_phy_reg_pg != NULL)) {
  3937. _rtw_memcpy(pHalData->para_file_buf, pHalData->bb_phy_reg_pg, pHalData->bb_phy_reg_pg_len);
  3938. rtStatus = _SUCCESS;
  3939. } else
  3940. RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__);
  3941. }
  3942. if (rtStatus == _SUCCESS) {
  3943. /* RTW_INFO("phy_ConfigBBWithPgParaFile(): read %s ok\n", pFileName); */
  3944. rtStatus = phy_ParseBBPgParaFile(Adapter, pHalData->para_file_buf);
  3945. } else
  3946. RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName);
  3947. return rtStatus;
  3948. }
  3949. #if (MP_DRIVER == 1)
  3950. int
  3951. phy_ConfigBBWithMpParaFile(
  3952. IN PADAPTER Adapter,
  3953. IN char *pFileName
  3954. )
  3955. {
  3956. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
  3957. int rlen = 0, rtStatus = _FAIL;
  3958. char *szLine, *ptmp;
  3959. u32 u4bRegOffset, u4bRegValue, u4bMove;
  3960. if (!(Adapter->registrypriv.load_phy_file & LOAD_BB_MP_PARA_FILE))
  3961. return rtStatus;
  3962. _rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
  3963. if ((pHalData->bb_phy_reg_mp_len == 0) && (pHalData->bb_phy_reg_mp == NULL)) {
  3964. rtw_get_phy_file_path(Adapter, pFileName);
  3965. if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) {
  3966. rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
  3967. if (rlen > 0) {
  3968. rtStatus = _SUCCESS;
  3969. pHalData->bb_phy_reg_mp = rtw_zvmalloc(rlen);
  3970. if (pHalData->bb_phy_reg_mp) {
  3971. _rtw_memcpy(pHalData->bb_phy_reg_mp, pHalData->para_file_buf, rlen);
  3972. pHalData->bb_phy_reg_mp_len = rlen;
  3973. } else
  3974. RTW_INFO("%s bb_phy_reg_mp alloc fail !\n", __FUNCTION__);
  3975. }
  3976. }
  3977. } else {
  3978. if ((pHalData->bb_phy_reg_mp_len != 0) && (pHalData->bb_phy_reg_mp != NULL)) {
  3979. _rtw_memcpy(pHalData->para_file_buf, pHalData->bb_phy_reg_mp, pHalData->bb_phy_reg_mp_len);
  3980. rtStatus = _SUCCESS;
  3981. } else
  3982. RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__);
  3983. }
  3984. if (rtStatus == _SUCCESS) {
  3985. /* RTW_INFO("phy_ConfigBBWithMpParaFile(): read %s ok\n", pFileName); */
  3986. ptmp = pHalData->para_file_buf;
  3987. for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
  3988. if (!IsCommentString(szLine)) {
  3989. /* Get 1st hex value as register offset. */
  3990. if (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) {
  3991. if (u4bRegOffset == 0xffff) {
  3992. /* Ending. */
  3993. break;
  3994. } else if (u4bRegOffset == 0xfe || u4bRegOffset == 0xffe) {
  3995. #ifdef CONFIG_LONG_DELAY_ISSUE
  3996. rtw_msleep_os(50);
  3997. #else
  3998. rtw_mdelay_os(50);
  3999. #endif
  4000. } else if (u4bRegOffset == 0xfd)
  4001. rtw_mdelay_os(5);
  4002. else if (u4bRegOffset == 0xfc)
  4003. rtw_mdelay_os(1);
  4004. else if (u4bRegOffset == 0xfb)
  4005. rtw_udelay_os(50);
  4006. else if (u4bRegOffset == 0xfa)
  4007. rtw_udelay_os(5);
  4008. else if (u4bRegOffset == 0xf9)
  4009. rtw_udelay_os(1);
  4010. /* Get 2nd hex value as register value. */
  4011. szLine += u4bMove;
  4012. if (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) {
  4013. /* RTW_INFO("[ADDR]%03lX=%08lX\n", u4bRegOffset, u4bRegValue); */
  4014. phy_set_bb_reg(Adapter, u4bRegOffset, bMaskDWord, u4bRegValue);
  4015. /* Add 1us delay between BB/RF register setting. */
  4016. rtw_udelay_os(1);
  4017. }
  4018. }
  4019. }
  4020. }
  4021. } else
  4022. RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName);
  4023. return rtStatus;
  4024. }
  4025. #endif
  4026. int
  4027. PHY_ConfigRFWithParaFile(
  4028. IN PADAPTER Adapter,
  4029. IN char *pFileName,
  4030. IN enum rf_path eRFPath
  4031. )
  4032. {
  4033. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
  4034. int rlen = 0, rtStatus = _FAIL;
  4035. char *szLine, *ptmp;
  4036. u32 u4bRegOffset, u4bRegValue, u4bMove;
  4037. u16 i;
  4038. char *pBuf = NULL;
  4039. u32 *pBufLen = NULL;
  4040. if (!(Adapter->registrypriv.load_phy_file & LOAD_RF_PARA_FILE))
  4041. return rtStatus;
  4042. switch (eRFPath) {
  4043. case RF_PATH_A:
  4044. pBuf = pHalData->rf_radio_a;
  4045. pBufLen = &pHalData->rf_radio_a_len;
  4046. break;
  4047. case RF_PATH_B:
  4048. pBuf = pHalData->rf_radio_b;
  4049. pBufLen = &pHalData->rf_radio_b_len;
  4050. break;
  4051. default:
  4052. RTW_INFO("Unknown RF path!! %d\r\n", eRFPath);
  4053. break;
  4054. }
  4055. _rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
  4056. if ((pBufLen != NULL) && (*pBufLen == 0) && (pBuf == NULL)) {
  4057. rtw_get_phy_file_path(Adapter, pFileName);
  4058. if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) {
  4059. rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
  4060. if (rlen > 0) {
  4061. rtStatus = _SUCCESS;
  4062. pBuf = rtw_zvmalloc(rlen);
  4063. if (pBuf) {
  4064. _rtw_memcpy(pBuf, pHalData->para_file_buf, rlen);
  4065. *pBufLen = rlen;
  4066. switch (eRFPath) {
  4067. case RF_PATH_A:
  4068. pHalData->rf_radio_a = pBuf;
  4069. break;
  4070. case RF_PATH_B:
  4071. pHalData->rf_radio_b = pBuf;
  4072. break;
  4073. default:
  4074. RTW_INFO("Unknown RF path!! %d\r\n", eRFPath);
  4075. break;
  4076. }
  4077. } else
  4078. RTW_INFO("%s(): eRFPath=%d alloc fail !\n", __FUNCTION__, eRFPath);
  4079. }
  4080. }
  4081. } else {
  4082. if ((pBufLen != NULL) && (*pBufLen != 0) && (pBuf != NULL)) {
  4083. _rtw_memcpy(pHalData->para_file_buf, pBuf, *pBufLen);
  4084. rtStatus = _SUCCESS;
  4085. } else
  4086. RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__);
  4087. }
  4088. if (rtStatus == _SUCCESS) {
  4089. /* RTW_INFO("%s(): read %s successfully\n", __FUNCTION__, pFileName); */
  4090. ptmp = pHalData->para_file_buf;
  4091. for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
  4092. if (!IsCommentString(szLine)) {
  4093. /* Get 1st hex value as register offset. */
  4094. if (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) {
  4095. if (u4bRegOffset == 0xfe || u4bRegOffset == 0xffe) {
  4096. /* Deay specific ms. Only RF configuration require delay. */
  4097. #ifdef CONFIG_LONG_DELAY_ISSUE
  4098. rtw_msleep_os(50);
  4099. #else
  4100. rtw_mdelay_os(50);
  4101. #endif
  4102. } else if (u4bRegOffset == 0xfd) {
  4103. /* delay_ms(5); */
  4104. for (i = 0; i < 100; i++)
  4105. rtw_udelay_os(MAX_STALL_TIME);
  4106. } else if (u4bRegOffset == 0xfc) {
  4107. /* delay_ms(1); */
  4108. for (i = 0; i < 20; i++)
  4109. rtw_udelay_os(MAX_STALL_TIME);
  4110. } else if (u4bRegOffset == 0xfb)
  4111. rtw_udelay_os(50);
  4112. else if (u4bRegOffset == 0xfa)
  4113. rtw_udelay_os(5);
  4114. else if (u4bRegOffset == 0xf9)
  4115. rtw_udelay_os(1);
  4116. else if (u4bRegOffset == 0xffff)
  4117. break;
  4118. /* Get 2nd hex value as register value. */
  4119. szLine += u4bMove;
  4120. if (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) {
  4121. phy_set_rf_reg(Adapter, eRFPath, u4bRegOffset, bRFRegOffsetMask, u4bRegValue);
  4122. /* Temp add, for frequency lock, if no delay, that may cause */
  4123. /* frequency shift, ex: 2412MHz => 2417MHz */
  4124. /* If frequency shift, the following action may works. */
  4125. /* Fractional-N table in radio_a.txt */
  4126. /* 0x2a 0x00001 */ /* channel 1 */
  4127. /* 0x2b 0x00808 frequency divider. */
  4128. /* 0x2b 0x53333 */
  4129. /* 0x2c 0x0000c */
  4130. rtw_udelay_os(1);
  4131. }
  4132. }
  4133. }
  4134. }
  4135. } else
  4136. RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName);
  4137. return rtStatus;
  4138. }
  4139. VOID
  4140. initDeltaSwingIndexTables(
  4141. PADAPTER Adapter,
  4142. char *Band,
  4143. char *Path,
  4144. char *Sign,
  4145. char *Channel,
  4146. char *Rate,
  4147. char *Data
  4148. )
  4149. {
  4150. #define STR_EQUAL_5G(_band, _path, _sign, _rate, _chnl) \
  4151. ((strcmp(Band, _band) == 0) && (strcmp(Path, _path) == 0) && (strcmp(Sign, _sign) == 0) &&\
  4152. (strcmp(Rate, _rate) == 0) && (strcmp(Channel, _chnl) == 0)\
  4153. )
  4154. #define STR_EQUAL_2G(_band, _path, _sign, _rate) \
  4155. ((strcmp(Band, _band) == 0) && (strcmp(Path, _path) == 0) && (strcmp(Sign, _sign) == 0) &&\
  4156. (strcmp(Rate, _rate) == 0)\
  4157. )
  4158. #define STORE_SWING_TABLE(_array, _iteratedIdx) \
  4159. do { \
  4160. for (token = strsep(&Data, delim); token != NULL; token = strsep(&Data, delim)) {\
  4161. sscanf(token, "%d", &idx);\
  4162. _array[_iteratedIdx++] = (u8)idx;\
  4163. } } while (0)\
  4164. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
  4165. struct dm_struct *pDM_Odm = &pHalData->odmpriv;
  4166. struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
  4167. u32 j = 0;
  4168. char *token;
  4169. char delim[] = ",";
  4170. u32 idx = 0;
  4171. /* RTW_INFO("===>initDeltaSwingIndexTables(): Band: %s;\nPath: %s;\nSign: %s;\nChannel: %s;\nRate: %s;\n, Data: %s;\n", */
  4172. /* Band, Path, Sign, Channel, Rate, Data); */
  4173. if (STR_EQUAL_2G("2G", "A", "+", "CCK"))
  4174. STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_p, j);
  4175. else if (STR_EQUAL_2G("2G", "A", "-", "CCK"))
  4176. STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_n, j);
  4177. else if (STR_EQUAL_2G("2G", "B", "+", "CCK"))
  4178. STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_p, j);
  4179. else if (STR_EQUAL_2G("2G", "B", "-", "CCK"))
  4180. STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_n, j);
  4181. else if (STR_EQUAL_2G("2G", "A", "+", "ALL"))
  4182. STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2ga_p, j);
  4183. else if (STR_EQUAL_2G("2G", "A", "-", "ALL"))
  4184. STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2ga_n, j);
  4185. else if (STR_EQUAL_2G("2G", "B", "+", "ALL"))
  4186. STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2gb_p, j);
  4187. else if (STR_EQUAL_2G("2G", "B", "-", "ALL"))
  4188. STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2gb_n, j);
  4189. else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "0"))
  4190. STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_p[0], j);
  4191. else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "0"))
  4192. STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_n[0], j);
  4193. else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "0"))
  4194. STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_p[0], j);
  4195. else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "0"))
  4196. STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_n[0], j);
  4197. else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "1"))
  4198. STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_p[1], j);
  4199. else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "1"))
  4200. STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_n[1], j);
  4201. else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "1"))
  4202. STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_p[1], j);
  4203. else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "1"))
  4204. STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_n[1], j);
  4205. else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "2"))
  4206. STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_p[2], j);
  4207. else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "2"))
  4208. STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_n[2], j);
  4209. else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "2"))
  4210. STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_p[2], j);
  4211. else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "2"))
  4212. STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_n[2], j);
  4213. else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "3"))
  4214. STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_p[3], j);
  4215. else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "3"))
  4216. STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_n[3], j);
  4217. else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "3"))
  4218. STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_p[3], j);
  4219. else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "3"))
  4220. STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_n[3], j);
  4221. else
  4222. RTW_INFO("===>initDeltaSwingIndexTables(): The input is invalid!!\n");
  4223. }
  4224. int
  4225. PHY_ConfigRFWithTxPwrTrackParaFile(
  4226. IN PADAPTER Adapter,
  4227. IN char *pFileName
  4228. )
  4229. {
  4230. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
  4231. struct dm_struct *pDM_Odm = &pHalData->odmpriv;
  4232. struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
  4233. int rlen = 0, rtStatus = _FAIL;
  4234. char *szLine, *ptmp;
  4235. u32 i = 0, j = 0;
  4236. char c = 0;
  4237. if (!(Adapter->registrypriv.load_phy_file & LOAD_RF_TXPWR_TRACK_PARA_FILE))
  4238. return rtStatus;
  4239. _rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
  4240. if ((pHalData->rf_tx_pwr_track_len == 0) && (pHalData->rf_tx_pwr_track == NULL)) {
  4241. rtw_get_phy_file_path(Adapter, pFileName);
  4242. if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) {
  4243. rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
  4244. if (rlen > 0) {
  4245. rtStatus = _SUCCESS;
  4246. pHalData->rf_tx_pwr_track = rtw_zvmalloc(rlen);
  4247. if (pHalData->rf_tx_pwr_track) {
  4248. _rtw_memcpy(pHalData->rf_tx_pwr_track, pHalData->para_file_buf, rlen);
  4249. pHalData->rf_tx_pwr_track_len = rlen;
  4250. } else
  4251. RTW_INFO("%s rf_tx_pwr_track alloc fail !\n", __FUNCTION__);
  4252. }
  4253. }
  4254. } else {
  4255. if ((pHalData->rf_tx_pwr_track_len != 0) && (pHalData->rf_tx_pwr_track != NULL)) {
  4256. _rtw_memcpy(pHalData->para_file_buf, pHalData->rf_tx_pwr_track, pHalData->rf_tx_pwr_track_len);
  4257. rtStatus = _SUCCESS;
  4258. } else
  4259. RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__);
  4260. }
  4261. if (rtStatus == _SUCCESS) {
  4262. /* RTW_INFO("%s(): read %s successfully\n", __FUNCTION__, pFileName); */
  4263. ptmp = pHalData->para_file_buf;
  4264. for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
  4265. if (!IsCommentString(szLine)) {
  4266. char band[5] = "", path[5] = "", sign[5] = "";
  4267. char chnl[5] = "", rate[10] = "";
  4268. char data[300] = ""; /* 100 is too small */
  4269. if (strlen(szLine) < 10 || szLine[0] != '[')
  4270. continue;
  4271. strncpy(band, szLine + 1, 2);
  4272. strncpy(path, szLine + 5, 1);
  4273. strncpy(sign, szLine + 8, 1);
  4274. i = 10; /* szLine+10 */
  4275. if (!ParseQualifiedString(szLine, &i, rate, '[', ']')) {
  4276. /* RTW_INFO("Fail to parse rate!\n"); */
  4277. }
  4278. if (!ParseQualifiedString(szLine, &i, chnl, '[', ']')) {
  4279. /* RTW_INFO("Fail to parse channel group!\n"); */
  4280. }
  4281. while (szLine[i] != '{' && i < strlen(szLine))
  4282. i++;
  4283. if (!ParseQualifiedString(szLine, &i, data, '{', '}')) {
  4284. /* RTW_INFO("Fail to parse data!\n"); */
  4285. }
  4286. initDeltaSwingIndexTables(Adapter, band, path, sign, chnl, rate, data);
  4287. }
  4288. }
  4289. } else
  4290. RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName);
  4291. #if 0
  4292. for (i = 0; i < DELTA_SWINGIDX_SIZE; ++i) {
  4293. RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2ga_p[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2ga_p[i]);
  4294. RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2ga_n[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2ga_n[i]);
  4295. RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2gb_p[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2gb_p[i]);
  4296. RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2gb_n[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2gb_n[i]);
  4297. RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_p[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_p[i]);
  4298. RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_n[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_n[i]);
  4299. RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_p[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_p[i]);
  4300. RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_n[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_n[i]);
  4301. for (j = 0; j < 3; ++j) {
  4302. RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_5ga_p[%d][%d] = %d\n", j, i, pRFCalibrateInfo->delta_swing_table_idx_5ga_p[j][i]);
  4303. RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_5ga_n[%d][%d] = %d\n", j, i, pRFCalibrateInfo->delta_swing_table_idx_5ga_n[j][i]);
  4304. RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_5gb_p[%d][%d] = %d\n", j, i, pRFCalibrateInfo->delta_swing_table_idx_5gb_p[j][i]);
  4305. RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_5gb_n[%d][%d] = %d\n", j, i, pRFCalibrateInfo->delta_swing_table_idx_5gb_n[j][i]);
  4306. }
  4307. }
  4308. #endif
  4309. return rtStatus;
  4310. }
  4311. #ifdef CONFIG_TXPWR_LIMIT
  4312. #ifndef DBG_TXPWR_LMT_FILE_PARSE
  4313. #define DBG_TXPWR_LMT_FILE_PARSE 0
  4314. #endif
  4315. #define PARSE_RET_NO_HDL 0
  4316. #define PARSE_RET_SUCCESS 1
  4317. #define PARSE_RET_FAIL 2
  4318. /*
  4319. * @@Ver=2.0
  4320. * or
  4321. * @@DomainCode=0x28, Regulation=C6
  4322. * or
  4323. * @@CountryCode=GB, Regulation=C7
  4324. */
  4325. static u8 parse_reg_exc_config(_adapter *adapter, char *szLine)
  4326. {
  4327. #define VER_PREFIX "Ver="
  4328. #define DOMAIN_PREFIX "DomainCode=0x"
  4329. #define COUNTRY_PREFIX "CountryCode="
  4330. #define REG_PREFIX "Regulation="
  4331. const u8 ver_prefix_len = strlen(VER_PREFIX);
  4332. const u8 domain_prefix_len = strlen(DOMAIN_PREFIX);
  4333. const u8 country_prefix_len = strlen(COUNTRY_PREFIX);
  4334. const u8 reg_prefix_len = strlen(REG_PREFIX);
  4335. u32 i, i_val_s, i_val_e;
  4336. u32 j;
  4337. u8 domain = 0xFF;
  4338. char *country = NULL;
  4339. u8 parse_reg = 0;
  4340. if (szLine[0] != '@' || szLine[1] != '@')
  4341. return PARSE_RET_NO_HDL;
  4342. i = 2;
  4343. if (strncmp(szLine + i, VER_PREFIX, ver_prefix_len) == 0)
  4344. ; /* nothing to do */
  4345. else if (strncmp(szLine + i, DOMAIN_PREFIX, domain_prefix_len) == 0) {
  4346. /* get string after domain prefix to ',' */
  4347. i += domain_prefix_len;
  4348. i_val_s = i;
  4349. while (szLine[i] != ',') {
  4350. if (szLine[i] == '\0')
  4351. return PARSE_RET_FAIL;
  4352. i++;
  4353. }
  4354. i_val_e = i;
  4355. /* check if all hex */
  4356. for (j = i_val_s; j < i_val_e; j++)
  4357. if (IsHexDigit(szLine[j]) == _FALSE)
  4358. return PARSE_RET_FAIL;
  4359. /* get value from hex string */
  4360. if (sscanf(szLine + i_val_s, "%hhx", &domain) != 1)
  4361. return PARSE_RET_FAIL;
  4362. parse_reg = 1;
  4363. } else if (strncmp(szLine + i, COUNTRY_PREFIX, country_prefix_len) == 0) {
  4364. /* get string after country prefix to ',' */
  4365. i += country_prefix_len;
  4366. i_val_s = i;
  4367. while (szLine[i] != ',') {
  4368. if (szLine[i] == '\0')
  4369. return PARSE_RET_FAIL;
  4370. i++;
  4371. }
  4372. i_val_e = i;
  4373. if (i_val_e - i_val_s != 2)
  4374. return PARSE_RET_FAIL;
  4375. /* check if all alpha */
  4376. for (j = i_val_s; j < i_val_e; j++)
  4377. if (is_alpha(szLine[j]) == _FALSE)
  4378. return PARSE_RET_FAIL;
  4379. country = szLine + i_val_s;
  4380. parse_reg = 1;
  4381. } else
  4382. return PARSE_RET_FAIL;
  4383. if (parse_reg) {
  4384. /* move to 'R' */
  4385. while (szLine[i] != 'R') {
  4386. if (szLine[i] == '\0')
  4387. return PARSE_RET_FAIL;
  4388. i++;
  4389. }
  4390. /* check if matching regulation prefix */
  4391. if (strncmp(szLine + i, REG_PREFIX, reg_prefix_len) != 0)
  4392. return PARSE_RET_FAIL;
  4393. /* get string after regulation prefix ending with space */
  4394. i += reg_prefix_len;
  4395. i_val_s = i;
  4396. while (szLine[i] != ' ' && szLine[i] != '\t' && szLine[i] != '\0')
  4397. i++;
  4398. if (i == i_val_s)
  4399. return PARSE_RET_FAIL;
  4400. rtw_regd_exc_add_with_nlen(adapter_to_rfctl(adapter), country, domain, szLine + i_val_s, i - i_val_s);
  4401. }
  4402. return PARSE_RET_SUCCESS;
  4403. }
  4404. static int
  4405. phy_ParsePowerLimitTableFile(
  4406. PADAPTER Adapter,
  4407. char *buffer
  4408. )
  4409. {
  4410. #define LD_STAGE_EXC_MAPPING 0
  4411. #define LD_STAGE_TAB_DEFINE 1
  4412. #define LD_STAGE_TAB_START 2
  4413. #define LD_STAGE_COLUMN_DEFINE 3
  4414. #define LD_STAGE_CH_ROW 4
  4415. int rtStatus = _FAIL;
  4416. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
  4417. struct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter);
  4418. struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
  4419. u8 loadingStage = LD_STAGE_EXC_MAPPING;
  4420. u32 i = 0, forCnt = 0;
  4421. char *szLine, *ptmp;
  4422. char band[10], bandwidth[10], rateSection[10], ntx[10], colNumBuf[10];
  4423. char **regulation = NULL;
  4424. u8 colNum = 0;
  4425. if (Adapter->registrypriv.RegDecryptCustomFile == 1)
  4426. phy_DecryptBBPgParaFile(Adapter, buffer);
  4427. ptmp = buffer;
  4428. for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
  4429. if (isAllSpaceOrTab(szLine, sizeof(*szLine)))
  4430. continue;
  4431. if (IsCommentString(szLine))
  4432. continue;
  4433. if (loadingStage == LD_STAGE_EXC_MAPPING) {
  4434. if (szLine[0] == '#' || szLine[1] == '#') {
  4435. loadingStage = LD_STAGE_TAB_DEFINE;
  4436. if (DBG_TXPWR_LMT_FILE_PARSE)
  4437. dump_regd_exc_list(RTW_DBGDUMP, adapter_to_rfctl(Adapter));
  4438. } else {
  4439. if (parse_reg_exc_config(Adapter, szLine) == PARSE_RET_FAIL) {
  4440. RTW_ERR("Fail to parse regulation exception ruls!\n");
  4441. goto exit;
  4442. }
  4443. continue;
  4444. }
  4445. }
  4446. if (loadingStage == LD_STAGE_TAB_DEFINE) {
  4447. /* read "## 2.4G, 20M, 1T, CCK" */
  4448. if (szLine[0] != '#' || szLine[1] != '#')
  4449. continue;
  4450. /* skip the space */
  4451. i = 2;
  4452. while (szLine[i] == ' ' || szLine[i] == '\t')
  4453. ++i;
  4454. szLine[--i] = ' '; /* return the space in front of the regulation info */
  4455. /* Parse the label of the table */
  4456. _rtw_memset((PVOID) band, 0, 10);
  4457. _rtw_memset((PVOID) bandwidth, 0, 10);
  4458. _rtw_memset((PVOID) ntx, 0, 10);
  4459. _rtw_memset((PVOID) rateSection, 0, 10);
  4460. if (!ParseQualifiedString(szLine, &i, band, ' ', ',')) {
  4461. RTW_ERR("Fail to parse band!\n");
  4462. goto exit;
  4463. }
  4464. if (!ParseQualifiedString(szLine, &i, bandwidth, ' ', ',')) {
  4465. RTW_ERR("Fail to parse bandwidth!\n");
  4466. goto exit;
  4467. }
  4468. if (!ParseQualifiedString(szLine, &i, ntx, ' ', ',')) {
  4469. RTW_ERR("Fail to parse ntx!\n");
  4470. goto exit;
  4471. }
  4472. if (!ParseQualifiedString(szLine, &i, rateSection, ' ', ',')) {
  4473. RTW_ERR("Fail to parse rate!\n");
  4474. goto exit;
  4475. }
  4476. loadingStage = LD_STAGE_TAB_START;
  4477. } else if (loadingStage == LD_STAGE_TAB_START) {
  4478. /* read "## START" */
  4479. if (szLine[0] != '#' || szLine[1] != '#')
  4480. continue;
  4481. /* skip the space */
  4482. i = 2;
  4483. while (szLine[i] == ' ' || szLine[i] == '\t')
  4484. ++i;
  4485. if (!eqNByte((u8 *)(szLine + i), (u8 *)("START"), 5)) {
  4486. RTW_ERR("Missing \"## START\" label\n");
  4487. goto exit;
  4488. }
  4489. loadingStage = LD_STAGE_COLUMN_DEFINE;
  4490. } else if (loadingStage == LD_STAGE_COLUMN_DEFINE) {
  4491. /* read "## #5# FCC ETSI MKK IC KCC" */
  4492. if (szLine[0] != '#' || szLine[1] != '#')
  4493. continue;
  4494. /* skip the space */
  4495. i = 2;
  4496. while (szLine[i] == ' ' || szLine[i] == '\t')
  4497. ++i;
  4498. _rtw_memset((PVOID) colNumBuf, 0, 10);
  4499. if (!ParseQualifiedString(szLine, &i, colNumBuf, '#', '#')) {
  4500. RTW_ERR("Fail to parse column number!\n");
  4501. goto exit;
  4502. }
  4503. if (!GetU1ByteIntegerFromStringInDecimal(colNumBuf, &colNum)) {
  4504. RTW_ERR("Column number \"%s\" is not unsigned decimal\n", colNumBuf);
  4505. goto exit;
  4506. }
  4507. if (colNum == 0) {
  4508. RTW_ERR("Column number is 0\n");
  4509. goto exit;
  4510. }
  4511. if (DBG_TXPWR_LMT_FILE_PARSE)
  4512. RTW_PRINT("[%s][%s][%s][%s] column num:%d\n", band, bandwidth, rateSection, ntx, colNum);
  4513. regulation = (char **)rtw_zmalloc(sizeof(char *) * colNum);
  4514. if (!regulation) {
  4515. RTW_ERR("Regulation alloc fail\n");
  4516. goto exit;
  4517. }
  4518. for (forCnt = 0; forCnt < colNum; ++forCnt) {
  4519. u32 i_ns;
  4520. /* skip the space */
  4521. while (szLine[i] == ' ' || szLine[i] == '\t')
  4522. i++;
  4523. i_ns = i;
  4524. while (szLine[i] != ' ' && szLine[i] != '\t' && szLine[i] != '\0')
  4525. i++;
  4526. regulation[forCnt] = (char *)rtw_malloc(i - i_ns + 1);
  4527. if (!regulation[forCnt]) {
  4528. RTW_ERR("Regulation alloc fail\n");
  4529. goto exit;
  4530. }
  4531. _rtw_memcpy(regulation[forCnt], szLine + i_ns, i - i_ns);
  4532. regulation[forCnt][i - i_ns] = '\0';
  4533. }
  4534. if (DBG_TXPWR_LMT_FILE_PARSE) {
  4535. RTW_PRINT("column name:");
  4536. for (forCnt = 0; forCnt < colNum; ++forCnt)
  4537. _RTW_PRINT(" %s", regulation[forCnt]);
  4538. _RTW_PRINT("\n");
  4539. }
  4540. loadingStage = LD_STAGE_CH_ROW;
  4541. } else if (loadingStage == LD_STAGE_CH_ROW) {
  4542. char channel[10] = {0}, powerLimit[10] = {0};
  4543. u8 cnt = 0;
  4544. /* the table ends */
  4545. if (szLine[0] == '#' && szLine[1] == '#') {
  4546. i = 2;
  4547. while (szLine[i] == ' ' || szLine[i] == '\t')
  4548. ++i;
  4549. if (eqNByte((u8 *)(szLine + i), (u8 *)("END"), 3)) {
  4550. loadingStage = LD_STAGE_TAB_DEFINE;
  4551. if (regulation) {
  4552. for (forCnt = 0; forCnt < colNum; ++forCnt) {
  4553. if (regulation[forCnt]) {
  4554. rtw_mfree(regulation[forCnt], strlen(regulation[forCnt]) + 1);
  4555. regulation[forCnt] = NULL;
  4556. }
  4557. }
  4558. rtw_mfree((u8 *)regulation, sizeof(char *) * colNum);
  4559. regulation = NULL;
  4560. }
  4561. colNum = 0;
  4562. continue;
  4563. } else {
  4564. RTW_ERR("Missing \"## END\" label\n");
  4565. goto exit;
  4566. }
  4567. }
  4568. if ((szLine[0] != 'c' && szLine[0] != 'C') ||
  4569. (szLine[1] != 'h' && szLine[1] != 'H')
  4570. ) {
  4571. RTW_WARN("Wrong channel prefix: '%c','%c'(%d,%d)\n", szLine[0], szLine[1], szLine[0], szLine[1]);
  4572. continue;
  4573. }
  4574. i = 2;/* move to the location behind 'h' */
  4575. /* load the channel number */
  4576. cnt = 0;
  4577. while (szLine[i] >= '0' && szLine[i] <= '9') {
  4578. channel[cnt] = szLine[i];
  4579. ++cnt;
  4580. ++i;
  4581. }
  4582. /* RTW_INFO("chnl %s!\n", channel); */
  4583. for (forCnt = 0; forCnt < colNum; ++forCnt) {
  4584. /* skip the space between channel number and the power limit value */
  4585. while (szLine[i] == ' ' || szLine[i] == '\t')
  4586. ++i;
  4587. /* load the power limit value */
  4588. _rtw_memset((PVOID) powerLimit, 0, 10);
  4589. if (szLine[i] == 'W' && szLine[i + 1] == 'W') {
  4590. /*
  4591. * case "WW" assign special ww value
  4592. * means to get minimal limit in other regulations at same channel
  4593. */
  4594. s8 ww_value = phy_txpwr_ww_lmt_value(Adapter);
  4595. sprintf(powerLimit, "%d", ww_value);
  4596. i += 2;
  4597. } else if (szLine[i] == 'N' && szLine[i + 1] == 'A') {
  4598. /*
  4599. * case "NA" assign max txgi value
  4600. * means no limitation
  4601. */
  4602. sprintf(powerLimit, "%d", hal_spec->txgi_max);
  4603. i += 2;
  4604. } else if ((szLine[i] >= '0' && szLine[i] <= '9') || szLine[i] == '.'
  4605. || szLine[i] == '+' || szLine[i] == '-'
  4606. ){
  4607. /* case of dBm value */
  4608. u8 integer = 0, fraction = 0, negative = 0;
  4609. u32 u4bMove;
  4610. s8 lmt = 0;
  4611. if (szLine[i] == '+' || szLine[i] == '-') {
  4612. if (szLine[i] == '-')
  4613. negative = 1;
  4614. i++;
  4615. }
  4616. if (GetFractionValueFromString(&szLine[i], &integer, &fraction, &u4bMove))
  4617. i += u4bMove;
  4618. else {
  4619. RTW_ERR("Limit \"%s\" is not valid decimal\n", &szLine[i]);
  4620. goto exit;
  4621. }
  4622. /* transform to string of value in unit of txgi */
  4623. lmt = integer * hal_spec->txgi_pdbm + ((u16)fraction * (u16)hal_spec->txgi_pdbm) / 100;
  4624. if (negative)
  4625. lmt = -lmt;
  4626. sprintf(powerLimit, "%d", lmt);
  4627. } else {
  4628. RTW_ERR("Wrong limit expression \"%c%c\"(%d, %d)\n"
  4629. , szLine[i], szLine[i + 1], szLine[i], szLine[i + 1]);
  4630. goto exit;
  4631. }
  4632. /* store the power limit value */
  4633. phy_set_tx_power_limit(pDM_Odm, (u8 *)regulation[forCnt], (u8 *)band,
  4634. (u8 *)bandwidth, (u8 *)rateSection, (u8 *)ntx, (u8 *)channel, (u8 *)powerLimit);
  4635. }
  4636. }
  4637. }
  4638. rtStatus = _SUCCESS;
  4639. exit:
  4640. if (regulation) {
  4641. for (forCnt = 0; forCnt < colNum; ++forCnt) {
  4642. if (regulation[forCnt]) {
  4643. rtw_mfree(regulation[forCnt], strlen(regulation[forCnt]) + 1);
  4644. regulation[forCnt] = NULL;
  4645. }
  4646. }
  4647. rtw_mfree((u8 *)regulation, sizeof(char *) * colNum);
  4648. regulation = NULL;
  4649. }
  4650. RTW_INFO("%s return %d\n", __func__, rtStatus);
  4651. return rtStatus;
  4652. }
  4653. int
  4654. PHY_ConfigRFWithPowerLimitTableParaFile(
  4655. IN PADAPTER Adapter,
  4656. IN const char *pFileName
  4657. )
  4658. {
  4659. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
  4660. int rlen = 0, rtStatus = _FAIL;
  4661. if (!(Adapter->registrypriv.load_phy_file & LOAD_RF_TXPWR_LMT_PARA_FILE))
  4662. return rtStatus;
  4663. _rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
  4664. if (pHalData->rf_tx_pwr_lmt == NULL) {
  4665. rtw_get_phy_file_path(Adapter, pFileName);
  4666. if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) {
  4667. rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
  4668. if (rlen > 0) {
  4669. rtStatus = _SUCCESS;
  4670. pHalData->rf_tx_pwr_lmt = rtw_zvmalloc(rlen);
  4671. if (pHalData->rf_tx_pwr_lmt) {
  4672. _rtw_memcpy(pHalData->rf_tx_pwr_lmt, pHalData->para_file_buf, rlen);
  4673. pHalData->rf_tx_pwr_lmt_len = rlen;
  4674. } else
  4675. RTW_INFO("%s rf_tx_pwr_lmt alloc fail !\n", __FUNCTION__);
  4676. }
  4677. }
  4678. } else {
  4679. if ((pHalData->rf_tx_pwr_lmt_len != 0) && (pHalData->rf_tx_pwr_lmt != NULL)) {
  4680. _rtw_memcpy(pHalData->para_file_buf, pHalData->rf_tx_pwr_lmt, pHalData->rf_tx_pwr_lmt_len);
  4681. rtStatus = _SUCCESS;
  4682. } else
  4683. RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__);
  4684. }
  4685. if (rtStatus == _SUCCESS) {
  4686. /* RTW_INFO("%s(): read %s ok\n", __FUNCTION__, pFileName); */
  4687. rtStatus = phy_ParsePowerLimitTableFile(Adapter, pHalData->para_file_buf);
  4688. } else
  4689. RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName);
  4690. return rtStatus;
  4691. }
  4692. #endif /* CONFIG_TXPWR_LIMIT */
  4693. void phy_free_filebuf_mask(_adapter *padapter, u8 mask)
  4694. {
  4695. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
  4696. if (pHalData->mac_reg && (mask & LOAD_MAC_PARA_FILE)) {
  4697. rtw_vmfree(pHalData->mac_reg, pHalData->mac_reg_len);
  4698. pHalData->mac_reg = NULL;
  4699. }
  4700. if (mask & LOAD_BB_PARA_FILE) {
  4701. if (pHalData->bb_phy_reg) {
  4702. rtw_vmfree(pHalData->bb_phy_reg, pHalData->bb_phy_reg_len);
  4703. pHalData->bb_phy_reg = NULL;
  4704. }
  4705. if (pHalData->bb_agc_tab) {
  4706. rtw_vmfree(pHalData->bb_agc_tab, pHalData->bb_agc_tab_len);
  4707. pHalData->bb_agc_tab = NULL;
  4708. }
  4709. }
  4710. if (pHalData->bb_phy_reg_pg && (mask & LOAD_BB_PG_PARA_FILE)) {
  4711. rtw_vmfree(pHalData->bb_phy_reg_pg, pHalData->bb_phy_reg_pg_len);
  4712. pHalData->bb_phy_reg_pg = NULL;
  4713. }
  4714. if (pHalData->bb_phy_reg_mp && (mask & LOAD_BB_MP_PARA_FILE)) {
  4715. rtw_vmfree(pHalData->bb_phy_reg_mp, pHalData->bb_phy_reg_mp_len);
  4716. pHalData->bb_phy_reg_mp = NULL;
  4717. }
  4718. if (mask & LOAD_RF_PARA_FILE) {
  4719. if (pHalData->rf_radio_a) {
  4720. rtw_vmfree(pHalData->rf_radio_a, pHalData->rf_radio_a_len);
  4721. pHalData->rf_radio_a = NULL;
  4722. }
  4723. if (pHalData->rf_radio_b) {
  4724. rtw_vmfree(pHalData->rf_radio_b, pHalData->rf_radio_b_len);
  4725. pHalData->rf_radio_b = NULL;
  4726. }
  4727. }
  4728. if (pHalData->rf_tx_pwr_track && (mask & LOAD_RF_TXPWR_TRACK_PARA_FILE)) {
  4729. rtw_vmfree(pHalData->rf_tx_pwr_track, pHalData->rf_tx_pwr_track_len);
  4730. pHalData->rf_tx_pwr_track = NULL;
  4731. }
  4732. if (pHalData->rf_tx_pwr_lmt && (mask & LOAD_RF_TXPWR_LMT_PARA_FILE)) {
  4733. rtw_vmfree(pHalData->rf_tx_pwr_lmt, pHalData->rf_tx_pwr_lmt_len);
  4734. pHalData->rf_tx_pwr_lmt = NULL;
  4735. }
  4736. }
  4737. inline void phy_free_filebuf(_adapter *padapter)
  4738. {
  4739. phy_free_filebuf_mask(padapter, 0xFF);
  4740. }
  4741. #endif