Hal8188EPhyCfg.h 6.8 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. *
  19. ******************************************************************************/
  20. #ifndef __INC_HAL8188EPHYCFG_H__
  21. #define __INC_HAL8188EPHYCFG_H__
  22. /*--------------------------Define Parameters-------------------------------*/
  23. #define LOOP_LIMIT 5
  24. #define MAX_STALL_TIME 50 /* us */
  25. #define AntennaDiversityValue 0x80 /* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
  26. #define MAX_TXPWR_IDX_NMODE_92S 63
  27. #define Reset_Cnt_Limit 3
  28. #ifdef CONFIG_PCI_HCI
  29. #define MAX_AGGR_NUM 0x0B
  30. #else
  31. #define MAX_AGGR_NUM 0x07
  32. #endif /* CONFIG_PCI_HCI */
  33. /*--------------------------Define Parameters-------------------------------*/
  34. /*------------------------------Define structure----------------------------*/
  35. #define MAX_TX_COUNT_8188E 1
  36. /* BB/RF related */
  37. /*------------------------------Define structure----------------------------*/
  38. /*------------------------Export global variable----------------------------*/
  39. /*------------------------Export global variable----------------------------*/
  40. /*------------------------Export Marco Definition---------------------------*/
  41. /*------------------------Export Marco Definition---------------------------*/
  42. /*--------------------------Exported Function prototype---------------------*/
  43. /*
  44. * BB and RF register read/write
  45. * */
  46. u32 PHY_QueryBBReg8188E(IN PADAPTER Adapter,
  47. IN u32 RegAddr,
  48. IN u32 BitMask);
  49. void PHY_SetBBReg8188E(IN PADAPTER Adapter,
  50. IN u32 RegAddr,
  51. IN u32 BitMask,
  52. IN u32 Data);
  53. u32 PHY_QueryRFReg8188E(IN PADAPTER Adapter,
  54. IN u8 eRFPath,
  55. IN u32 RegAddr,
  56. IN u32 BitMask);
  57. void PHY_SetRFReg8188E(IN PADAPTER Adapter,
  58. IN u8 eRFPath,
  59. IN u32 RegAddr,
  60. IN u32 BitMask,
  61. IN u32 Data);
  62. /*
  63. * Initialization related function
  64. */
  65. /* MAC/BB/RF HAL config */
  66. int PHY_MACConfig8188E(IN PADAPTER Adapter);
  67. int PHY_BBConfig8188E(IN PADAPTER Adapter);
  68. int PHY_RFConfig8188E(IN PADAPTER Adapter);
  69. /* RF config */
  70. int rtl8188e_PHY_ConfigRFWithParaFile(IN PADAPTER Adapter, IN u8 *pFileName, u8 eRFPath);
  71. /*
  72. * RF Power setting
  73. */
  74. /* extern BOOLEAN PHY_SetRFPowerState(IN PADAPTER Adapter,
  75. * IN RT_RF_POWER_STATE eRFPowerState); */
  76. /*
  77. * BB TX Power R/W
  78. * */
  79. void PHY_GetTxPowerLevel8188E(IN PADAPTER Adapter,
  80. OUT s32 *powerlevel);
  81. void PHY_SetTxPowerLevel8188E(IN PADAPTER Adapter,
  82. IN u8 channel);
  83. BOOLEAN PHY_UpdateTxPowerDbm8188E(IN PADAPTER Adapter,
  84. IN int powerInDbm);
  85. VOID
  86. PHY_SetTxPowerIndex_8188E(
  87. IN PADAPTER Adapter,
  88. IN u32 PowerIndex,
  89. IN u8 RFPath,
  90. IN u8 Rate
  91. );
  92. u8
  93. PHY_GetTxPowerIndex_8188E(
  94. IN PADAPTER pAdapter,
  95. IN u8 RFPath,
  96. IN u8 Rate,
  97. IN u8 BandWidth,
  98. IN u8 Channel,
  99. struct txpwr_idx_comp *tic
  100. );
  101. /*
  102. * Switch bandwidth for 8192S
  103. */
  104. /* extern void PHY_SetBWModeCallback8192C( IN PRT_TIMER pTimer ); */
  105. void PHY_SetBWMode8188E(IN PADAPTER pAdapter,
  106. IN CHANNEL_WIDTH ChnlWidth,
  107. IN unsigned char Offset);
  108. /*
  109. * Set FW CMD IO for 8192S.
  110. */
  111. /* extern BOOLEAN HalSetIO8192C( IN PADAPTER Adapter,
  112. * IN IO_TYPE IOType); */
  113. /*
  114. * Set A2 entry to fw for 8192S
  115. * */
  116. extern void FillA2Entry8192C(IN PADAPTER Adapter,
  117. IN u8 index,
  118. IN u8 *val);
  119. /*
  120. * channel switch related funciton
  121. */
  122. /* extern void PHY_SwChnlCallback8192C( IN PRT_TIMER pTimer ); */
  123. void PHY_SwChnl8188E(IN PADAPTER pAdapter,
  124. IN u8 channel);
  125. VOID
  126. PHY_SetSwChnlBWMode8188E(
  127. IN PADAPTER Adapter,
  128. IN u8 channel,
  129. IN CHANNEL_WIDTH Bandwidth,
  130. IN u8 Offset40,
  131. IN u8 Offset80
  132. );
  133. VOID
  134. PHY_SetRFEReg_8188E(
  135. IN PADAPTER Adapter
  136. );
  137. /*
  138. * BB/MAC/RF other monitor API
  139. * */
  140. VOID phy_set_rf_path_switch_8188e(IN PADAPTER pAdapter, IN bool bMain);
  141. extern VOID
  142. PHY_SwitchEphyParameter(
  143. IN PADAPTER Adapter
  144. );
  145. extern VOID
  146. PHY_EnableHostClkReq(
  147. IN PADAPTER Adapter
  148. );
  149. BOOLEAN
  150. SetAntennaConfig92C(
  151. IN PADAPTER Adapter,
  152. IN u8 DefaultAnt
  153. );
  154. /*--------------------------Exported Function prototype---------------------*/
  155. /*
  156. * Initialization related function
  157. *
  158. * MAC/BB/RF HAL config */
  159. /* extern s32 PHY_MACConfig8723(PADAPTER padapter);
  160. * s32 PHY_BBConfig8723(PADAPTER padapter);
  161. * s32 PHY_RFConfig8723(PADAPTER padapter); */
  162. /* ******************************************************************
  163. * Note: If SIC_ENABLE under PCIE, because of the slow operation
  164. * you should
  165. * 2) "#define RTL8723_FPGA_VERIFICATION 1" in Precomp.h.WlanE.Windows
  166. * 3) "#define RTL8190_Download_Firmware_From_Header 0" in Precomp.h.WlanE.Windows if needed.
  167. * */
  168. #if (RTL8188E_SUPPORT == 1) && (RTL8188E_FPGA_TRUE_PHY_VERIFICATION == 1)
  169. #define SIC_ENABLE 1
  170. #define SIC_HW_SUPPORT 1
  171. #else
  172. #define SIC_ENABLE 0
  173. #define SIC_HW_SUPPORT 0
  174. #endif
  175. /* ****************************************************************** */
  176. #define SIC_MAX_POLL_CNT 5
  177. #if (SIC_HW_SUPPORT == 1)
  178. #define SIC_CMD_READY 0
  179. #define SIC_CMD_PREWRITE 0x1
  180. #if (RTL8188E_SUPPORT == 1)
  181. #define SIC_CMD_WRITE 0x40
  182. #define SIC_CMD_PREREAD 0x2
  183. #define SIC_CMD_READ 0x80
  184. #define SIC_CMD_INIT 0xf0
  185. #define SIC_INIT_VAL 0xff
  186. #define SIC_INIT_REG 0x1b7
  187. #define SIC_CMD_REG 0x1EB /* 1byte */
  188. #define SIC_ADDR_REG 0x1E8 /* 1b4~1b5, 2 bytes */
  189. #define SIC_DATA_REG 0x1EC /* 1b0~1b3 */
  190. #else
  191. #define SIC_CMD_WRITE 0x11
  192. #define SIC_CMD_PREREAD 0x2
  193. #define SIC_CMD_READ 0x12
  194. #define SIC_CMD_INIT 0x1f
  195. #define SIC_INIT_VAL 0xff
  196. #define SIC_INIT_REG 0x1b7
  197. #define SIC_CMD_REG 0x1b6 /* 1byte */
  198. #define SIC_ADDR_REG 0x1b4 /* 1b4~1b5, 2 bytes */
  199. #define SIC_DATA_REG 0x1b0 /* 1b0~1b3 */
  200. #endif
  201. #else
  202. #define SIC_CMD_READY 0
  203. #define SIC_CMD_WRITE 1
  204. #define SIC_CMD_READ 2
  205. #if (RTL8188E_SUPPORT == 1)
  206. #define SIC_CMD_REG 0x1EB /* 1byte */
  207. #define SIC_ADDR_REG 0x1E8 /* 1b9~1ba, 2 bytes */
  208. #define SIC_DATA_REG 0x1EC /* 1bc~1bf */
  209. #else
  210. #define SIC_CMD_REG 0x1b8 /* 1byte */
  211. #define SIC_ADDR_REG 0x1b9 /* 1b9~1ba, 2 bytes */
  212. #define SIC_DATA_REG 0x1bc /* 1bc~1bf */
  213. #endif
  214. #endif
  215. #if (SIC_ENABLE == 1)
  216. VOID SIC_Init(IN PADAPTER Adapter);
  217. #endif
  218. #endif /* __INC_HAL8192CPHYCFG_H */