HalPwrSeqCmd.h 4.3 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. *
  19. ******************************************************************************/
  20. #ifndef __HALPWRSEQCMD_H__
  21. #define __HALPWRSEQCMD_H__
  22. #include <drv_types.h>
  23. /*---------------------------------------------*/
  24. /* 3 The value of cmd: 4 bits
  25. *---------------------------------------------*/
  26. #define PWR_CMD_READ 0x00
  27. /* offset: the read register offset
  28. * msk: the mask of the read value
  29. * value: N/A, left by 0
  30. * note: dirver shall implement this function by read & msk */
  31. #define PWR_CMD_WRITE 0x01
  32. /* offset: the read register offset
  33. * msk: the mask of the write bits
  34. * value: write value
  35. * note: driver shall implement this cmd by read & msk after write */
  36. #define PWR_CMD_POLLING 0x02
  37. /* offset: the read register offset
  38. * msk: the mask of the polled value
  39. * value: the value to be polled, masked by the msd field.
  40. * note: driver shall implement this cmd by
  41. * do {
  42. * if( (Read(offset) & msk) == (value & msk) )
  43. * break;
  44. * } while(not timeout); */
  45. #define PWR_CMD_DELAY 0x03
  46. /* offset: the value to delay
  47. * msk: N/A
  48. * value: the unit of delay, 0: us, 1: ms */
  49. #define PWR_CMD_END 0x04
  50. /* offset: N/A
  51. * msk: N/A
  52. * value: N/A */
  53. /*---------------------------------------------*/
  54. /* 3 The value of base: 4 bits
  55. *---------------------------------------------
  56. * define the base address of each block */
  57. #define PWR_BASEADDR_MAC 0x00
  58. #define PWR_BASEADDR_USB 0x01
  59. #define PWR_BASEADDR_PCIE 0x02
  60. #define PWR_BASEADDR_SDIO 0x03
  61. /*---------------------------------------------*/
  62. /* 3 The value of interface_msk: 4 bits
  63. *---------------------------------------------*/
  64. #define PWR_INTF_SDIO_MSK BIT(0)
  65. #define PWR_INTF_USB_MSK BIT(1)
  66. #define PWR_INTF_PCI_MSK BIT(2)
  67. #define PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
  68. /*---------------------------------------------*/
  69. /* 3 The value of fab_msk: 4 bits
  70. *---------------------------------------------*/
  71. #define PWR_FAB_TSMC_MSK BIT(0)
  72. #define PWR_FAB_UMC_MSK BIT(1)
  73. #define PWR_FAB_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
  74. /*---------------------------------------------*/
  75. /* 3 The value of cut_msk: 8 bits
  76. *---------------------------------------------*/
  77. #define PWR_CUT_TESTCHIP_MSK BIT(0)
  78. #define PWR_CUT_A_MSK BIT(1)
  79. #define PWR_CUT_B_MSK BIT(2)
  80. #define PWR_CUT_C_MSK BIT(3)
  81. #define PWR_CUT_D_MSK BIT(4)
  82. #define PWR_CUT_E_MSK BIT(5)
  83. #define PWR_CUT_F_MSK BIT(6)
  84. #define PWR_CUT_G_MSK BIT(7)
  85. #define PWR_CUT_ALL_MSK 0xFF
  86. typedef enum _PWRSEQ_CMD_DELAY_UNIT_ {
  87. PWRSEQ_DELAY_US,
  88. PWRSEQ_DELAY_MS,
  89. } PWRSEQ_DELAY_UNIT;
  90. typedef struct _WL_PWR_CFG_ {
  91. u16 offset;
  92. u8 cut_msk;
  93. u8 fab_msk:4;
  94. u8 interface_msk:4;
  95. u8 base:4;
  96. u8 cmd:4;
  97. u8 msk;
  98. u8 value;
  99. } WLAN_PWR_CFG, *PWLAN_PWR_CFG;
  100. #define GET_PWR_CFG_OFFSET(__PWR_CMD) ((__PWR_CMD).offset)
  101. #define GET_PWR_CFG_CUT_MASK(__PWR_CMD) ((__PWR_CMD).cut_msk)
  102. #define GET_PWR_CFG_FAB_MASK(__PWR_CMD) ((__PWR_CMD).fab_msk)
  103. #define GET_PWR_CFG_INTF_MASK(__PWR_CMD) ((__PWR_CMD).interface_msk)
  104. #define GET_PWR_CFG_BASE(__PWR_CMD) ((__PWR_CMD).base)
  105. #define GET_PWR_CFG_CMD(__PWR_CMD) ((__PWR_CMD).cmd)
  106. #define GET_PWR_CFG_MASK(__PWR_CMD) ((__PWR_CMD).msk)
  107. #define GET_PWR_CFG_VALUE(__PWR_CMD) ((__PWR_CMD).value)
  108. /* ********************************************************************************
  109. * Prototype of protected function.
  110. * ******************************************************************************** */
  111. u8 HalPwrSeqCmdParsing(
  112. PADAPTER padapter,
  113. u8 CutVersion,
  114. u8 FabVersion,
  115. u8 InterfaceType,
  116. WLAN_PWR_CFG PwrCfgCmd[]);
  117. #endif