rtl8821ce/hal/halmac/halmac_reg_8814b.h

/******************************************************************************
 *
 * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
 * more details.
 *
 ******************************************************************************/

#ifndef __INC_HALMAC_REG_8814B_H
#define __INC_HALMAC_REG_8814B_H

#define REG_SYS_ISO_CTRL_8814B 0x0000
#define REG_SYS_FUNC_EN_8814B 0x0002
#define REG_SYS_PW_CTRL_8814B 0x0004
#define REG_SYS_CLK_CTRL_8814B 0x0008
#define REG_SYS_EEPROM_CTRL_8814B 0x000A
#define REG_EE_VPD_8814B 0x000C
#define REG_SYS_SWR_CTRL1_8814B 0x0010
#define REG_SYS_SWR_CTRL2_8814B 0x0014
#define REG_SYS_SWR_CTRL3_8814B 0x0018
#define REG_RSV_CTRL_8814B 0x001C
#define REG_RF_CTRL_8814B 0x001F
#define REG_AFE_LDO_CTRL_8814B 0x0020
#define REG_AFE_CTRL1_8814B 0x0024
#define REG_ANAPARSW_POW_MAC_8814B 0x0028
#define REG_ANAPARLDO_POW_MAC_8814B 0x0029
#define REG_ANAPAR_POW_MAC_8814B 0x002A
#define REG_ANAPAR_POW_XTAL_8814B 0x002B
#define REG_ANAPARLDO_MAC_8814B 0x002C
#define REG_EFUSE_CTRL_8814B 0x0030
#define REG_LDO_EFUSE_CTRL_8814B 0x0034
#define REG_PWR_OPTION_CTRL_8814B 0x0038
#define REG_CAL_TIMER_8814B 0x003C
#define REG_ACLK_MON_8814B 0x003E
#define REG_GPIO_MUXCFG_8814B 0x0040
#define REG_GPIO_PIN_CTRL_8814B 0x0044
#define REG_GPIO_INTM_8814B 0x0048
#define REG_LED_CFG_8814B 0x004C
#define REG_FSIMR_8814B 0x0050
#define REG_FSISR_8814B 0x0054
#define REG_HSIMR_8814B 0x0058
#define REG_HSISR_8814B 0x005C
#define REG_GPIO_EXT_CTRL_8814B 0x0060
#define REG_PAD_CTRL1_8814B 0x0064
#define REG_WL_BT_PWR_CTRL_8814B 0x0068
#define REG_SDM_DEBUG_8814B 0x006C
#define REG_SYS_SDIO_CTRL_8814B 0x0070
#define REG_HCI_OPT_CTRL_8814B 0x0074
#define REG_AFE_CTRL4_8814B 0x0078
#define REG_LDO_SWR_CTRL_8814B 0x007C
#define REG_MCUFW_CTRL_8814B 0x0080
#define REG_MCU_TST_CFG_8814B 0x0084
#define REG_HMEBOX_E0_E1_8814B 0x0088
#define REG_HMEBOX_E2_E3_8814B 0x008C
#define REG_WLLPS_CTRL_8814B 0x0090
#define REG_AFE_CTRL5_8814B 0x0094
#define REG_GPIO_DEBOUNCE_CTRL_8814B 0x0098
#define REG_RPWM2_8814B 0x009C
#define REG_SYSON_FSM_MON_8814B 0x00A0
#define REG_AFE_CTRL6_8814B 0x00A4
#define REG_PMC_DBG_CTRL1_8814B 0x00A8
#define REG_AFE_CTRL7_8814B 0x00AC
#define REG_HIMR0_8814B 0x00B0
#define REG_HISR0_8814B 0x00B4
#define REG_HIMR1_8814B 0x00B8
#define REG_HISR1_8814B 0x00BC
#define REG_DBG_PORT_SEL_8814B 0x00C0
#define REG_PAD_CTRL2_8814B 0x00C4
#define REG_PMC_DBG_CTRL2_8814B 0x00CC
#define REG_MEM_CTRL_8814B 0x00D8
#define REG_SYN_RFC_CTRL_8814B 0x00DC
#define REG_USB_SIE_INTF_8814B 0x00E0
#define REG_PCIE_MIO_INTF_8814B 0x00E4
#define REG_PCIE_MIO_INTD_8814B 0x00E8
#define REG_WLRF1_8814B 0x00EC
#define REG_SYS_CFG1_8814B 0x00F0
#define REG_SYS_STATUS1_8814B 0x00F4
#define REG_SYS_STATUS2_8814B 0x00F8
#define REG_SYS_CFG2_8814B 0x00FC
#define REG_ANAPARSW_MAC_0_8814B 0x1010
#define REG_ANAPARSW_MAC_1_8814B 0x1014
#define REG_ANAPAR_MAC_0_8814B 0x1018
#define REG_ANAPAR_MAC_1_8814B 0x101C
#define REG_ANAPAR_MAC_2_8814B 0x1020
#define REG_ANAPAR_MAC_3_8814B 0x1024
#define REG_ANAPAR_MAC_4_8814B 0x1028
#define REG_ANAPAR_MAC_5_8814B 0x102C
#define REG_ANAPAR_MAC_6_8814B 0x1030
#define REG_ANAPAR_MAC_7_8814B 0x1034
#define REG_ANAPAR_MAC_8_8814B 0x1038
#define REG_ANAPAR_XTAL_0_8814B 0x1040
#define REG_ANAPAR_XTAL_1_8814B 0x1044
#define REG_ANAPAR_XTAL_2_8814B 0x1048
#define REG_ANAPAR_XTAL_AAC_8814B 0x104C
#define REG_ANAPAR_XTAL_R_ONLY_8814B 0x1050
#define REG_CPHY_LDO_8814B 0x1054
#define REG_CPHY_BG_8814B 0x1058
#define REG_HIMR_4_8814B 0x1060
#define REG_HISR_4_8814B 0x1064
#define REG_HIMR_5_8814B 0x1068
#define REG_HISR_5_8814B 0x106C
#define REG_SYS_CFG5_8814B 0x1070
#define REG_HIMR_6_8814B 0x1078
#define REG_HISR_6_8814B 0x107C
#define REG_CPU_DMEM_CON_8814B 0x1080
#define REG_BOOT_REASON_8814B 0x1088
#define REG_DATA_CPU_CTL0_8814B 0x1090
#define REG_DATA_CPU_CTL1_8814B 0x1094
#define REG_TXDMA_STOP_HIMR_8814B 0x1098
#define REG_TXDMA_STOP_HISR_8814B 0x109C
#define REG_TXDMA_START_HIMR_8814B 0x10A0
#define REG_TXDMA_START_HISR_8814B 0x10A4
#define REG_NFCPAD_CTRL_8814B 0x10A8
#define REG_HIMR2_8814B 0x10B0
#define REG_HISR2_8814B 0x10B4
#define REG_HIMR3_8814B 0x10B8
#define REG_HISR3_8814B 0x10BC
#define REG_SW_MDIO_8814B 0x10C0
#define REG_HIMR_7_8814B 0x10C8
#define REG_HISR_7_8814B 0x10CC
#define REG_H2C_PKT_READADDR_8814B 0x10D0
#define REG_H2C_PKT_WRITEADDR_8814B 0x10D4
#define REG_MEM_PWR_CRTL_8814B 0x10D8
#define REG_FW_DRV_HANDSHAKE_8814B 0x10DC
#define REG_FW_DBG0_8814B 0x10E0
#define REG_FW_DBG1_8814B 0x10E4
#define REG_FW_DBG2_8814B 0x10E8
#define REG_FW_DBG3_8814B 0x10EC
#define REG_FW_DBG4_8814B 0x10F0
#define REG_FW_DBG5_8814B 0x10F4
#define REG_FW_DBG6_8814B 0x10F8
#define REG_FW_DBG7_8814B 0x10FC
#define REG_CR_8814B 0x0100
#define REG_PG_SIZE_8814B 0x0104
#define REG_PKT_BUFF_ACCESS_CTRL_8814B 0x0106
#define REG_TSF_CLK_STATE_8814B 0x0108
#define REG_TXDMA_PQ_MAP_8814B 0x010C
#define REG_TRXFF_BNDY_8814B 0x0114
#define REG_PTA_I2C_MBOX_8814B 0x0118
#define REG_RXFF_BNDY_8814B 0x011C
#define REG_FE1IMR_8814B 0x0120
#define REG_FE1ISR_8814B 0x0124
#define REG_CPWM_8814B 0x012C
#define REG_FWIMR_8814B 0x0130
#define REG_FWISR_8814B 0x0134
#define REG_FTIMR_8814B 0x0138
#define REG_FTISR_8814B 0x013C
#define REG_PKTBUF_DBG_CTRL_8814B 0x0140
#define REG_PKTBUF_DBG_DATA_L_8814B 0x0144
#define REG_PKTBUF_DBG_DATA_H_8814B 0x0148
#define REG_CPWM2_8814B 0x014C
#define REG_TC0_CTRL_8814B 0x0150
#define REG_TC1_CTRL_8814B 0x0154
#define REG_TC2_CTRL_8814B 0x0158
#define REG_TC3_CTRL_8814B 0x015C
#define REG_TC4_CTRL_8814B 0x0160
#define REG_TCUNIT_BASE_8814B 0x0164
#define REG_TC5_CTRL_8814B 0x0168
#define REG_TC6_CTRL_8814B 0x016C
#define REG_AES_DECRPT_DATA_8814B 0x0180
#define REG_AES_DECRPT_CFG_8814B 0x0184
#define REG_HIOE_CTRL_8814B 0x0188
#define REG_HIOE_CFG_FILE_8814B 0x018C
#define REG_TMETER_8814B 0x0190
#define REG_OSC_32K_CTRL_8814B 0x0194
#define REG_32K_CAL_REG1_8814B 0x0198
#define REG_C2HEVT_8814B 0x01A0
#define REG_C2HEVT_1_8814B 0x01A4
#define REG_C2HEVT_2_8814B 0x01A8
#define REG_C2HEVT_3_8814B 0x01AC
#define REG_RXDESC_BUFF_RPTR_8814B 0x01B0
#define REG_RXDESC_BUFF_WPTR_8814B 0x01B4
#define REG_SW_DEFINED_PAGE1_8814B 0x01B8
#define REG_SW_DEFINED_PAGE2_8814B 0x01BC
#define REG_MCUTST_I_8814B 0x01C0
#define REG_MCUTST_II_8814B 0x01C4
#define REG_FMETHR_8814B 0x01C8
#define REG_HMETFR_8814B 0x01CC
#define REG_HMEBOX0_8814B 0x01D0
#define REG_HMEBOX1_8814B 0x01D4
#define REG_HMEBOX2_8814B 0x01D8
#define REG_HMEBOX3_8814B 0x01DC
#define REG_RXDESC_BUFF_BNDY_8814B 0x01E0
#define REG_BB_ACCESS_CTRL_8814B 0x01E8
#define REG_BB_ACCESS_DATA_8814B 0x01EC
#define REG_HMEBOX_E0_8814B 0x01F0
#define REG_HMEBOX_E1_8814B 0x01F4
#define REG_HMEBOX_E2_8814B 0x01F8
#define REG_HMEBOX_E3_8814B 0x01FC
#define REG_CR_EXT_8814B 0x1100
#define REG_TC9_CTRL_8814B 0x1104
#define REG_TC10_CTRL_8814B 0x1108
#define REG_TC11_CTRL_8814B 0x110C
#define REG_TC12_CTRL_8814B 0x1110
#define REG_FWFF_8814B 0x1114
#define REG_RXFF_PTR_V1_8814B 0x1118
#define REG_RXFF_WTR_V1_8814B 0x111C
#define REG_FE2IMR_8814B 0x1120
#define REG_FE2ISR_8814B 0x1124
#define REG_FE3IMR_8814B 0x1128
#define REG_FE3ISR_8814B 0x112C
#define REG_FE4IMR_8814B 0x1130
#define REG_FE4ISR_8814B 0x1134
#define REG_FT1IMR_8814B 0x1138
#define REG_FT1ISR_8814B 0x113C
#define REG_SPWR0_8814B 0x1140
#define REG_SPWR1_8814B 0x1144
#define REG_SPWR2_8814B 0x1148
#define REG_SPWR3_8814B 0x114C
#define REG_POWSEQ_8814B 0x1150
#define REG_TC7_CTRL_V1_8814B 0x1158
#define REG_TC8_CTRL_V1_8814B 0x115C
#define REG_RX_BCN_TBTT_ITVL0_8814B 0x1160
#define REG_RX_BCN_TBTT_ITVL1_8814B 0x1164
#define REG_FWIMR1_8814B 0x1168
#define REG_FWISR1_8814B 0x116C
#define REG_FWIMR2_8814B 0x1170
#define REG_FWISR2_8814B 0x1174
#define REG_FWIMR3_8814B 0x1178
#define REG_FWISR3_8814B 0x117C
#define REG_SPEED_SENSOR_8814B 0x1180
#define REG_SPEED_SENSOR1_8814B 0x1184
#define REG_SPEED_SENSOR2_8814B 0x1188
#define REG_SPEED_SENSOR3_8814B 0x118C
#define REG_SPEED_SENSOR4_8814B 0x1190
#define REG_SPEED_SENSOR5_8814B 0x1194
#define REG_RXPKTBUF_1_MAX_ADDR_8814B 0x1198
#define REG_RXFWBUF_1_MAX_ADDR_8814B 0x119C
#define REG_IO_WRAP_ERR_FLAG_V1_8814B 0x11A0
#define REG_RXPKTBUF_1_READ_8814B 0x11A4
#define REG_RXPKTBUF_1_WRITE_8814B 0x11A8
#define REG_BUFF_DBGUG_8814B 0x11AC
#define REG_RFE_CTRL_PAD_E2_8814B 0x11B0
#define REG_RFE_CTRL_PAD_SR_8814B 0x11B4
#define REG_H2C_PRIORITY_SEL_8814B 0x11C0
#define REG_COUNTER_CTRL_8814B 0x11C4
#define REG_COUNTER_THRESHOLD_8814B 0x11C8
#define REG_COUNTER_SET_8814B 0x11CC
#define REG_COUNTER_OVERFLOW_8814B 0x11D0
#define REG_TXDMA_LEN_THRESHOLD_8814B 0x11D4
#define REG_RXDMA_LEN_THRESHOLD_8814B 0x11D8
#define REG_PCIE_EXEC_TIME_THRESHOLD_8814B 0x11DC
#define REG_FT2IMR_8814B 0x11E0
#define REG_FT2ISR_8814B 0x11E4
#define REG_MSG2_8814B 0x11F0
#define REG_MSG3_8814B 0x11F4
#define REG_MSG4_8814B 0x11F8
#define REG_MSG5_8814B 0x11FC
#define REG_BIST_RSTN0_8814B 0x2100
#define REG_BIST_RSTN2_8814B 0x2108
#define REG_BIST_MODE_NRML0_8814B 0x2110
#define REG_BIST_MODE_NRML1_8814B 0x2114
#define REG_BIST_MODE_NRML2_8814B 0x2118
#define REG_BIST_MODE_NRML3_8814B 0x211C
#define REG_BIST_DONE_NRML_MAC_8814B 0x2150
#define REG_BIST_DONE_NRML1_8814B 0x2158
#define REG_BIST_DONE_DRF_MAC_8814B 0x2160
#define REG_BIST_DONE_DRF_8814B 0x2164
#define REG_BIST_DONE_DRF1_8814B 0x2168
#define REG_BIST_FAIL_NRML_MAC_8814B 0x2170
#define REG_BIST_FAIL_NRML_8814B 0x2174
#define REG_BIST_FAIL_NRML1_8814B 0x2178
#define REG_BIST_FAIL_NRML_MAC_V1_8814B 0x2180
#define REG_BIST_FAIL_NRML_V1_8814B 0x2184
#define REG_BIST_FAIL_NRML1_V1_8814B 0x2188
#define REG_BIST_MISR_DATAOUT_8814B 0x2190
#define REG_BIST_MISR_DATAOUT1_8814B 0x2194
#define REG_BIST_MISR_DATAOUT_CPU_8814B 0x2198
#define REG_BIST_MISR_DATAOUT_CPU1_8814B 0x219C
#define REG_BIST_MISR_DATAOUT_CPU2_8814B 0x21A0
#define REG_BIST_MISR_DATOUT_CPU3_8814B 0x21A4
#define REG_BCN_CTRL_0_8814B 0x0200
#define REG_BCN_CTRL_1_8814B 0x0204
#define REG_AUTO_LLT_V1_8814B 0x0208
#define REG_TXDMA_OFFSET_CHK_8814B 0x020C
#define REG_TXDMA_STATUS_8814B 0x0210
#define REG_TX_DMA_DBG_8814B 0x0214
#define REG_DMA_RQPN_INFO_PUB_8814B 0x0218
#define REG_RQPN_CTRL_2_V1_8814B 0x021C
#define REG_BCN_CTRL_2_8814B 0x0220
#define REG_TXPKTNUM_0_8814B 0x0230
#define REG_TXPKTNUM_1_8814B 0x0234
#define REG_TXPKTNUM_2_8814B 0x0238
#define REG_TXPKTNUM_3_8814B 0x023C
#define REG_TX_AGG_ALIGN_8814B 0x0240
#define REG_H2C_HEAD_8814B 0x0244
#define REG_H2C_TAIL_8814B 0x0248
#define REG_H2C_READ_ADDR_8814B 0x024C
#define REG_H2C_WR_ADDR_8814B 0x0250
#define REG_H2C_INFO_8814B 0x0254
#define REG_DMA_OQT_0_8814B 0x0260
#define REG_DMA_OQT_1_8814B 0x0264
#define REG_RXDMA_AGG_PG_TH_8814B 0x0280
#define REG_RXDMA_CTRL_8814B 0x0284
#define REG_RXDMA_STATUS_8814B 0x0288
#define REG_RXDMA_DPR_8814B 0x028C
#define REG_RXDMA_MODE_8814B 0x0290
#define REG_C2H_PKT_8814B 0x0294
#define REG_FWFF_C2H_8814B 0x0298
#define REG_FWFF_CTRL_8814B 0x029C
#define REG_FWFF_PKT_INFO_8814B 0x02A0
#define REG_FWFF_PKT_INFO2_8814B 0x02A4
#define REG_RXPKTNUM_8814B 0x02B0
#define REG_RXPKTNUM_TH_8814B 0x02B4
#define REG_FW_UPD_RXDES_RDPTR_8814B 0x02B8
#define REG_DDMA_CH0SA_8814B 0x1200
#define REG_DDMA_CH0DA_8814B 0x1204
#define REG_DDMA_CH0CTRL_8814B 0x1208
#define REG_DDMA_CH1SA_8814B 0x1210
#define REG_DDMA_CH1DA_8814B 0x1214
#define REG_DDMA_CH1CTRL_8814B 0x1218
#define REG_DDMA_CH2SA_8814B 0x1220
#define REG_DDMA_CH2DA_8814B 0x1224
#define REG_DDMA_CH2CTRL_8814B 0x1228
#define REG_DDMA_CH3SA_8814B 0x1230
#define REG_DDMA_CH3DA_8814B 0x1234
#define REG_DDMA_CH3CTRL_8814B 0x1238
#define REG_DDMA_CH4SA_8814B 0x1240
#define REG_DDMA_CH4DA_8814B 0x1244
#define REG_DDMA_CH4CTRL_8814B 0x1248
#define REG_DDMA_CH5SA_8814B 0x1250
#define REG_DDMA_CH5DA_8814B 0x1254
#define REG_DDMA_CH5CTRL_8814B 0x1258
#define REG_DDMA_INT_MSK_8814B 0x12E0
#define REG_DDMA_CHSTATUS_8814B 0x12E8
#define REG_DDMA_CHKSUM_8814B 0x12F0
#define REG_DDMA_MONITOR_8814B 0x12FC
#define REG_DMA_RQPN_INFO_0_8814B 0x2200
#define REG_DMA_RQPN_INFO_1_8814B 0x2204
#define REG_DMA_RQPN_INFO_2_8814B 0x2208
#define REG_DMA_RQPN_INFO_3_8814B 0x220C
#define REG_DMA_RQPN_INFO_4_8814B 0x2210
#define REG_DMA_RQPN_INFO_5_8814B 0x2214
#define REG_DMA_RQPN_INFO_6_8814B 0x2218
#define REG_DMA_RQPN_INFO_7_8814B 0x221C
#define REG_DMA_RQPN_INFO_8_8814B 0x2220
#define REG_DMA_RQPN_INFO_9_8814B 0x2224
#define REG_DMA_RQPN_INFO_10_8814B 0x2228
#define REG_DMA_RQPN_INFO_11_8814B 0x222C
#define REG_DMA_RQPN_INFO_12_8814B 0x2230
#define REG_DMA_RQPN_INFO_13_8814B 0x2234
#define REG_DMA_RQPN_INFO_14_8814B 0x2238
#define REG_DMA_RQPN_INFO_15_8814B 0x223C
#define REG_DMA_RQPN_INFO_16_8814B 0x2240
#define REG_HWAMSDU_CTL1_8814B 0x2250
#define REG_HWAMSDU_CTL2_8814B 0x2254
#define REG_TXPAGE_INT_CTRL_0_8814B 0x3200
#define REG_TXPAGE_INT_CTRL_1_8814B 0x3204
#define REG_TXPAGE_INT_CTRL_2_8814B 0x3208
#define REG_TXPAGE_INT_CTRL_3_8814B 0x320C
#define REG_TXPAGE_INT_CTRL_4_8814B 0x3210
#define REG_TXPAGE_INT_CTRL_5_8814B 0x3214
#define REG_TXPAGE_INT_CTRL_6_8814B 0x3218
#define REG_TXPAGE_INT_CTRL_7_8814B 0x321C
#define REG_TXPAGE_INT_CTRL_8_8814B 0x3220
#define REG_TXPAGE_INT_CTRL_9_8814B 0x3224
#define REG_TXPAGE_INT_CTRL_10_8814B 0x3228
#define REG_TXPAGE_INT_CTRL_11_8814B 0x322C
#define REG_TXPAGE_INT_CTRL_12_8814B 0x3230
#define REG_TXPAGE_INT_CTRL_13_8814B 0x3234
#define REG_TXPAGE_INT_CTRL_14_8814B 0x3238
#define REG_TXPAGE_INT_CTRL_15_8814B 0x323C
#define REG_TXPAGE_INT_CTRL_16_8814B 0x3240
#define REG_PCIE_CTRL_8814B 0x0300
#define REG_ACH_CTRL_8814B 0x0304
#define REG_HIQ_CTRL_8814B 0x0308
#define REG_INT_MIG_V1_8814B 0x030C
#define REG_P0MGQ_TXBD_DESA_L_8814B 0x0310
#define REG_P0MGQ_TXBD_DESA_H_8814B 0x0314
#define REG_ACH0_TXBD_DESA_L_8814B 0x0318
#define REG_ACH0_TXBD_DESA_H_8814B 0x031C
#define REG_ACH1_TXBD_DESA_L_8814B 0x0320
#define REG_ACH1_TXBD_DESA_H_8814B 0x0324
#define REG_ACH2_TXBD_DESA_L_8814B 0x0328
#define REG_ACH2_TXBD_DESA_H_8814B 0x032C
#define REG_ACH3_TXBD_DESA_L_8814B 0x0330
#define REG_ACH3_TXBD_DESA_H_8814B 0x0334
#define REG_P0RXQ_RXBD_DESA_L_8814B 0x0338
#define REG_P0RXQ_RXBD_DESA_H_8814B 0x033C
#define REG_P0BCNQ_TXBD_DESA_L_8814B 0x0340
#define REG_P0BCNQ_TXBD_DESA_H_8814B 0x0344
#define REG_FWCMDQ_TXBD_DESA_L_8814B 0x0348
#define REG_FWCMDQ_TXBD_DESA_H_8814B 0x034C
#define REG_PCIE_HRPWM1_HCPWM1_DCPU_8814B 0x0354
#define REG_P0_MPRT_BCNQ_TXBD_DESA_L_8814B 0x0358
#define REG_P0_MPRT_BCNQ_TXBD_DESA_H_8814B 0x035C
#define REG_P0_MPRT_BCNQ_TXRXBD_NUM_8814B 0x036C
#define REG_BD_RWPTR_CLR2_8814B 0x0370
#define REG_BD_RWPTR_CLR3_8814B 0x0374
#define REG_P0MGQ_RXQ_TXRXBD_NUM_8814B 0x0378
#define REG_CHNL_DMA_CFG_8814B 0x037C
#define REG_FWCMDQ_TXBD_NUM_8814B 0x0380
#define REG_ACH0_ACH1_TXBD_NUM_8814B 0x0384
#define REG_ACH2_ACH3_TXBD_NUM_8814B 0x0388
#define REG_P0HI0Q_HI1Q_TXBD_NUM_8814B 0x038C
#define REG_P0HI2Q_HI3Q_TXBD_NUM_8814B 0x0390
#define REG_P0HI4Q_HI5Q_TXBD_NUM_8814B 0x0394
#define REG_P0HI6Q_HI7Q_TXBD_NUM_8814B 0x0398
#define REG_BD_RWPTR_CLR1_8814B 0x039C
#define REG_TSFTIMER_HCI_8814B 0x039C
#define REG_ACH0_TXBD_IDX_8814B 0x03A0
#define REG_ACH1_TXBD_IDX_8814B 0x03A4
#define REG_ACH2_TXBD_IDX_8814B 0x03A8
#define REG_ACH3_TXBD_IDX_8814B 0x03AC
#define REG_P0MGQ_TXBD_IDX_8814B 0x03B0
#define REG_P0RXQ_RXBD_IDX_8814B 0x03B4
#define REG_P0HI0Q_TXBD_IDX_8814B 0x03B8
#define REG_P0HI1Q_TXBD_IDX_8814B 0x03BC
#define REG_P0HI2Q_TXBD_IDX_8814B 0x03C0
#define REG_P0HI3Q_TXBD_IDX_8814B 0x03C4
#define REG_P0HI4Q_TXBD_IDX_8814B 0x03C8
#define REG_P0HI5Q_TXBD_IDX_8814B 0x03CC
#define REG_P0HI6Q_TXBD_IDX_8814B 0x03D0
#define REG_P0HI7Q_TXBD_IDX_8814B 0x03D4
#define REG_DBGSEL_PCIE_HRPWM1_HCPWM1_V1_8814B 0x03D8
#define REG_PCIE_HRPWM2_HCPWM2_V1_8814B 0x03DC
#define REG_PCIE_H2C_MSG_V1_8814B 0x03E0
#define REG_PCIE_C2H_MSG_V1_8814B 0x03E4
#define REG_DBI_WDATA_V1_8814B 0x03E8
#define REG_DBI_RDATA_V1_8814B 0x03EC
#define REG_DBI_FLAG_V1_8814B 0x03F0
#define REG_MDIO_V1_8814B 0x03F4
#define REG_PCIE_MIX_CFG_8814B 0x03F8
#define REG_HCI_MIX_CFG_8814B 0x03FC
#define REG_STC_INT_CS_8814B 0x1300
#define REG_ST_INT_CFG_8814B 0x1304
#define REG_ACH4_ACH5_TXBD_NUM_8814B 0x130C
#define REG_FWCMDQ_TXBD_IDX_8814B 0x1318
#define REG_P0HI8Q_TXBD_IDX_8814B 0x131C
#define REG_H2CQ_TXBD_DESA_L_8814B 0x1320
#define REG_H2CQ_TXBD_DESA_H_8814B 0x1324
#define REG_H2CQ_TXBD_NUM_8814B 0x1328
#define REG_H2CQ_TXBD_IDX_8814B 0x132C
#define REG_H2CQ_CSR_8814B 0x1330
#define REG_P0HI9Q_TXBD_IDX_8814B 0x1334
#define REG_P0HI10Q_TXBD_IDX_8814B 0x1338
#define REG_P0HI11Q_TXBD_IDX_8814B 0x133C
#define REG_P0HI12Q_TXBD_IDX_8814B 0x1340
#define REG_P0HI13Q_TXBD_IDX_8814B 0x1344
#define REG_P0HI14Q_TXBD_IDX_8814B 0x1348
#define REG_P0HI15Q_TXBD_IDX_8814B 0x134C
#define REG_CHANGE_PCIE_SPEED_8814B 0x1350
#define REG_DEBUG_STATE1_8814B 0x1354
#define REG_DEBUG_STATE2_8814B 0x1358
#define REG_DEBUG_STATE3_8814B 0x135C
#define REG_ACH5_TXBD_DESA_L_8814B 0x1360
#define REG_ACH5_TXBD_DESA_H_8814B 0x1364
#define REG_ACH6_TXBD_DESA_L_8814B 0x1368
#define REG_ACH6_TXBD_DESA_H_8814B 0x136C
#define REG_ACH7_TXBD_DESA_L_8814B 0x1370
#define REG_ACH7_TXBD_DESA_H_8814B 0x1374
#define REG_ACH8_TXBD_DESA_L_8814B 0x1378
#define REG_ACH8_TXBD_DESA_H_8814B 0x137C
#define REG_ACH9_TXBD_DESA_L_8814B 0x1380
#define REG_ACH9_TXBD_DESA_H_8814B 0x1384
#define REG_ACH10_TXBD_DESA_L_8814B 0x1388
#define REG_ACH10_TXBD_DESA_H_8814B 0x138C
#define REG_ACH11_TXBD_DESA_L_8814B 0x1390
#define REG_ACH11_TXBD_DESA_H_8814B 0x1394
#define REG_ACH12_TXBD_DESA_L_8814B 0x1398
#define REG_ACH12_TXBD_DESA_H_8814B 0x139C
#define REG_ACH13_TXBD_DESA_L_8814B 0x13A0
#define REG_ACH13_TXBD_DESA_H_8814B 0x13A4
#define REG_HI0Q_TXBD_DESA_L_8814B 0x13A8
#define REG_HI0Q_TXBD_DESA_H_8814B 0x13AC
#define REG_HI1Q_TXBD_DESA_L_8814B 0x13B0
#define REG_HI1Q_TXBD_DESA_H_8814B 0x13B4
#define REG_HI2Q_TXBD_DESA_L_8814B 0x13B8
#define REG_HI2Q_TXBD_DESA_H_8814B 0x13BC
#define REG_HI3Q_TXBD_DESA_L_8814B 0x13C0
#define REG_HI3Q_TXBD_DESA_H_8814B 0x13C4
#define REG_HI4Q_TXBD_DESA_L_8814B 0x13C8
#define REG_HI4Q_TXBD_DESA_H_8814B 0x13CC
#define REG_HI5Q_TXBD_DESA_L_8814B 0x13D0
#define REG_HI5Q_TXBD_DESA_H_8814B 0x13D4
#define REG_HI6Q_TXBD_DESA_L_8814B 0x13D8
#define REG_HI6Q_TXBD_DESA_H_8814B 0x13DC
#define REG_HI7Q_TXBD_DESA_L_8814B 0x13E0
#define REG_HI7Q_TXBD_DESA_H_8814B 0x13E4
#define REG_ACH8_ACH9_TXBD_NUM_8814B 0x13E8
#define REG_ACH10_ACH11_TXBD_NUM_8814B 0x13EC
#define REG_ACH12_ACH13_TXBD_NUM_8814B 0x13F0
#define REG_OLD_DEHANG_8814B 0x13F4
#define REG_ACH4_TXBD_DESA_L_8814B 0x13F8
#define REG_ACH4_TXBD_DESA_H_8814B 0x13FC
#define REG_HI8Q_TXBD_DESA_L_8814B 0x2300
#define REG_HI8Q_TXBD_DESA_H_8814B 0x2304
#define REG_HI9Q_TXBD_DESA_L_8814B 0x2308
#define REG_HI9Q_TXBD_DESA_H_8814B 0x230C
#define REG_HI10Q_TXBD_DESA_L_8814B 0x2310
#define REG_HI10Q_TXBD_DESA_H_8814B 0x2314
#define REG_HI11Q_TXBD_DESA_L_8814B 0x2318
#define REG_HI11Q_TXBD_DESA_H_8814B 0x231C
#define REG_HI12Q_TXBD_DESA_L_8814B 0x2320
#define REG_HI12Q_TXBD_DESA_H_8814B 0x2324
#define REG_HI13Q_TXBD_DESA_L_8814B 0x2328
#define REG_HI13Q_TXBD_DESA_H_8814B 0x232C
#define REG_HI14Q_TXBD_DESA_L_8814B 0x2330
#define REG_HI14Q_TXBD_DESA_H_8814B 0x2334
#define REG_HI15Q_TXBD_DESA_L_8814B 0x2338
#define REG_HI15Q_TXBD_DESA_H_8814B 0x233C
#define REG_HI16Q_TXBD_DESA_L_8814B 0x2340
#define REG_HI16Q_TXBD_DESA_H_8814B 0x2344
#define REG_HI17Q_TXBD_DESA_L_8814B 0x2348
#define REG_HI17Q_TXBD_DESA_H_8814B 0x234C
#define REG_HI18Q_TXBD_DESA_L_8814B 0x2350
#define REG_HI18Q_TXBD_DESA_H_8814B 0x2354
#define REG_HI19Q_TXBD_DESA_L_8814B 0x2358
#define REG_HI19Q_TXBD_DESA_H_8814B 0x235C
#define REG_BD_RWPTR_CLR6_8814B 0x2364
#define REG_P0HI16Q_TXBD_IDX_8814B 0x2370
#define REG_P0HI17Q_TXBD_IDX_8814B 0x2374
#define REG_P0HI18Q_TXBD_IDX_8814B 0x2378
#define REG_P0HI19Q_TXBD_IDX_8814B 0x237C
#define REG_P0HI16Q_HI17Q_TXBD_NUM_8814B 0x2380
#define REG_P0HI18Q_HI19Q_TXBD_NUM_8814B 0x2384
#define REG_PCIE_HISR0_8814B 0x23B4
#define REG_PCIE_HISR1_8814B 0x23BC
#define REG_P0HI8Q_HI9Q_TXBD_NUM_8814B 0x23C0
#define REG_P0HI10Q_HI11Q_TXBD_NUM_8814B 0x23C4
#define REG_P0HI12Q_HI13Q_TXBD_NUM_8814B 0x23C8
#define REG_P0HI14Q_HI15Q_TXBD_NUM_8814B 0x23CC
#define REG_ACH6_ACH7_TXBD_NUM_8814B 0x23F0
#define REG_ACH4_TXBD_IDX_8814B 0x3340
#define REG_ACH5_TXBD_IDX_8814B 0x3344
#define REG_ACH6_TXBD_IDX_8814B 0x3348
#define REG_ACH7_TXBD_IDX_8814B 0x334C
#define REG_ACH8_TXBD_IDX_8814B 0x3350
#define REG_ACH9_TXBD_IDX_8814B 0x3354
#define REG_ACH10_TXBD_IDX_8814B 0x3358
#define REG_ACH11_TXBD_IDX_8814B 0x335C
#define REG_ACH12_TXBD_IDX_8814B 0x3360
#define REG_ACH13_TXBD_IDX_8814B 0x3364
#define REG_AC_CHANNEL0_WEIGHT_8814B 0x3368
#define REG_AC_CHANNEL1_WEIGHT_8814B 0x3369
#define REG_AC_CHANNEL2_WEIGHT_8814B 0x336A
#define REG_AC_CHANNEL3_WEIGHT_8814B 0x336B
#define REG_AC_CHANNEL4_WEIGHT_8814B 0x336C
#define REG_AC_CHANNEL5_WEIGHT_8814B 0x336D
#define REG_AC_CHANNEL6_WEIGHT_8814B 0x336E
#define REG_AC_CHANNEL7_WEIGHT_8814B 0x336F
#define REG_AC_CHANNEL8_WEIGHT_8814B 0x3370
#define REG_AC_CHANNEL9_WEIGHT_8814B 0x3371
#define REG_AC_CHANNEL10_WEIGHT_8814B 0x3372
#define REG_AC_CHANNEL11_WEIGHT_8814B 0x3373
#define REG_AC_CHANNEL12_WEIGHT_8814B 0x3374
#define REG_AC_CHANNEL13_WEIGHT_8814B 0x3375
#define REG_PCIE_HISR2_8814B 0x33B4
#define REG_PCIE_HISR3_8814B 0x33BC
#define REG_QUEUELIST_INFO0_8814B 0x0400
#define REG_QUEUELIST_INFO1_8814B 0x0404
#define REG_QUEUELIST_INFO2_8814B 0x0408
#define REG_QUEUELIST_INFO3_8814B 0x040C
#define REG_QUEUELIST_INFO_EMPTY_8814B 0x0410
#define REG_QUEUELIST_ACQ_EN_8814B 0x0414
#define REG_BCNQ_BDNY_V2_8814B 0x0418
#define REG_CPU_MGQ_INFO_8814B 0x041C
#define REG_FWHW_TXQ_CTRL_8814B 0x0420
#define REG_DATAFB_SEL_8814B 0x0423
#define REG_TXBDNY_8814B 0x0424
#define REG_LIFETIME_EN_8814B 0x0426
#define REG_SPEC_SIFS_8814B 0x0428
#define REG_RETRY_LIMIT_8814B 0x042A
#define REG_TXBF_CTRL_8814B 0x042C
#define REG_DARFRC_8814B 0x0430
#define REG_DARFRCH_8814B 0x0434
#define REG_RARFRC_8814B 0x0438
#define REG_RARFRCH_8814B 0x043C
#define REG_RRSR_8814B 0x0440
#define REG_ARFR0_8814B 0x0444
#define REG_ARFRH0_8814B 0x0448
#define REG_REG_ARFR_WT0_8814B 0x044C
#define REG_REG_ARFR_WT1_8814B 0x0450
#define REG_CCK_CHECK_8814B 0x0454
#define REG_AMPDU_MAX_TIME_V1_8814B 0x0455
#define REG_TAB_SEL_8814B 0x0456
#define REG_BCN_INVALID_CTRL_8814B 0x0457
#define REG_AMPDU_MAX_LENGTH_HT_8814B 0x0458
#define REG_NDPA_RATE_8814B 0x045D
#define REG_TX_HANG_CTRL_8814B 0x045E
#define REG_NDPA_OPT_CTRL_8814B 0x045F
#define REG_AMPDU_MAX_LENGTH_VHT_8814B 0x0460
#define REG_RD_RESP_PKT_TH_8814B 0x0463
#define REG_NEW_EDCA_CTRL_V1_8814B 0x0464
#define REG_ACQ_STOP_V2_8814B 0x0468
#define REG_WMAC_LBK_BUF_HD_V1_8814B 0x0478
#define REG_MGQ_BDNY_V1_8814B 0x047A
#define REG_TXRPT_CTRL_8814B 0x047C
#define REG_INIRTS_RATE_SEL_8814B 0x0480
#define REG_BASIC_CFEND_RATE_8814B 0x0481
#define REG_STBC_CFEND_RATE_8814B 0x0482
#define REG_DATA_SC_8814B 0x0483
#define REG_MOREDATA_V1_8814B 0x0484
#define REG_DATA_SC1_8814B 0x0487
#define REG_TXRPT_START_OFFSET_8814B 0x04AC
#define REG_POWER_STAGE1_8814B 0x04B4
#define REG_POWER_STAGE2_8814B 0x04B8
#define REG_SW_AMPDU_BURST_MODE_CTRL_8814B 0x04BC
#define REG_PKT_LIFE_TIME_8814B 0x04C0
#define REG_STBC_SETTING_8814B 0x04C4
#define REG_STBC_SETTING2_8814B 0x04C5
#define REG_QUEUE_CTRL_8814B 0x04C6
#define REG_SINGLE_AMPDU_CTRL_8814B 0x04C7
#define REG_PROT_MODE_CTRL_8814B 0x04C8
#define REG_BAR_MODE_CTRL_8814B 0x04CC
#define REG_RA_TRY_RATE_AGG_LMT_8814B 0x04CF
#define REG_MACID_SLEEP_CTRL_8814B 0x04D0
#define REG_MACID_SLEEP_INFO_8814B 0x04D4
#define REG_HW_SEQ0_8814B 0x04D8
#define REG_HW_SEQ1_8814B 0x04DA
#define REG_HW_SEQ2_8814B 0x04DC
#define REG_HW_SEQ3_8814B 0x04DE
#define REG_PTCL_ERR_STATUS_V1_8814B 0x04E2
#define REG_NULL_PKT_STATUS_V2_8814B 0x04E4
#define REG_PRECNT_CTRL_8814B 0x04E5
#define REG_NULL_PKT_STATUS_EXTEND_V1_8814B 0x04E7
#define REG_PTCL_DBG_V1_8814B 0x04EC
#define REG_BT_POLLUTE_PKTCNT_8814B 0x04F0
#define REG_CPUMGQ_TIMER_CTRL2_8814B 0x04F4
#define REG_PTCL_DBG_OUT_8814B 0x04F8
#define REG_DUMMY_PAGE4_V1_8814B 0x04FC
#define REG_DUMMY_PAGE4_1_8814B 0x04FE
#define REG_MU_OFFSET_8814B 0x1400
#define REG_BF0_TIME_SETTING_8814B 0x1428
#define REG_BF1_TIME_SETTING_8814B 0x142C
#define REG_BF_TIMEOUT_EN_8814B 0x1430
#define REG_MACID_RELEASE_INFO_8814B 0x1434
#define REG_MACID_RELEASE_SUCCESS_INFO_8814B 0x1438
#define REG_MACID_RELEASE_CTRL_8814B 0x143C
#define REG_FAST_EDCA_VOVI_SETTING_8814B 0x1448
#define REG_FAST_EDCA_BEBK_SETTING_8814B 0x144C
#define REG_MACID_DROP_INFO_8814B 0x1450
#define REG_MACID_DROP_CTRL_8814B 0x1454
#define REG_MGQ_FIFO_WRITE_POINTER_8814B 0x1470
#define REG_MGQ_FIFO_READ_POINTER_8814B 0x1472
#define REG_MGQ_FIFO_ENABLE_8814B 0x1472
#define REG_MGQ_FIFO_RELEASE_INT_MASK_8814B 0x1474
#define REG_MGQ_FIFO_RELEASE_INT_FLAG_8814B 0x1476
#define REG_MGQ_FIFO_VALID_MAP_8814B 0x1478
#define REG_MGQ_FIFO_LIFETIME_8814B 0x147A
#define REG_PKT_TRANS_8814B 0x1480
#define REG_SHCUT_LLC_ETH_TYPE0_8814B 0x1484
#define REG_SHCUT_LLC_ETH_TYPE1_8814B 0x1488
#define REG_SHCUT_LLC_OUI0_8814B 0x148C
#define REG_SHCUT_LLC_OUI1_8814B 0x1490
#define REG_SHCUT_LLC_OUI2_8814B 0x1494
#define REG_FWCMDQ_CTRL_8814B 0x14A0
#define REG_FWCMDQ_PAGE_8814B 0x14A4
#define REG_FWCMDQ_INFO_8814B 0x14A8
#define REG_FWCMDQ_HOLD_PKTNUM_8814B 0x14AC
#define REG_MU_TX_CTRL_8814B 0x14C0
#define REG_MU_STA_GID_VLD_8814B 0x14C4
#define REG_MU_STA_USER_POS_INFO_8814B 0x14C8
#define REG_MU_STA_USER_POS_INFO_H_8814B 0x14CC
#define REG_CHNL_INFO_CTRL_8814B 0x14D0
#define REG_CHNL_IDLE_TIME_8814B 0x14D4
#define REG_CHNL_BUSY_TIME_8814B 0x14D8
#define REG_MU_TRX_DBG_CNT_V1_8814B 0x14DC
#define REG_SWPS_CTRL_8814B 0x14F4
#define REG_SWPS_PKT_TH_8814B 0x14F6
#define REG_SWPS_TIME_TH_8814B 0x14F8
#define REG_MACID_SWPS_EN_8814B 0x14FC
#define REG_EDCA_VO_PARAM_8814B 0x0500
#define REG_EDCA_VI_PARAM_8814B 0x0504
#define REG_EDCA_BE_PARAM_8814B 0x0508
#define REG_EDCA_BK_PARAM_8814B 0x050C
#define REG_BCNTCFG_8814B 0x0510
#define REG_PIFS_8814B 0x0512
#define REG_RDG_PIFS_8814B 0x0513
#define REG_SIFS_8814B 0x0514
#define REG_FORCE_BCN_IFS_V1_8814B 0x0518
#define REG_AGGR_BREAK_TIME_8814B 0x051A
#define REG_SLOT_8814B 0x051B
#define REG_EDCA_CPUMGQ_PARAM_8814B 0x051C
#define REG_CPUMGQ_PAUSE_8814B 0x051E
#define REG_TX_PTCL_CTRL_8814B 0x0520
#define REG_TXPAUSE_8814B 0x0522
#define REG_DIS_TXREQ_CLR_8814B 0x0523
#define REG_RD_CTRL_8814B 0x0524
#define REG_PKT_LIFETIME_CTRL_8814B 0x0528
#define REG_TXOP_LIMIT_CTRL_8814B 0x052C
#define REG_CCA_TXEN_CNT_8814B 0x0534
#define REG_MAX_INTER_COLLISION_8814B 0x0538
#define REG_MAX_INTER_COLLISION_CNT_8814B 0x053C
#define REG_RD_NAV_NXT_8814B 0x0544
#define REG_NAV_PROT_LEN_8814B 0x0546
#define REG_FTM_PTT_8814B 0x0548
#define REG_FTM_TSF_8814B 0x054C
#define REG_HGQ_TIMEOUT_PERIOD_8814B 0x0575
#define REG_TXCMD_TIMEOUT_PERIOD_8814B 0x0576
#define REG_MISC_CTRL_8814B 0x0577
#define REG_TXOP_MIN_8814B 0x0590
#define REG_PRE_BKF_TIME_8814B 0x0592
#define REG_CROSS_TXOP_CTRL_8814B 0x0593
#define REG_ACMHWCTRL_8814B 0x05C0
#define REG_ACMRSTCTRL_8814B 0x05C1
#define REG_ACMAVG_8814B 0x05C2
#define REG_VO_ADMTIME_8814B 0x05C4
#define REG_VI_ADMTIME_8814B 0x05C6
#define REG_BE_ADMTIME_8814B 0x05C8
#define REG_MAC_HEADER_NAV_OFFSET_8814B 0x05CA
#define REG_DIS_NDPA_NAV_CHECK_8814B 0x05CB
#define REG_EDCA_RANDOM_GEN_8814B 0x05CC
#define REG_TXCMD_SEL_8814B 0x05CF
#define REG_MU_DBG_INFO_8814B 0x05E8
#define REG_MU_DBG_INFO_1_8814B 0x05EC
#define REG_SCH_DBG_SEL_8814B 0x05F0
#define REG_SCHEDULER_RST_8814B 0x05F1
#define REG_MU_DBG_ERR_FLAG_8814B 0x05F2
#define REG_TX_ERR_RECOVERY_RST_8814B 0x05F3
#define REG_SCH_DBG_VALUE_8814B 0x05F4
#define REG_SCH_TXCMD_8814B 0x05F8
#define REG_PAGE5_DUMMY_8814B 0x05FC
#define REG_PORT_CTRL_SEL_8814B 0x1500
#define REG_PORT_CTRL_CFG_8814B 0x1501
#define REG_TBTT_PROHIBIT_CFG_8814B 0x1504
#define REG_DRVERLYINT_CFG_8814B 0x1507
#define REG_BCNDMATIM_CFG_8814B 0x1508
#define REG_CTWND_CFG_8814B 0x1509
#define REG_BCNIVLCUNT_CFG_8814B 0x150A
#define REG_EARLY_128US_CFG_8814B 0x150B
#define REG_TSFTR_SYNC_OFFSET_CFG_8814B 0x150C
#define REG_TSFTR_SYNC_CTRL_CFG_8814B 0x150F
#define REG_BCN_SPACE_CFG_8814B 0x1510
#define REG_EARLY_INT_ADJUST_CFG_8814B 0x1512
#define REG_SW_TBTT_TSF_INFO_8814B 0x151C
#define REG_TSFTR_LOW_8814B 0x1520
#define REG_TSFTR_HIGH_8814B 0x1524
#define REG_BCN_ERR_CNT_MAC_8814B 0x1528
#define REG_BCN_ERR_CNT_EDCCA_8814B 0x1529
#define REG_BCN_ERR_CNT_CCA_8814B 0x152A
#define REG_BCN_ERR_CNT_INVALID_8814B 0x152B
#define REG_BCN_ERR_CNT_OTHERS_8814B 0x152C
#define REG_RX_BCN_TIMER_8814B 0x152D
#define REG_TBTT_CTN_AREA_V1_8814B 0x1530
#define REG_BCN_MAX_ERR_V1_8814B 0x1531
#define REG_RXTSF_OFFSET_CCK_V1_8814B 0x1532
#define REG_RXTSF_OFFSET_OFDM_V1_8814B 0x1533
#define REG_SUB_BCN_SPACE_8814B 0x1534
#define REG_MBID_NUM_V1_8814B 0x1535
#define REG_MBSSID_CTRL_V1_8814B 0x1536
#define REG_USTIME_TSF_V1_8814B 0x1538
#define REG_BW_CFG_8814B 0x1539
#define REG_ATIMWND_CFG_8814B 0x153A
#define REG_DTIM_COUNTER_CFG_8814B 0x153B
#define REG_ATIM_DTIM_CTRL_SEL_8814B 0x153C
#define REG_ATIMUGT_V1_8814B 0x153D
#define REG_BCNDROPCTRL_V1_8814B 0x153E
#define REG_DIS_ATIM_V1_8814B 0x1540
#define REG_HIQ_NO_LMT_EN_V1_8814B 0x1544
#define REG_P2PPS_CTRL_V1_8814B 0x1548
#define REG_P2PPS_SPEC_STATE_V1_8814B 0x154A
#define REG_P2PPS_STATE_V1_8814B 0x154B
#define REG_P2PPS1_CTRL_V1_8814B 0x154C
#define REG_P2PPS1_SPEC_STATE_V1_8814B 0x154E
#define REG_P2PPS1_STATE_V1_8814B 0x154F
#define REG_P2PPS2_CTRL_V1_8814B 0x1550
#define REG_P2PPS2_SPEC_STATE_V1_8814B 0x1552
#define REG_P2PPS2_STATE_V1_8814B 0x1553
#define REG_P2PON_DIS_TXTIME_V1_8814B 0x1554
#define REG_P2POFF_DIS_TXTIME_V1_8814B 0x1555
#define REG_CHG_POWER_BCN_AREA_8814B 0x1556
#define REG_NOA_SEL_8814B 0x1557
#define REG_NOA_PARAM_V1_8814B 0x1558
#define REG_NOA_PARAM_1_V1_8814B 0x155C
#define REG_NOA_PARAM_2_V1_8814B 0x1560
#define REG_NOA_PARAM_3_V1_8814B 0x1564
#define REG_NOA_ON_ERLY_TIME_V1_8814B 0x1568
#define REG_NOA_OFF_ERLY_TIME_V1_8814B 0x1569
#define REG_P2PPS_HW_AUTO_PAUSE_CTRL_8814B 0x156C
#define REG_P2PPS1_HW_AUTO_PAUSE_CTRL_8814B 0x1570
#define REG_P2PPS2_HW_AUTO_PAUSE_CTRL_8814B 0x1574
#define REG_RX_TBTT_SHIFT_8814B 0x1578
#define REG_FREERUN_CNT_LOW_8814B 0x1580
#define REG_FREERUN_CNT_HIGH_8814B 0x1584
#define REG_CPUMGQ_TX_TIMER_V1_8814B 0x1588
#define REG_PS_TIMER_0_8814B 0x158C
#define REG_PS_TIMER_1_8814B 0x1590
#define REG_PS_TIMER_2_8814B 0x1594
#define REG_PS_TIMER_3_8814B 0x1598
#define REG_PS_TIMER_4_8814B 0x159C
#define REG_PS_TIMER_5_8814B 0x15A0
#define REG_PS_TIMER_01_CTRL_8814B 0x15A4
#define REG_PS_TIMER_23_CTRL_8814B 0x15A8
#define REG_PS_TIMER_45_CTRL_8814B 0x15AC
#define REG_CPUMGQ_FREERUN_TIMER_CTRL_8814B 0x15B0
#define REG_CPUMGQ_PROHIBIT_8814B 0x15B4
#define REG_TIMER_COMPARE_8814B 0x15C0
#define REG_TIMER_COMPARE_VALUE_LOW_8814B 0x15C4
#define REG_TIMER_COMPARE_VALUE_HIGH_8814B 0x15C8
#define REG_SCHEDULER_COUNTER_8814B 0x15D0
#define REG_WMAC_CR_8814B 0x0600
#define REG_WMAC_FWPKT_CR_8814B 0x0601
#define REG_FW_STS_FILTER_8814B 0x0602
#define REG_TCR_8814B 0x0604
#define REG_RCR_8814B 0x0608
#define REG_RX_PKT_LIMIT_8814B 0x060C
#define REG_RX_DLK_TIME_8814B 0x060D
#define REG_RX_DRVINFO_SZ_8814B 0x060F
#define REG_MACID_8814B 0x0610
#define REG_MACID_H_8814B 0x0614
#define REG_BSSID_8814B 0x0618
#define REG_BSSID_H_8814B 0x061C
#define REG_MAR_8814B 0x0620
#define REG_MAR_H_8814B 0x0624
#define REG_WMAC_DEBUG_SEL_8814B 0x062C
#define REG_WMAC_TCR_TSFT_OFS_8814B 0x0630
#define REG_UDF_THSD_8814B 0x0632
#define REG_ZLD_NUM_8814B 0x0633
#define REG_STMP_THSD_8814B 0x0634
#define REG_WMAC_TXTIMEOUT_8814B 0x0635
#define REG_MCU_TEST_2_V1_8814B 0x0636
#define REG_USTIME_EDCA_8814B 0x0638
#define REG_ACKTO_CCK_8814B 0x0639
#define REG_MAC_SPEC_SIFS_8814B 0x063A
#define REG_RESP_SIFS_CCK_8814B 0x063C
#define REG_RESP_SIFS_OFDM_8814B 0x063E
#define REG_ACKTO_8814B 0x0640
#define REG_CTS2TO_8814B 0x0641
#define REG_EIFS_8814B 0x0642
#define REG_RPFM_MAP0_8814B 0x0644
#define REG_RPFM_MAP1_V1_8814B 0x0646
#define REG_RPFM_CAM_CMD_8814B 0x0648
#define REG_RPFM_CAM_RWD_8814B 0x064C
#define REG_NAV_CTRL_8814B 0x0650
#define REG_BACAMCMD_8814B 0x0654
#define REG_BACAMCONTENT_8814B 0x0658
#define REG_BACAMCONTENT_H_8814B 0x065C
#define REG_LBDLY_8814B 0x0660
#define REG_WMAC_BACAM_RPMEN_8814B 0x0661
#define REG_TX_RX_8814B 0x0662
#define REG_WMAC_BITMAP_CTL_8814B 0x0663
#define REG_RXERR_RPT_8814B 0x0664
#define REG_WMAC_TRXPTCL_CTL_8814B 0x0668
#define REG_WMAC_TRXPTCL_CTL_H_8814B 0x066C
#define REG_CAMCMD_8814B 0x0670
#define REG_CAMWRITE_8814B 0x0674
#define REG_CAMREAD_8814B 0x0678
#define REG_CAMDBG_8814B 0x067C
#define REG_SECCFG_8814B 0x0680
#define REG_RXFILTER_CATEGORY_1_8814B 0x0682
#define REG_RXFILTER_ACTION_1_8814B 0x0683
#define REG_RXFILTER_CATEGORY_2_8814B 0x0684
#define REG_RXFILTER_ACTION_2_8814B 0x0685
#define REG_RXFILTER_CATEGORY_3_8814B 0x0686
#define REG_RXFILTER_ACTION_3_8814B 0x0687
#define REG_RXFLTMAP3_8814B 0x0688
#define REG_RXFLTMAP4_8814B 0x068A
#define REG_RXFLTMAP5_8814B 0x068C
#define REG_RXFLTMAP6_8814B 0x068E
#define REG_WOW_CTRL_8814B 0x0690
#define REG_NAN_RX_TSF_FILTER_8814B 0x0691
#define REG_PS_RX_INFO_8814B 0x0692
#define REG_WMMPS_UAPSD_TID_8814B 0x0693
#define REG_LPNAV_CTRL_8814B 0x0694
#define REG_WKFMCAM_CMD_8814B 0x0698
#define REG_WKFMCAM_RWD_8814B 0x069C
#define REG_RXFLTMAP0_8814B 0x06A0
#define REG_RXFLTMAP1_8814B 0x06A2
#define REG_RXFLTMAP2_8814B 0x06A4
#define REG_BCN_PSR_RPT_8814B 0x06A8
#define REG_FLC_RPC_8814B 0x06AC
#define REG_FLC_RPCT_8814B 0x06AD
#define REG_FLC_PTS_8814B 0x06AE
#define REG_FLC_TRPC_8814B 0x06AF
#define REG_RXPKTMON_CTRL_8814B 0x06B0
#define REG_STATE_MON_8814B 0x06B4
#define REG_ERROR_MON_8814B 0x06B8
#define REG_SEARCH_MACID_8814B 0x06BC
#define REG_BT_COEX_TABLE_8814B 0x06C0
#define REG_BT_COEX_TABLE2_8814B 0x06C4
#define REG_BT_COEX_BREAK_TABLE_8814B 0x06C8
#define REG_BT_COEX_TABLE_H_8814B 0x06CC
#define REG_RXCMD_0_8814B 0x06D0
#define REG_RXCMD_1_8814B 0x06D4
#define REG_WMAC_RESP_TXINFO_8814B 0x06D8
#define REG_BBPSF_CTRL_8814B 0x06DC
#define REG_P2P_RX_BCN_NOA_8814B 0x06E0
#define REG_ASSOCIATED_BFMER0_INFO_8814B 0x06E4
#define REG_ASSOCIATED_BFMER0_INFO_H_8814B 0x06E8
#define REG_ASSOCIATED_BFMER1_INFO_8814B 0x06EC
#define REG_ASSOCIATED_BFMER1_INFO_H_8814B 0x06F0
#define REG_TX_CSI_RPT_PARAM_BW20_8814B 0x06F4
#define REG_TX_CSI_RPT_PARAM_BW40_8814B 0x06F8
#define REG_BCN_PSR_RPT2_8814B 0x1600
#define REG_BCN_PSR_RPT3_8814B 0x1604
#define REG_BCN_PSR_RPT4_8814B 0x1608
#define REG_A1_ADDR_MASK_8814B 0x160C
#define REG_RXPSF_CTRL_8814B 0x1610
#define REG_RXPSF_TYPE_CTRL_8814B 0x1614
#define REG_CAM_ACCESS_CTRL_8814B 0x1618
#define REG_CUT_AMSDU_CTRL_8814B 0x161C
#define REG_MACID2_8814B 0x1620
#define REG_MACID2_H_8814B 0x1624
#define REG_BSSID2_8814B 0x1628
#define REG_BSSID2_H_8814B 0x162C
#define REG_MACID3_8814B 0x1630
#define REG_MACID3_H_8814B 0x1634
#define REG_BSSID3_8814B 0x1638
#define REG_BSSID3_H_8814B 0x163C
#define REG_MACID4_8814B 0x1640
#define REG_MACID4_H_8814B 0x1644
#define REG_BSSID4_8814B 0x1648
#define REG_BSSID4_H_8814B 0x164C
#define REG_NOA_REPORT_8814B 0x1650
#define REG_NOA_REPORT_1_8814B 0x1654
#define REG_NOA_REPORT_2_8814B 0x1658
#define REG_NOA_REPORT_3_8814B 0x165C
#define REG_PWRBIT_SETTING_8814B 0x1660
#define REG_GENERAL_OPTION_8814B 0x1664
#define REG_FWPHYFF_RCR_8814B 0x1668
#define REG_ADDRCAM_WRITE_CONTENT_8814B 0x166C
#define REG_ADDRCAM_READ_CONTENT_8814B 0x1670
#define REG_ADDRCAM_CFG_8814B 0x1674
#define REG_CSI_RRSR_8814B 0x1678
#define REG_MU_BF_OPTION_8814B 0x167C
#define REG_WMAC_PAUSE_BB_CLR_TH_8814B 0x167D
#define REG_WMAC_MULBK_BUF_8814B 0x167E
#define REG_WMAC_MU_OPTION_8814B 0x167F
#define REG_WMAC_MU_BF_CTL_8814B 0x1680
#define REG_WMAC_MU_BFRPT_PARA_8814B 0x1682
#define REG_WMAC_ASSOCIATED_MU_BFMEE2_8814B 0x1684
#define REG_WMAC_ASSOCIATED_MU_BFMEE3_8814B 0x1686
#define REG_WMAC_ASSOCIATED_MU_BFMEE4_8814B 0x1688
#define REG_WMAC_ASSOCIATED_MU_BFMEE5_8814B 0x168A
#define REG_WMAC_ASSOCIATED_MU_BFMEE6_8814B 0x168C
#define REG_WMAC_ASSOCIATED_MU_BFMEE7_8814B 0x168E
#define REG_WMAC_BB_STOP_RX_COUNTER_8814B 0x1690
#define REG_WMAC_PLCP_MONITOR_8814B 0x1694
#define REG_WMAC_DEBUG_PORT_8814B 0x1698
#define REG_TRANSMIT_ADDRSS_0_8814B 0x16A0
#define REG_TRANSMIT_ADDRSS_0_H_8814B 0x16A4
#define REG_TRANSMIT_ADDRSS_1_8814B 0x16A8
#define REG_TRANSMIT_ADDRSS_1_H_8814B 0x16AC
#define REG_TRANSMIT_ADDRSS_2_8814B 0x16B0
#define REG_TRANSMIT_ADDRSS_2_H_8814B 0x16B4
#define REG_TRANSMIT_ADDRSS_3_8814B 0x16B8
#define REG_TRANSMIT_ADDRSS_3_H_8814B 0x16BC
#define REG_TRANSMIT_ADDRSS_4_8814B 0x16C0
#define REG_TRANSMIT_ADDRSS_4_H_8814B 0x16C4
#define REG_MACID1_8814B 0x0700
#define REG_MACID1_1_8814B 0x0704
#define REG_BSSID1_8814B 0x0708
#define REG_BSSID1_1_8814B 0x070C
#define REG_BCN_PSR_RPT1_8814B 0x0710
#define REG_ASSOCIATED_BFMEE_SEL_8814B 0x0714
#define REG_SND_PTCL_CTRL_8814B 0x0718
#define REG_RX_CSI_RPT_INFO_8814B 0x071C
#define REG_NS_ARP_CTRL_8814B 0x0720
#define REG_NS_ARP_INFO_8814B 0x0724
#define REG_BEAMFORMING_INFO_NSARP_V1_8814B 0x0728
#define REG_BEAMFORMING_INFO_NSARP_8814B 0x072C
#define REG_IPV6_8814B 0x0730
#define REG_IPV6_1_8814B 0x0734
#define REG_IPV6_2_8814B 0x0738
#define REG_IPV6_3_8814B 0x073C
#define REG_WMAC_RTX_CTX_SUBTYPE_CFG_8814B 0x0750
#define REG_WMAC_SWAES_CFG_8814B 0x0760
#define REG_BT_COEX_V2_8814B 0x0762
#define REG_BT_COEX_8814B 0x0764
#define REG_WLAN_ACT_MASK_CTRL_8814B 0x0768
#define REG_WLAN_ACT_MASK_CTRL_1_8814B 0x076C
#define REG_BT_COEX_ENHANCED_INTR_CTRL_8814B 0x076E
#define REG_BT_ACT_STATISTICS_8814B 0x0770
#define REG_BT_ACT_STATISTICS_1_8814B 0x0774
#define REG_BT_STATISTICS_CONTROL_REGISTER_8814B 0x0778
#define REG_BT_STATUS_REPORT_REGISTER_8814B 0x077C
#define REG_BT_INTERRUPT_CONTROL_REGISTER_8814B 0x0780
#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8814B 0x0784
#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8814B 0x0785
#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1_8814B 0x0788
#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8814B 0x078C
#define REG_BT_INTERRUPT_STATUS_REGISTER_8814B 0x078F
#define REG_BT_TDMA_TIME_REGISTER_8814B 0x0790
#define REG_BT_ACT_REGISTER_8814B 0x0794
#define REG_OBFF_CTRL_BASIC_8814B 0x0798
#define REG_OBFF_CTRL2_TIMER_8814B 0x079C
#define REG_LTR_CTRL_BASIC_8814B 0x07A0
#define REG_LTR_CTRL2_TIMER_THRESHOLD_8814B 0x07A4
#define REG_LTR_IDLE_LATENCY_V1_8814B 0x07A8
#define REG_LTR_ACTIVE_LATENCY_V1_8814B 0x07AC
#define REG_SMART_ANT_CONDITION_8814B 0x07B0
#define REG_SMART_ANT_CTRL_8814B 0x07B4
#define REG_CONTROL_FRAME_REPORT_8814B 0x07B8
#define REG_CONTROL_FRAME_CNT_CTRL_8814B 0x07BC
#define REG_IQ_DUMP_8814B 0x07C0
#define REG_IQ_DUMP_1_8814B 0x07C4
#define REG_IQ_DUMP_2_8814B 0x07C8
#define REG_WMAC_FTM_CTL_8814B 0x07CC
#define REG_WMAC_IQ_MDPK_FUNC_8814B 0x07CE
#define REG_WMAC_OPTION_FUNCTION_8814B 0x07D0
#define REG_WMAC_OPTION_FUNCTION_1_8814B 0x07D4
#define REG_WMAC_OPTION_FUNCTION_2_8814B 0x07D8
#define REG_RX_FILTER_FUNCTION_8814B 0x07DA
#define REG_NDP_SIG_8814B 0x07E0
#define REG_TXCMD_INFO_FOR_RSP_PKT_8814B 0x07E4
#define REG_TXCMD_INFO_FOR_RSP_PKT_1_8814B 0x07E8
#define REG_WSEC_OPTION_8814B 0x07EC
#define REG_RTS_ADDRESS_0_8814B 0x07F0
#define REG_RTS_ADDRESS_0_1_8814B 0x07F4
#define REG_RTS_ADDRESS_1_8814B 0x07F8
#define REG_RTS_ADDRESS_1_1_8814B 0x07FC
#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8814B 0x1700
#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8814B 0x1704
#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8814B 0x1708
#define REG_PCIE_CFG_FORCE_LINK_L_8814B 0x0709
#define REG_PCIE_CFG_FORCE_LINK_H_8814B 0x070A
#define REG_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B 0x070C
#define REG_PCIE_CFG_CX_NFTS_8814B 0x070D
#define REG_PCIE_CFG_DEFAULT_ENTR_LATENCY_8814B 0x070F
#define REG_PCIE_CFG_L1_MISC_SEL_8814B 0x0711
#define REG_PCIE_CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF_8814B 0x0718
#define REG_PCIE_CFG_FORCE_CLKREQ_N_PAD_8814B 0x0719
#define REG_PCIE_CFG_TIMER_MODIFIER_FOR_ACK_NAK_LATENCY_8814B 0x071A
#define REG_PCIE_CFG_TIMER_MODIFIER_FOR_FLOW_CONTROL_WATCHDOG_8814B 0x071B
#define REG_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B 0x071C
#define REG_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B 0x071D
#define REG_PCIE_CFG_L1_UNIT_SEL_8814B 0x0724
#define REG_PCIE_CFG_MIN_CLKREQ_SEL_8814B 0x0725
#define REG_SDIO_TX_CTRL_8814B 0x10250000
#define REG_SDIO_HIMR_8814B 0x10250014
#define REG_SDIO_HISR_8814B 0x10250018
#define REG_SDIO_RX_REQ_LEN_8814B 0x1025001C
#define REG_SDIO_FREE_TXPG_SEQ_V1_8814B 0x1025001F
#define REG_SDIO_FREE_TXPG_8814B 0x10250020
#define REG_SDIO_FREE_TXPG2_8814B 0x10250024
#define REG_SDIO_OQT_FREE_TXPG_V1_8814B 0x10250028
#define REG_SDIO_HTSFR_INFO_8814B 0x10250030
#define REG_SDIO_HCPWM1_V2_8814B 0x10250038
#define REG_SDIO_HCPWM2_V2_8814B 0x1025003A
#define REG_SDIO_INDIRECT_REG_CFG_8814B 0x10250040
#define REG_SDIO_INDIRECT_REG_DATA_8814B 0x10250044
#define REG_SDIO_H2C_8814B 0x10250060
#define REG_SDIO_C2H_8814B 0x10250064
#define REG_SDIO_HRPWM1_8814B 0x10250080
#define REG_SDIO_HRPWM2_8814B 0x10250082
#define REG_SDIO_HPS_CLKR_8814B 0x10250084
#define REG_SDIO_BUS_CTRL_8814B 0x10250085
#define REG_SDIO_HSUS_CTRL_8814B 0x10250086
#define REG_SDIO_RESPONSE_TIMER_8814B 0x10250088
#define REG_SDIO_CMD_CRC_8814B 0x1025008A
#define REG_SDIO_HSISR_8814B 0x10250090
#define REG_SDIO_ERR_RPT_8814B 0x102500C0
#define REG_SDIO_CMD_ERRCNT_8814B 0x102500C2
#define REG_SDIO_DATA_ERRCNT_8814B 0x102500C3
#define REG_SDIO_CMD_ERR_CONTENT_8814B 0x102500C4
#define REG_SDIO_CRC_ERR_IDX_8814B 0x102500C9
#define REG_SDIO_DATA_CRC_8814B 0x102500CA
#define REG_SDIO_DATA_REPLY_TIME_8814B 0x102500CB

#endif