hal_com.c 327 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. *
  19. ******************************************************************************/
  20. #define _HAL_COM_C_
  21. #include <drv_types.h>
  22. #include "hal_com_h2c.h"
  23. #include "hal_data.h"
  24. #ifdef RTW_HALMAC
  25. #include "../../hal/hal_halmac.h"
  26. #endif
  27. void rtw_dump_fw_info(void *sel, _adapter *adapter)
  28. {
  29. HAL_DATA_TYPE *hal_data = NULL;
  30. if (!adapter)
  31. return;
  32. hal_data = GET_HAL_DATA(adapter);
  33. if (adapter->bFWReady)
  34. RTW_PRINT_SEL(sel, "FW VER -%d.%d\n", hal_data->firmware_version, hal_data->firmware_sub_version);
  35. else
  36. RTW_PRINT_SEL(sel, "FW not ready\n");
  37. }
  38. /* #define CONFIG_GTK_OL_DBG */
  39. /*#define DBG_SEC_CAM_MOVE*/
  40. #ifdef DBG_SEC_CAM_MOVE
  41. void rtw_hal_move_sta_gk_to_dk(_adapter *adapter)
  42. {
  43. struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
  44. int cam_id, index = 0;
  45. u8 *addr = NULL;
  46. if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
  47. return;
  48. addr = get_bssid(pmlmepriv);
  49. if (addr == NULL) {
  50. RTW_INFO("%s: get bssid MAC addr fail!!\n", __func__);
  51. return;
  52. }
  53. rtw_clean_dk_section(adapter);
  54. do {
  55. cam_id = rtw_camid_search(adapter, addr, index, 1);
  56. if (cam_id == -1)
  57. RTW_INFO("%s: cam_id: %d, key_id:%d\n", __func__, cam_id, index);
  58. else
  59. rtw_sec_cam_swap(adapter, cam_id, index);
  60. index++;
  61. } while (index < 4);
  62. }
  63. void rtw_hal_read_sta_dk_key(_adapter *adapter, u8 key_id)
  64. {
  65. struct security_priv *psecuritypriv = &adapter->securitypriv;
  66. struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
  67. struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
  68. _irqL irqL;
  69. u8 get_key[16];
  70. _rtw_memset(get_key, 0, sizeof(get_key));
  71. if (key_id > 4) {
  72. RTW_INFO("%s [ERROR] gtk_keyindex:%d invalid\n", __func__, key_id);
  73. rtw_warn_on(1);
  74. return;
  75. }
  76. rtw_sec_read_cam_ent(adapter, key_id, NULL, NULL, get_key);
  77. /*update key into related sw variable*/
  78. _enter_critical_bh(&cam_ctl->lock, &irqL);
  79. if (_rtw_camid_is_gk(adapter, key_id)) {
  80. RTW_INFO("[HW KEY] -Key-id:%d "KEY_FMT"\n", key_id, KEY_ARG(get_key));
  81. RTW_INFO("[cam_cache KEY] - Key-id:%d "KEY_FMT"\n", key_id, KEY_ARG(&dvobj->cam_cache[key_id].key));
  82. }
  83. _exit_critical_bh(&cam_ctl->lock, &irqL);
  84. }
  85. #endif
  86. #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
  87. char rtw_phy_para_file_path[PATH_LENGTH_MAX];
  88. #endif
  89. void dump_chip_info(HAL_VERSION ChipVersion)
  90. {
  91. int cnt = 0;
  92. u8 buf[128] = {0};
  93. if (IS_8188E(ChipVersion))
  94. cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8188E_");
  95. else if (IS_8188F(ChipVersion))
  96. cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8188F_");
  97. else if (IS_8812_SERIES(ChipVersion))
  98. cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8812_");
  99. else if (IS_8192E(ChipVersion))
  100. cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8192E_");
  101. else if (IS_8821_SERIES(ChipVersion))
  102. cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8821_");
  103. else if (IS_8723B_SERIES(ChipVersion))
  104. cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8723B_");
  105. else if (IS_8703B_SERIES(ChipVersion))
  106. cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8703B_");
  107. else if (IS_8723D_SERIES(ChipVersion))
  108. cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8723D_");
  109. else if (IS_8814A_SERIES(ChipVersion))
  110. cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8814A_");
  111. else if (IS_8822B_SERIES(ChipVersion))
  112. cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8822B_");
  113. else if (IS_8821C_SERIES(ChipVersion))
  114. cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8821C_");
  115. else
  116. cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_UNKNOWN_");
  117. cnt += sprintf((buf + cnt), "%s_", IS_NORMAL_CHIP(ChipVersion) ? "Normal_Chip" : "Test_Chip");
  118. if (IS_CHIP_VENDOR_TSMC(ChipVersion))
  119. cnt += sprintf((buf + cnt), "%s_", "TSMC");
  120. else if (IS_CHIP_VENDOR_UMC(ChipVersion))
  121. cnt += sprintf((buf + cnt), "%s_", "UMC");
  122. else if (IS_CHIP_VENDOR_SMIC(ChipVersion))
  123. cnt += sprintf((buf + cnt), "%s_", "SMIC");
  124. if (IS_A_CUT(ChipVersion))
  125. cnt += sprintf((buf + cnt), "A_CUT_");
  126. else if (IS_B_CUT(ChipVersion))
  127. cnt += sprintf((buf + cnt), "B_CUT_");
  128. else if (IS_C_CUT(ChipVersion))
  129. cnt += sprintf((buf + cnt), "C_CUT_");
  130. else if (IS_D_CUT(ChipVersion))
  131. cnt += sprintf((buf + cnt), "D_CUT_");
  132. else if (IS_E_CUT(ChipVersion))
  133. cnt += sprintf((buf + cnt), "E_CUT_");
  134. else if (IS_F_CUT(ChipVersion))
  135. cnt += sprintf((buf + cnt), "F_CUT_");
  136. else if (IS_I_CUT(ChipVersion))
  137. cnt += sprintf((buf + cnt), "I_CUT_");
  138. else if (IS_J_CUT(ChipVersion))
  139. cnt += sprintf((buf + cnt), "J_CUT_");
  140. else if (IS_K_CUT(ChipVersion))
  141. cnt += sprintf((buf + cnt), "K_CUT_");
  142. else
  143. cnt += sprintf((buf + cnt), "UNKNOWN_CUT(%d)_", ChipVersion.CUTVersion);
  144. if (IS_1T1R(ChipVersion))
  145. cnt += sprintf((buf + cnt), "1T1R_");
  146. else if (IS_1T2R(ChipVersion))
  147. cnt += sprintf((buf + cnt), "1T2R_");
  148. else if (IS_2T2R(ChipVersion))
  149. cnt += sprintf((buf + cnt), "2T2R_");
  150. else if (IS_3T3R(ChipVersion))
  151. cnt += sprintf((buf + cnt), "3T3R_");
  152. else if (IS_3T4R(ChipVersion))
  153. cnt += sprintf((buf + cnt), "3T4R_");
  154. else if (IS_4T4R(ChipVersion))
  155. cnt += sprintf((buf + cnt), "4T4R_");
  156. else
  157. cnt += sprintf((buf + cnt), "UNKNOWN_RFTYPE(%d)_", ChipVersion.RFType);
  158. cnt += sprintf((buf + cnt), "RomVer(%d)\n", ChipVersion.ROMVer);
  159. RTW_INFO("%s", buf);
  160. }
  161. void rtw_hal_config_rftype(PADAPTER padapter)
  162. {
  163. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
  164. if (IS_1T1R(pHalData->version_id)) {
  165. pHalData->rf_type = RF_1T1R;
  166. pHalData->NumTotalRFPath = 1;
  167. } else if (IS_2T2R(pHalData->version_id)) {
  168. pHalData->rf_type = RF_2T2R;
  169. pHalData->NumTotalRFPath = 2;
  170. } else if (IS_1T2R(pHalData->version_id)) {
  171. pHalData->rf_type = RF_1T2R;
  172. pHalData->NumTotalRFPath = 2;
  173. } else if (IS_3T3R(pHalData->version_id)) {
  174. pHalData->rf_type = RF_3T3R;
  175. pHalData->NumTotalRFPath = 3;
  176. } else if (IS_4T4R(pHalData->version_id)) {
  177. pHalData->rf_type = RF_4T4R;
  178. pHalData->NumTotalRFPath = 4;
  179. } else {
  180. pHalData->rf_type = RF_1T1R;
  181. pHalData->NumTotalRFPath = 1;
  182. }
  183. RTW_INFO("%s RF_Type is %d TotalTxPath is %d\n", __FUNCTION__, pHalData->rf_type, pHalData->NumTotalRFPath);
  184. }
  185. #define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
  186. /*
  187. * Description:
  188. * Use hardware(efuse), driver parameter(registry) and default channel plan
  189. * to decide which one should be used.
  190. *
  191. * Parameters:
  192. * padapter pointer of adapter
  193. * hw_alpha2 country code from HW (efuse/eeprom/mapfile)
  194. * hw_chplan channel plan from HW (efuse/eeprom/mapfile)
  195. * BIT[7] software configure mode; 0:Enable, 1:disable
  196. * BIT[6:0] Channel Plan
  197. * sw_alpha2 country code from HW (registry/module param)
  198. * sw_chplan channel plan from SW (registry/module param)
  199. * def_chplan channel plan used when HW/SW both invalid
  200. * AutoLoadFail efuse autoload fail or not
  201. *
  202. * Return:
  203. * Final channel plan decision
  204. *
  205. */
  206. u8 hal_com_config_channel_plan(
  207. IN PADAPTER padapter,
  208. IN char *hw_alpha2,
  209. IN u8 hw_chplan,
  210. IN char *sw_alpha2,
  211. IN u8 sw_chplan,
  212. IN u8 def_chplan,
  213. IN BOOLEAN AutoLoadFail
  214. )
  215. {
  216. PHAL_DATA_TYPE pHalData;
  217. u8 force_hw_chplan = _FALSE;
  218. int chplan = -1;
  219. const struct country_chplan *country_ent = NULL, *ent;
  220. pHalData = GET_HAL_DATA(padapter);
  221. /* treat 0xFF as invalid value, bypass hw_chplan & force_hw_chplan parsing */
  222. if (hw_chplan == 0xFF)
  223. goto chk_hw_country_code;
  224. if (AutoLoadFail == _TRUE)
  225. goto chk_sw_config;
  226. #ifndef CONFIG_FORCE_SW_CHANNEL_PLAN
  227. if (hw_chplan & EEPROM_CHANNEL_PLAN_BY_HW_MASK)
  228. force_hw_chplan = _TRUE;
  229. #endif
  230. hw_chplan &= (~EEPROM_CHANNEL_PLAN_BY_HW_MASK);
  231. chk_hw_country_code:
  232. if (hw_alpha2 && !IS_ALPHA2_NO_SPECIFIED(hw_alpha2)) {
  233. ent = rtw_get_chplan_from_country(hw_alpha2);
  234. if (ent) {
  235. /* get chplan from hw country code, by pass hw chplan setting */
  236. country_ent = ent;
  237. chplan = ent->chplan;
  238. goto chk_sw_config;
  239. } else
  240. RTW_PRINT("%s unsupported hw_alpha2:\"%c%c\"\n", __func__, hw_alpha2[0], hw_alpha2[1]);
  241. }
  242. if (rtw_is_channel_plan_valid(hw_chplan))
  243. chplan = hw_chplan;
  244. else if (force_hw_chplan == _TRUE) {
  245. RTW_PRINT("%s unsupported hw_chplan:0x%02X\n", __func__, hw_chplan);
  246. /* hw infomaton invalid, refer to sw information */
  247. force_hw_chplan = _FALSE;
  248. }
  249. chk_sw_config:
  250. if (force_hw_chplan == _TRUE)
  251. goto done;
  252. if (sw_alpha2 && !IS_ALPHA2_NO_SPECIFIED(sw_alpha2)) {
  253. ent = rtw_get_chplan_from_country(sw_alpha2);
  254. if (ent) {
  255. /* get chplan from sw country code, by pass sw chplan setting */
  256. country_ent = ent;
  257. chplan = ent->chplan;
  258. goto done;
  259. } else
  260. RTW_PRINT("%s unsupported sw_alpha2:\"%c%c\"\n", __func__, sw_alpha2[0], sw_alpha2[1]);
  261. }
  262. if (rtw_is_channel_plan_valid(sw_chplan)) {
  263. /* cancel hw_alpha2 because chplan is specified by sw_chplan*/
  264. country_ent = NULL;
  265. chplan = sw_chplan;
  266. } else if (sw_chplan != RTW_CHPLAN_MAX)
  267. RTW_PRINT("%s unsupported sw_chplan:0x%02X\n", __func__, sw_chplan);
  268. done:
  269. if (chplan == -1) {
  270. RTW_PRINT("%s use def_chplan:0x%02X\n", __func__, def_chplan);
  271. chplan = def_chplan;
  272. } else if (country_ent) {
  273. RTW_PRINT("%s country code:\"%c%c\" with chplan:0x%02X\n", __func__
  274. , country_ent->alpha2[0], country_ent->alpha2[1], country_ent->chplan);
  275. } else
  276. RTW_PRINT("%s chplan:0x%02X\n", __func__, chplan);
  277. padapter->mlmepriv.country_ent = country_ent;
  278. pHalData->bDisableSWChannelPlan = force_hw_chplan;
  279. return chplan;
  280. }
  281. BOOLEAN
  282. HAL_IsLegalChannel(
  283. IN PADAPTER Adapter,
  284. IN u32 Channel
  285. )
  286. {
  287. BOOLEAN bLegalChannel = _TRUE;
  288. if (Channel > 14) {
  289. if (is_supported_5g(Adapter->registrypriv.wireless_mode) == _FALSE) {
  290. bLegalChannel = _FALSE;
  291. RTW_INFO("Channel > 14 but wireless_mode do not support 5G\n");
  292. }
  293. } else if ((Channel <= 14) && (Channel >= 1)) {
  294. if (IsSupported24G(Adapter->registrypriv.wireless_mode) == _FALSE) {
  295. bLegalChannel = _FALSE;
  296. RTW_INFO("(Channel <= 14) && (Channel >=1) but wireless_mode do not support 2.4G\n");
  297. }
  298. } else {
  299. bLegalChannel = _FALSE;
  300. RTW_INFO("Channel is Invalid !!!\n");
  301. }
  302. return bLegalChannel;
  303. }
  304. u8 MRateToHwRate(u8 rate)
  305. {
  306. u8 ret = DESC_RATE1M;
  307. switch (rate) {
  308. case MGN_1M:
  309. ret = DESC_RATE1M;
  310. break;
  311. case MGN_2M:
  312. ret = DESC_RATE2M;
  313. break;
  314. case MGN_5_5M:
  315. ret = DESC_RATE5_5M;
  316. break;
  317. case MGN_11M:
  318. ret = DESC_RATE11M;
  319. break;
  320. case MGN_6M:
  321. ret = DESC_RATE6M;
  322. break;
  323. case MGN_9M:
  324. ret = DESC_RATE9M;
  325. break;
  326. case MGN_12M:
  327. ret = DESC_RATE12M;
  328. break;
  329. case MGN_18M:
  330. ret = DESC_RATE18M;
  331. break;
  332. case MGN_24M:
  333. ret = DESC_RATE24M;
  334. break;
  335. case MGN_36M:
  336. ret = DESC_RATE36M;
  337. break;
  338. case MGN_48M:
  339. ret = DESC_RATE48M;
  340. break;
  341. case MGN_54M:
  342. ret = DESC_RATE54M;
  343. break;
  344. case MGN_MCS0:
  345. ret = DESC_RATEMCS0;
  346. break;
  347. case MGN_MCS1:
  348. ret = DESC_RATEMCS1;
  349. break;
  350. case MGN_MCS2:
  351. ret = DESC_RATEMCS2;
  352. break;
  353. case MGN_MCS3:
  354. ret = DESC_RATEMCS3;
  355. break;
  356. case MGN_MCS4:
  357. ret = DESC_RATEMCS4;
  358. break;
  359. case MGN_MCS5:
  360. ret = DESC_RATEMCS5;
  361. break;
  362. case MGN_MCS6:
  363. ret = DESC_RATEMCS6;
  364. break;
  365. case MGN_MCS7:
  366. ret = DESC_RATEMCS7;
  367. break;
  368. case MGN_MCS8:
  369. ret = DESC_RATEMCS8;
  370. break;
  371. case MGN_MCS9:
  372. ret = DESC_RATEMCS9;
  373. break;
  374. case MGN_MCS10:
  375. ret = DESC_RATEMCS10;
  376. break;
  377. case MGN_MCS11:
  378. ret = DESC_RATEMCS11;
  379. break;
  380. case MGN_MCS12:
  381. ret = DESC_RATEMCS12;
  382. break;
  383. case MGN_MCS13:
  384. ret = DESC_RATEMCS13;
  385. break;
  386. case MGN_MCS14:
  387. ret = DESC_RATEMCS14;
  388. break;
  389. case MGN_MCS15:
  390. ret = DESC_RATEMCS15;
  391. break;
  392. case MGN_MCS16:
  393. ret = DESC_RATEMCS16;
  394. break;
  395. case MGN_MCS17:
  396. ret = DESC_RATEMCS17;
  397. break;
  398. case MGN_MCS18:
  399. ret = DESC_RATEMCS18;
  400. break;
  401. case MGN_MCS19:
  402. ret = DESC_RATEMCS19;
  403. break;
  404. case MGN_MCS20:
  405. ret = DESC_RATEMCS20;
  406. break;
  407. case MGN_MCS21:
  408. ret = DESC_RATEMCS21;
  409. break;
  410. case MGN_MCS22:
  411. ret = DESC_RATEMCS22;
  412. break;
  413. case MGN_MCS23:
  414. ret = DESC_RATEMCS23;
  415. break;
  416. case MGN_MCS24:
  417. ret = DESC_RATEMCS24;
  418. break;
  419. case MGN_MCS25:
  420. ret = DESC_RATEMCS25;
  421. break;
  422. case MGN_MCS26:
  423. ret = DESC_RATEMCS26;
  424. break;
  425. case MGN_MCS27:
  426. ret = DESC_RATEMCS27;
  427. break;
  428. case MGN_MCS28:
  429. ret = DESC_RATEMCS28;
  430. break;
  431. case MGN_MCS29:
  432. ret = DESC_RATEMCS29;
  433. break;
  434. case MGN_MCS30:
  435. ret = DESC_RATEMCS30;
  436. break;
  437. case MGN_MCS31:
  438. ret = DESC_RATEMCS31;
  439. break;
  440. case MGN_VHT1SS_MCS0:
  441. ret = DESC_RATEVHTSS1MCS0;
  442. break;
  443. case MGN_VHT1SS_MCS1:
  444. ret = DESC_RATEVHTSS1MCS1;
  445. break;
  446. case MGN_VHT1SS_MCS2:
  447. ret = DESC_RATEVHTSS1MCS2;
  448. break;
  449. case MGN_VHT1SS_MCS3:
  450. ret = DESC_RATEVHTSS1MCS3;
  451. break;
  452. case MGN_VHT1SS_MCS4:
  453. ret = DESC_RATEVHTSS1MCS4;
  454. break;
  455. case MGN_VHT1SS_MCS5:
  456. ret = DESC_RATEVHTSS1MCS5;
  457. break;
  458. case MGN_VHT1SS_MCS6:
  459. ret = DESC_RATEVHTSS1MCS6;
  460. break;
  461. case MGN_VHT1SS_MCS7:
  462. ret = DESC_RATEVHTSS1MCS7;
  463. break;
  464. case MGN_VHT1SS_MCS8:
  465. ret = DESC_RATEVHTSS1MCS8;
  466. break;
  467. case MGN_VHT1SS_MCS9:
  468. ret = DESC_RATEVHTSS1MCS9;
  469. break;
  470. case MGN_VHT2SS_MCS0:
  471. ret = DESC_RATEVHTSS2MCS0;
  472. break;
  473. case MGN_VHT2SS_MCS1:
  474. ret = DESC_RATEVHTSS2MCS1;
  475. break;
  476. case MGN_VHT2SS_MCS2:
  477. ret = DESC_RATEVHTSS2MCS2;
  478. break;
  479. case MGN_VHT2SS_MCS3:
  480. ret = DESC_RATEVHTSS2MCS3;
  481. break;
  482. case MGN_VHT2SS_MCS4:
  483. ret = DESC_RATEVHTSS2MCS4;
  484. break;
  485. case MGN_VHT2SS_MCS5:
  486. ret = DESC_RATEVHTSS2MCS5;
  487. break;
  488. case MGN_VHT2SS_MCS6:
  489. ret = DESC_RATEVHTSS2MCS6;
  490. break;
  491. case MGN_VHT2SS_MCS7:
  492. ret = DESC_RATEVHTSS2MCS7;
  493. break;
  494. case MGN_VHT2SS_MCS8:
  495. ret = DESC_RATEVHTSS2MCS8;
  496. break;
  497. case MGN_VHT2SS_MCS9:
  498. ret = DESC_RATEVHTSS2MCS9;
  499. break;
  500. case MGN_VHT3SS_MCS0:
  501. ret = DESC_RATEVHTSS3MCS0;
  502. break;
  503. case MGN_VHT3SS_MCS1:
  504. ret = DESC_RATEVHTSS3MCS1;
  505. break;
  506. case MGN_VHT3SS_MCS2:
  507. ret = DESC_RATEVHTSS3MCS2;
  508. break;
  509. case MGN_VHT3SS_MCS3:
  510. ret = DESC_RATEVHTSS3MCS3;
  511. break;
  512. case MGN_VHT3SS_MCS4:
  513. ret = DESC_RATEVHTSS3MCS4;
  514. break;
  515. case MGN_VHT3SS_MCS5:
  516. ret = DESC_RATEVHTSS3MCS5;
  517. break;
  518. case MGN_VHT3SS_MCS6:
  519. ret = DESC_RATEVHTSS3MCS6;
  520. break;
  521. case MGN_VHT3SS_MCS7:
  522. ret = DESC_RATEVHTSS3MCS7;
  523. break;
  524. case MGN_VHT3SS_MCS8:
  525. ret = DESC_RATEVHTSS3MCS8;
  526. break;
  527. case MGN_VHT3SS_MCS9:
  528. ret = DESC_RATEVHTSS3MCS9;
  529. break;
  530. case MGN_VHT4SS_MCS0:
  531. ret = DESC_RATEVHTSS4MCS0;
  532. break;
  533. case MGN_VHT4SS_MCS1:
  534. ret = DESC_RATEVHTSS4MCS1;
  535. break;
  536. case MGN_VHT4SS_MCS2:
  537. ret = DESC_RATEVHTSS4MCS2;
  538. break;
  539. case MGN_VHT4SS_MCS3:
  540. ret = DESC_RATEVHTSS4MCS3;
  541. break;
  542. case MGN_VHT4SS_MCS4:
  543. ret = DESC_RATEVHTSS4MCS4;
  544. break;
  545. case MGN_VHT4SS_MCS5:
  546. ret = DESC_RATEVHTSS4MCS5;
  547. break;
  548. case MGN_VHT4SS_MCS6:
  549. ret = DESC_RATEVHTSS4MCS6;
  550. break;
  551. case MGN_VHT4SS_MCS7:
  552. ret = DESC_RATEVHTSS4MCS7;
  553. break;
  554. case MGN_VHT4SS_MCS8:
  555. ret = DESC_RATEVHTSS4MCS8;
  556. break;
  557. case MGN_VHT4SS_MCS9:
  558. ret = DESC_RATEVHTSS4MCS9;
  559. break;
  560. default:
  561. break;
  562. }
  563. return ret;
  564. }
  565. u8 hw_rate_to_m_rate(u8 rate)
  566. {
  567. u8 ret_rate = MGN_1M;
  568. switch (rate) {
  569. case DESC_RATE1M:
  570. ret_rate = MGN_1M;
  571. break;
  572. case DESC_RATE2M:
  573. ret_rate = MGN_2M;
  574. break;
  575. case DESC_RATE5_5M:
  576. ret_rate = MGN_5_5M;
  577. break;
  578. case DESC_RATE11M:
  579. ret_rate = MGN_11M;
  580. break;
  581. case DESC_RATE6M:
  582. ret_rate = MGN_6M;
  583. break;
  584. case DESC_RATE9M:
  585. ret_rate = MGN_9M;
  586. break;
  587. case DESC_RATE12M:
  588. ret_rate = MGN_12M;
  589. break;
  590. case DESC_RATE18M:
  591. ret_rate = MGN_18M;
  592. break;
  593. case DESC_RATE24M:
  594. ret_rate = MGN_24M;
  595. break;
  596. case DESC_RATE36M:
  597. ret_rate = MGN_36M;
  598. break;
  599. case DESC_RATE48M:
  600. ret_rate = MGN_48M;
  601. break;
  602. case DESC_RATE54M:
  603. ret_rate = MGN_54M;
  604. break;
  605. case DESC_RATEMCS0:
  606. ret_rate = MGN_MCS0;
  607. break;
  608. case DESC_RATEMCS1:
  609. ret_rate = MGN_MCS1;
  610. break;
  611. case DESC_RATEMCS2:
  612. ret_rate = MGN_MCS2;
  613. break;
  614. case DESC_RATEMCS3:
  615. ret_rate = MGN_MCS3;
  616. break;
  617. case DESC_RATEMCS4:
  618. ret_rate = MGN_MCS4;
  619. break;
  620. case DESC_RATEMCS5:
  621. ret_rate = MGN_MCS5;
  622. break;
  623. case DESC_RATEMCS6:
  624. ret_rate = MGN_MCS6;
  625. break;
  626. case DESC_RATEMCS7:
  627. ret_rate = MGN_MCS7;
  628. break;
  629. case DESC_RATEMCS8:
  630. ret_rate = MGN_MCS8;
  631. break;
  632. case DESC_RATEMCS9:
  633. ret_rate = MGN_MCS9;
  634. break;
  635. case DESC_RATEMCS10:
  636. ret_rate = MGN_MCS10;
  637. break;
  638. case DESC_RATEMCS11:
  639. ret_rate = MGN_MCS11;
  640. break;
  641. case DESC_RATEMCS12:
  642. ret_rate = MGN_MCS12;
  643. break;
  644. case DESC_RATEMCS13:
  645. ret_rate = MGN_MCS13;
  646. break;
  647. case DESC_RATEMCS14:
  648. ret_rate = MGN_MCS14;
  649. break;
  650. case DESC_RATEMCS15:
  651. ret_rate = MGN_MCS15;
  652. break;
  653. case DESC_RATEMCS16:
  654. ret_rate = MGN_MCS16;
  655. break;
  656. case DESC_RATEMCS17:
  657. ret_rate = MGN_MCS17;
  658. break;
  659. case DESC_RATEMCS18:
  660. ret_rate = MGN_MCS18;
  661. break;
  662. case DESC_RATEMCS19:
  663. ret_rate = MGN_MCS19;
  664. break;
  665. case DESC_RATEMCS20:
  666. ret_rate = MGN_MCS20;
  667. break;
  668. case DESC_RATEMCS21:
  669. ret_rate = MGN_MCS21;
  670. break;
  671. case DESC_RATEMCS22:
  672. ret_rate = MGN_MCS22;
  673. break;
  674. case DESC_RATEMCS23:
  675. ret_rate = MGN_MCS23;
  676. break;
  677. case DESC_RATEMCS24:
  678. ret_rate = MGN_MCS24;
  679. break;
  680. case DESC_RATEMCS25:
  681. ret_rate = MGN_MCS25;
  682. break;
  683. case DESC_RATEMCS26:
  684. ret_rate = MGN_MCS26;
  685. break;
  686. case DESC_RATEMCS27:
  687. ret_rate = MGN_MCS27;
  688. break;
  689. case DESC_RATEMCS28:
  690. ret_rate = MGN_MCS28;
  691. break;
  692. case DESC_RATEMCS29:
  693. ret_rate = MGN_MCS29;
  694. break;
  695. case DESC_RATEMCS30:
  696. ret_rate = MGN_MCS30;
  697. break;
  698. case DESC_RATEMCS31:
  699. ret_rate = MGN_MCS31;
  700. break;
  701. case DESC_RATEVHTSS1MCS0:
  702. ret_rate = MGN_VHT1SS_MCS0;
  703. break;
  704. case DESC_RATEVHTSS1MCS1:
  705. ret_rate = MGN_VHT1SS_MCS1;
  706. break;
  707. case DESC_RATEVHTSS1MCS2:
  708. ret_rate = MGN_VHT1SS_MCS2;
  709. break;
  710. case DESC_RATEVHTSS1MCS3:
  711. ret_rate = MGN_VHT1SS_MCS3;
  712. break;
  713. case DESC_RATEVHTSS1MCS4:
  714. ret_rate = MGN_VHT1SS_MCS4;
  715. break;
  716. case DESC_RATEVHTSS1MCS5:
  717. ret_rate = MGN_VHT1SS_MCS5;
  718. break;
  719. case DESC_RATEVHTSS1MCS6:
  720. ret_rate = MGN_VHT1SS_MCS6;
  721. break;
  722. case DESC_RATEVHTSS1MCS7:
  723. ret_rate = MGN_VHT1SS_MCS7;
  724. break;
  725. case DESC_RATEVHTSS1MCS8:
  726. ret_rate = MGN_VHT1SS_MCS8;
  727. break;
  728. case DESC_RATEVHTSS1MCS9:
  729. ret_rate = MGN_VHT1SS_MCS9;
  730. break;
  731. case DESC_RATEVHTSS2MCS0:
  732. ret_rate = MGN_VHT2SS_MCS0;
  733. break;
  734. case DESC_RATEVHTSS2MCS1:
  735. ret_rate = MGN_VHT2SS_MCS1;
  736. break;
  737. case DESC_RATEVHTSS2MCS2:
  738. ret_rate = MGN_VHT2SS_MCS2;
  739. break;
  740. case DESC_RATEVHTSS2MCS3:
  741. ret_rate = MGN_VHT2SS_MCS3;
  742. break;
  743. case DESC_RATEVHTSS2MCS4:
  744. ret_rate = MGN_VHT2SS_MCS4;
  745. break;
  746. case DESC_RATEVHTSS2MCS5:
  747. ret_rate = MGN_VHT2SS_MCS5;
  748. break;
  749. case DESC_RATEVHTSS2MCS6:
  750. ret_rate = MGN_VHT2SS_MCS6;
  751. break;
  752. case DESC_RATEVHTSS2MCS7:
  753. ret_rate = MGN_VHT2SS_MCS7;
  754. break;
  755. case DESC_RATEVHTSS2MCS8:
  756. ret_rate = MGN_VHT2SS_MCS8;
  757. break;
  758. case DESC_RATEVHTSS2MCS9:
  759. ret_rate = MGN_VHT2SS_MCS9;
  760. break;
  761. case DESC_RATEVHTSS3MCS0:
  762. ret_rate = MGN_VHT3SS_MCS0;
  763. break;
  764. case DESC_RATEVHTSS3MCS1:
  765. ret_rate = MGN_VHT3SS_MCS1;
  766. break;
  767. case DESC_RATEVHTSS3MCS2:
  768. ret_rate = MGN_VHT3SS_MCS2;
  769. break;
  770. case DESC_RATEVHTSS3MCS3:
  771. ret_rate = MGN_VHT3SS_MCS3;
  772. break;
  773. case DESC_RATEVHTSS3MCS4:
  774. ret_rate = MGN_VHT3SS_MCS4;
  775. break;
  776. case DESC_RATEVHTSS3MCS5:
  777. ret_rate = MGN_VHT3SS_MCS5;
  778. break;
  779. case DESC_RATEVHTSS3MCS6:
  780. ret_rate = MGN_VHT3SS_MCS6;
  781. break;
  782. case DESC_RATEVHTSS3MCS7:
  783. ret_rate = MGN_VHT3SS_MCS7;
  784. break;
  785. case DESC_RATEVHTSS3MCS8:
  786. ret_rate = MGN_VHT3SS_MCS8;
  787. break;
  788. case DESC_RATEVHTSS3MCS9:
  789. ret_rate = MGN_VHT3SS_MCS9;
  790. break;
  791. case DESC_RATEVHTSS4MCS0:
  792. ret_rate = MGN_VHT4SS_MCS0;
  793. break;
  794. case DESC_RATEVHTSS4MCS1:
  795. ret_rate = MGN_VHT4SS_MCS1;
  796. break;
  797. case DESC_RATEVHTSS4MCS2:
  798. ret_rate = MGN_VHT4SS_MCS2;
  799. break;
  800. case DESC_RATEVHTSS4MCS3:
  801. ret_rate = MGN_VHT4SS_MCS3;
  802. break;
  803. case DESC_RATEVHTSS4MCS4:
  804. ret_rate = MGN_VHT4SS_MCS4;
  805. break;
  806. case DESC_RATEVHTSS4MCS5:
  807. ret_rate = MGN_VHT4SS_MCS5;
  808. break;
  809. case DESC_RATEVHTSS4MCS6:
  810. ret_rate = MGN_VHT4SS_MCS6;
  811. break;
  812. case DESC_RATEVHTSS4MCS7:
  813. ret_rate = MGN_VHT4SS_MCS7;
  814. break;
  815. case DESC_RATEVHTSS4MCS8:
  816. ret_rate = MGN_VHT4SS_MCS8;
  817. break;
  818. case DESC_RATEVHTSS4MCS9:
  819. ret_rate = MGN_VHT4SS_MCS9;
  820. break;
  821. default:
  822. RTW_INFO("hw_rate_to_m_rate(): Non supported Rate [%x]!!!\n", rate);
  823. break;
  824. }
  825. return ret_rate;
  826. }
  827. void HalSetBrateCfg(
  828. IN PADAPTER Adapter,
  829. IN u8 *mBratesOS,
  830. OUT u16 *pBrateCfg)
  831. {
  832. u8 i, is_brate, brate;
  833. for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {
  834. is_brate = mBratesOS[i] & IEEE80211_BASIC_RATE_MASK;
  835. brate = mBratesOS[i] & 0x7f;
  836. if (is_brate) {
  837. switch (brate) {
  838. case IEEE80211_CCK_RATE_1MB:
  839. *pBrateCfg |= RATE_1M;
  840. break;
  841. case IEEE80211_CCK_RATE_2MB:
  842. *pBrateCfg |= RATE_2M;
  843. break;
  844. case IEEE80211_CCK_RATE_5MB:
  845. *pBrateCfg |= RATE_5_5M;
  846. break;
  847. case IEEE80211_CCK_RATE_11MB:
  848. *pBrateCfg |= RATE_11M;
  849. break;
  850. case IEEE80211_OFDM_RATE_6MB:
  851. *pBrateCfg |= RATE_6M;
  852. break;
  853. case IEEE80211_OFDM_RATE_9MB:
  854. *pBrateCfg |= RATE_9M;
  855. break;
  856. case IEEE80211_OFDM_RATE_12MB:
  857. *pBrateCfg |= RATE_12M;
  858. break;
  859. case IEEE80211_OFDM_RATE_18MB:
  860. *pBrateCfg |= RATE_18M;
  861. break;
  862. case IEEE80211_OFDM_RATE_24MB:
  863. *pBrateCfg |= RATE_24M;
  864. break;
  865. case IEEE80211_OFDM_RATE_36MB:
  866. *pBrateCfg |= RATE_36M;
  867. break;
  868. case IEEE80211_OFDM_RATE_48MB:
  869. *pBrateCfg |= RATE_48M;
  870. break;
  871. case IEEE80211_OFDM_RATE_54MB:
  872. *pBrateCfg |= RATE_54M;
  873. break;
  874. }
  875. }
  876. }
  877. }
  878. static VOID
  879. _OneOutPipeMapping(
  880. IN PADAPTER pAdapter
  881. )
  882. {
  883. struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(pAdapter);
  884. pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
  885. pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */
  886. pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[0];/* BE */
  887. pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];/* BK */
  888. pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
  889. pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
  890. pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
  891. pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
  892. }
  893. static VOID
  894. _TwoOutPipeMapping(
  895. IN PADAPTER pAdapter,
  896. IN BOOLEAN bWIFICfg
  897. )
  898. {
  899. struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(pAdapter);
  900. if (bWIFICfg) { /* WMM */
  901. /* BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA */
  902. /* { 0, 1, 0, 1, 0, 0, 0, 0, 0 }; */
  903. /* 0:ep_0 num, 1:ep_1 num */
  904. pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[1];/* VO */
  905. pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */
  906. pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];/* BE */
  907. pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];/* BK */
  908. pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
  909. pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
  910. pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
  911. pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
  912. } else { /* typical setting */
  913. /* BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA */
  914. /* { 1, 1, 0, 0, 0, 0, 0, 0, 0 }; */
  915. /* 0:ep_0 num, 1:ep_1 num */
  916. pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
  917. pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */
  918. pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];/* BE */
  919. pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];/* BK */
  920. pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
  921. pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
  922. pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
  923. pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
  924. }
  925. }
  926. static VOID _ThreeOutPipeMapping(
  927. IN PADAPTER pAdapter,
  928. IN BOOLEAN bWIFICfg
  929. )
  930. {
  931. struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(pAdapter);
  932. if (bWIFICfg) { /* for WMM */
  933. /* BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA */
  934. /* { 1, 2, 1, 0, 0, 0, 0, 0, 0 }; */
  935. /* 0:H, 1:N, 2:L */
  936. pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
  937. pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */
  938. pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */
  939. pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];/* BK */
  940. pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
  941. pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
  942. pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
  943. pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
  944. } else { /* typical setting */
  945. /* BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA */
  946. /* { 2, 2, 1, 0, 0, 0, 0, 0, 0 }; */
  947. /* 0:H, 1:N, 2:L */
  948. pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
  949. pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */
  950. pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */
  951. pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[2];/* BK */
  952. pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
  953. pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
  954. pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
  955. pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
  956. }
  957. }
  958. static VOID _FourOutPipeMapping(
  959. IN PADAPTER pAdapter,
  960. IN BOOLEAN bWIFICfg
  961. )
  962. {
  963. struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(pAdapter);
  964. if (bWIFICfg) { /* for WMM */
  965. /* BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA */
  966. /* { 1, 2, 1, 0, 0, 0, 0, 0, 0 }; */
  967. /* 0:H, 1:N, 2:L ,3:E */
  968. pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
  969. pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */
  970. pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */
  971. pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];/* BK */
  972. pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
  973. pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
  974. pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[3];/* HIGH */
  975. pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
  976. } else { /* typical setting */
  977. /* BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA */
  978. /* { 2, 2, 1, 0, 0, 0, 0, 0, 0 }; */
  979. /* 0:H, 1:N, 2:L */
  980. pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
  981. pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */
  982. pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */
  983. pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[2];/* BK */
  984. pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
  985. pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
  986. pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[3];/* HIGH */
  987. pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
  988. }
  989. }
  990. BOOLEAN
  991. Hal_MappingOutPipe(
  992. IN PADAPTER pAdapter,
  993. IN u8 NumOutPipe
  994. )
  995. {
  996. struct registry_priv *pregistrypriv = &pAdapter->registrypriv;
  997. BOOLEAN bWIFICfg = (pregistrypriv->wifi_spec) ? _TRUE : _FALSE;
  998. BOOLEAN result = _TRUE;
  999. switch (NumOutPipe) {
  1000. case 2:
  1001. _TwoOutPipeMapping(pAdapter, bWIFICfg);
  1002. break;
  1003. case 3:
  1004. case 4:
  1005. _ThreeOutPipeMapping(pAdapter, bWIFICfg);
  1006. break;
  1007. case 1:
  1008. _OneOutPipeMapping(pAdapter);
  1009. break;
  1010. default:
  1011. result = _FALSE;
  1012. break;
  1013. }
  1014. return result;
  1015. }
  1016. void rtw_hal_reqtxrpt(_adapter *padapter, u8 macid)
  1017. {
  1018. if (padapter->hal_func.reqtxrpt)
  1019. padapter->hal_func.reqtxrpt(padapter, macid);
  1020. }
  1021. void rtw_hal_dump_macaddr(void *sel, _adapter *adapter)
  1022. {
  1023. int i;
  1024. _adapter *iface;
  1025. struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
  1026. u8 mac_addr[ETH_ALEN];
  1027. #ifdef CONFIG_MI_WITH_MBSSID_CAM
  1028. rtw_mbid_cam_dump(sel, __func__, adapter);
  1029. #else
  1030. for (i = 0; i < dvobj->iface_nums; i++) {
  1031. iface = dvobj->padapters[i];
  1032. if (iface) {
  1033. rtw_hal_get_macaddr_port(iface, mac_addr);
  1034. RTW_PRINT_SEL(sel, ADPT_FMT"- hw port(%d) mac_addr ="MAC_FMT"\n",
  1035. ADPT_ARG(iface), iface->hw_port, MAC_ARG(mac_addr));
  1036. }
  1037. }
  1038. #endif
  1039. }
  1040. void rtw_restore_mac_addr(_adapter *adapter)
  1041. {
  1042. #ifdef CONFIG_MI_WITH_MBSSID_CAM
  1043. _adapter *iface;
  1044. struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
  1045. rtw_mbid_cam_restore(adapter);
  1046. #else
  1047. int i;
  1048. _adapter *iface;
  1049. struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
  1050. for (i = 0; i < dvobj->iface_nums; i++) {
  1051. iface = dvobj->padapters[i];
  1052. if (iface)
  1053. rtw_hal_set_macaddr_port(iface, adapter_mac_addr(iface));
  1054. }
  1055. #endif
  1056. if (1)
  1057. rtw_hal_dump_macaddr(RTW_DBGDUMP, adapter);
  1058. }
  1059. void rtw_init_hal_com_default_value(PADAPTER Adapter)
  1060. {
  1061. PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
  1062. struct registry_priv *regsty = adapter_to_regsty(Adapter);
  1063. pHalData->AntDetection = 1;
  1064. pHalData->antenna_test = _FALSE;
  1065. pHalData->u1ForcedIgiLb = regsty->force_igi_lb;
  1066. }
  1067. #ifdef CONFIG_FW_C2H_REG
  1068. void c2h_evt_clear(_adapter *adapter)
  1069. {
  1070. rtw_write8(adapter, REG_C2HEVT_CLEAR, C2H_EVT_HOST_CLOSE);
  1071. }
  1072. s32 c2h_evt_read_88xx(_adapter *adapter, u8 *buf)
  1073. {
  1074. s32 ret = _FAIL;
  1075. int i;
  1076. u8 trigger;
  1077. if (buf == NULL)
  1078. goto exit;
  1079. trigger = rtw_read8(adapter, REG_C2HEVT_CLEAR);
  1080. if (trigger == C2H_EVT_HOST_CLOSE) {
  1081. goto exit; /* Not ready */
  1082. } else if (trigger != C2H_EVT_FW_CLOSE) {
  1083. goto clear_evt; /* Not a valid value */
  1084. }
  1085. _rtw_memset(buf, 0, C2H_REG_LEN);
  1086. /* Read ID, LEN, SEQ */
  1087. SET_C2H_ID_88XX(buf, rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL));
  1088. SET_C2H_SEQ_88XX(buf, rtw_read8(adapter, REG_C2HEVT_CMD_SEQ_88XX));
  1089. SET_C2H_PLEN_88XX(buf, rtw_read8(adapter, REG_C2HEVT_CMD_LEN_88XX));
  1090. if (0) {
  1091. RTW_INFO("%s id=0x%02x, seq=%u, plen=%u, trigger=0x%02x\n", __func__
  1092. , C2H_ID_88XX(buf), C2H_SEQ_88XX(buf), C2H_PLEN_88XX(buf), trigger);
  1093. }
  1094. /* Read the content */
  1095. for (i = 0; i < C2H_PLEN_88XX(buf); i++)
  1096. *(C2H_PAYLOAD_88XX(buf) + i) = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 2 + i);
  1097. RTW_DBG_DUMP("payload:\n", C2H_PAYLOAD_88XX(buf), C2H_PLEN_88XX(buf));
  1098. ret = _SUCCESS;
  1099. clear_evt:
  1100. /*
  1101. * Clear event to notify FW we have read the command.
  1102. * If this field isn't clear, the FW won't update the next command message.
  1103. */
  1104. c2h_evt_clear(adapter);
  1105. exit:
  1106. return ret;
  1107. }
  1108. #endif /* CONFIG_FW_C2H_REG */
  1109. #ifdef CONFIG_FW_C2H_PKT
  1110. #ifndef DBG_C2H_PKT_PRE_HDL
  1111. #define DBG_C2H_PKT_PRE_HDL 0
  1112. #endif
  1113. #ifndef DBG_C2H_PKT_HDL
  1114. #define DBG_C2H_PKT_HDL 0
  1115. #endif
  1116. void rtw_hal_c2h_pkt_pre_hdl(_adapter *adapter, u8 *buf, u16 len)
  1117. {
  1118. #ifdef RTW_HALMAC
  1119. /* TODO: extract hal_mac IC's code here*/
  1120. #else
  1121. u8 parse_fail = 0;
  1122. u8 hdl_here = 0;
  1123. s32 ret = _FAIL;
  1124. u8 id, seq, plen;
  1125. u8 *payload;
  1126. if (rtw_hal_c2h_pkt_hdr_parse(adapter, buf, len, &id, &seq, &plen, &payload) != _SUCCESS) {
  1127. parse_fail = 1;
  1128. goto exit;
  1129. }
  1130. hdl_here = rtw_hal_c2h_id_handle_directly(adapter, id, seq, plen, payload) == _TRUE ? 1 : 0;
  1131. if (hdl_here)
  1132. ret = rtw_hal_c2h_handler(adapter, id, seq, plen, payload);
  1133. else
  1134. ret = rtw_c2h_packet_wk_cmd(adapter, buf, len);
  1135. exit:
  1136. if (parse_fail)
  1137. RTW_ERR("%s parse fail, buf=%p, len=:%u\n", __func__, buf, len);
  1138. else if (ret != _SUCCESS || DBG_C2H_PKT_PRE_HDL > 0) {
  1139. RTW_PRINT("%s: id=0x%02x, seq=%u, plen=%u, %s %s\n", __func__, id, seq, plen
  1140. , hdl_here ? "handle" : "enqueue"
  1141. , ret == _SUCCESS ? "ok" : "fail"
  1142. );
  1143. if (DBG_C2H_PKT_PRE_HDL >= 2)
  1144. RTW_PRINT_DUMP("dump: ", buf, len);
  1145. }
  1146. #endif
  1147. }
  1148. void rtw_hal_c2h_pkt_hdl(_adapter *adapter, u8 *buf, u16 len)
  1149. {
  1150. #ifdef RTW_HALMAC
  1151. adapter->hal_func.hal_mac_c2h_handler(adapter, buf, len);
  1152. #else
  1153. u8 parse_fail = 0;
  1154. u8 bypass = 0;
  1155. s32 ret = _FAIL;
  1156. u8 id, seq, plen;
  1157. u8 *payload;
  1158. if (rtw_hal_c2h_pkt_hdr_parse(adapter, buf, len, &id, &seq, &plen, &payload) != _SUCCESS) {
  1159. parse_fail = 1;
  1160. goto exit;
  1161. }
  1162. #ifdef CONFIG_WOWLAN
  1163. if (adapter_to_pwrctl(adapter)->wowlan_mode == _TRUE) {
  1164. bypass = 1;
  1165. ret = _SUCCESS;
  1166. goto exit;
  1167. }
  1168. #endif
  1169. ret = rtw_hal_c2h_handler(adapter, id, seq, plen, payload);
  1170. exit:
  1171. if (parse_fail)
  1172. RTW_ERR("%s parse fail, buf=%p, len=:%u\n", __func__, buf, len);
  1173. else if (ret != _SUCCESS || bypass || DBG_C2H_PKT_HDL > 0) {
  1174. RTW_PRINT("%s: id=0x%02x, seq=%u, plen=%u, %s %s\n", __func__, id, seq, plen
  1175. , !bypass ? "handle" : "bypass"
  1176. , ret == _SUCCESS ? "ok" : "fail"
  1177. );
  1178. if (DBG_C2H_PKT_HDL >= 2)
  1179. RTW_PRINT_DUMP("dump: ", buf, len);
  1180. }
  1181. #endif
  1182. }
  1183. #endif /* CONFIG_FW_C2H_PKT */
  1184. void c2h_iqk_offload(_adapter *adapter, u8 *data, u8 len)
  1185. {
  1186. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
  1187. struct submit_ctx *iqk_sctx = &hal_data->iqk_sctx;
  1188. RTW_INFO("IQK offload finish in %dms\n", rtw_get_passing_time_ms(iqk_sctx->submit_time));
  1189. if (0)
  1190. RTW_INFO_DUMP("C2H_IQK_FINISH: ", data, len);
  1191. rtw_sctx_done(&iqk_sctx);
  1192. }
  1193. int c2h_iqk_offload_wait(_adapter *adapter, u32 timeout_ms)
  1194. {
  1195. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
  1196. struct submit_ctx *iqk_sctx = &hal_data->iqk_sctx;
  1197. iqk_sctx->submit_time = rtw_get_current_time();
  1198. iqk_sctx->timeout_ms = timeout_ms;
  1199. iqk_sctx->status = RTW_SCTX_SUBMITTED;
  1200. return rtw_sctx_wait(iqk_sctx, __func__);
  1201. }
  1202. #define GET_C2H_MAC_HIDDEN_RPT_UUID_X(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 0, 0, 8)
  1203. #define GET_C2H_MAC_HIDDEN_RPT_UUID_Y(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 1, 0, 8)
  1204. #define GET_C2H_MAC_HIDDEN_RPT_UUID_Z(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 2, 0, 5)
  1205. #define GET_C2H_MAC_HIDDEN_RPT_UUID_CRC(_data) LE_BITS_TO_2BYTE(((u8 *)(_data)) + 2, 5, 11)
  1206. #define GET_C2H_MAC_HIDDEN_RPT_HCI_TYPE(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 4, 0, 4)
  1207. #define GET_C2H_MAC_HIDDEN_RPT_PACKAGE_TYPE(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 4, 4, 3)
  1208. #define GET_C2H_MAC_HIDDEN_RPT_TR_SWITCH(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 4, 7, 1)
  1209. #define GET_C2H_MAC_HIDDEN_RPT_WL_FUNC(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 5, 0, 4)
  1210. #define GET_C2H_MAC_HIDDEN_RPT_HW_STYPE(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 5, 4, 4)
  1211. #define GET_C2H_MAC_HIDDEN_RPT_BW(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 0, 3)
  1212. #define GET_C2H_MAC_HIDDEN_RPT_FAB(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 3, 2)
  1213. #define GET_C2H_MAC_HIDDEN_RPT_ANT_NUM(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 5, 3)
  1214. #define GET_C2H_MAC_HIDDEN_RPT_80211_PROTOCOL(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 7, 2, 2)
  1215. #define GET_C2H_MAC_HIDDEN_RPT_NIC_ROUTER(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 7, 6, 2)
  1216. #ifndef DBG_C2H_MAC_HIDDEN_RPT_HANDLE
  1217. #define DBG_C2H_MAC_HIDDEN_RPT_HANDLE 0
  1218. #endif
  1219. #ifdef CONFIG_RTW_MAC_HIDDEN_RPT
  1220. int c2h_mac_hidden_rpt_hdl(_adapter *adapter, u8 *data, u8 len)
  1221. {
  1222. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
  1223. struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
  1224. int ret = _FAIL;
  1225. u32 uuid;
  1226. u8 uuid_x;
  1227. u8 uuid_y;
  1228. u8 uuid_z;
  1229. u16 uuid_crc;
  1230. u8 hci_type;
  1231. u8 package_type;
  1232. u8 tr_switch;
  1233. u8 wl_func;
  1234. u8 hw_stype;
  1235. u8 bw;
  1236. u8 fab;
  1237. u8 ant_num;
  1238. u8 protocol;
  1239. u8 nic;
  1240. int i;
  1241. if (len < MAC_HIDDEN_RPT_LEN) {
  1242. RTW_WARN("%s len(%u) < %d\n", __func__, len, MAC_HIDDEN_RPT_LEN);
  1243. goto exit;
  1244. }
  1245. uuid_x = GET_C2H_MAC_HIDDEN_RPT_UUID_X(data);
  1246. uuid_y = GET_C2H_MAC_HIDDEN_RPT_UUID_Y(data);
  1247. uuid_z = GET_C2H_MAC_HIDDEN_RPT_UUID_Z(data);
  1248. uuid_crc = GET_C2H_MAC_HIDDEN_RPT_UUID_CRC(data);
  1249. hci_type = GET_C2H_MAC_HIDDEN_RPT_HCI_TYPE(data);
  1250. package_type = GET_C2H_MAC_HIDDEN_RPT_PACKAGE_TYPE(data);
  1251. tr_switch = GET_C2H_MAC_HIDDEN_RPT_TR_SWITCH(data);
  1252. wl_func = GET_C2H_MAC_HIDDEN_RPT_WL_FUNC(data);
  1253. hw_stype = GET_C2H_MAC_HIDDEN_RPT_HW_STYPE(data);
  1254. bw = GET_C2H_MAC_HIDDEN_RPT_BW(data);
  1255. fab = GET_C2H_MAC_HIDDEN_RPT_FAB(data);
  1256. ant_num = GET_C2H_MAC_HIDDEN_RPT_ANT_NUM(data);
  1257. protocol = GET_C2H_MAC_HIDDEN_RPT_80211_PROTOCOL(data);
  1258. nic = GET_C2H_MAC_HIDDEN_RPT_NIC_ROUTER(data);
  1259. if (DBG_C2H_MAC_HIDDEN_RPT_HANDLE) {
  1260. for (i = 0; i < len; i++)
  1261. RTW_PRINT("%s: 0x%02X\n", __func__, *(data + i));
  1262. RTW_PRINT("uuid x:0x%02x y:0x%02x z:0x%x crc:0x%x\n", uuid_x, uuid_y, uuid_z, uuid_crc);
  1263. RTW_PRINT("hci_type:0x%x\n", hci_type);
  1264. RTW_PRINT("package_type:0x%x\n", package_type);
  1265. RTW_PRINT("tr_switch:0x%x\n", tr_switch);
  1266. RTW_PRINT("wl_func:0x%x\n", wl_func);
  1267. RTW_PRINT("hw_stype:0x%x\n", hw_stype);
  1268. RTW_PRINT("bw:0x%x\n", bw);
  1269. RTW_PRINT("fab:0x%x\n", fab);
  1270. RTW_PRINT("ant_num:0x%x\n", ant_num);
  1271. RTW_PRINT("protocol:0x%x\n", protocol);
  1272. RTW_PRINT("nic:0x%x\n", nic);
  1273. }
  1274. /*
  1275. * NOTICE:
  1276. * for now, the following is common info/format
  1277. * if there is any hal difference need to export
  1278. * some IC dependent code will need to be implement
  1279. */
  1280. hal_data->PackageType = package_type;
  1281. hal_spec->wl_func &= mac_hidden_wl_func_to_hal_wl_func(wl_func);
  1282. hal_spec->bw_cap &= mac_hidden_max_bw_to_hal_bw_cap(bw);
  1283. hal_spec->tx_nss_num = rtw_min(hal_spec->tx_nss_num, ant_num);
  1284. hal_spec->rx_nss_num = rtw_min(hal_spec->rx_nss_num, ant_num);
  1285. hal_spec->proto_cap &= mac_hidden_proto_to_hal_proto_cap(protocol);
  1286. hal_spec->hci_type = hci_type;
  1287. /* TODO: tr_switch */
  1288. /* TODO: fab */
  1289. ret = _SUCCESS;
  1290. exit:
  1291. return ret;
  1292. }
  1293. int c2h_mac_hidden_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len)
  1294. {
  1295. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
  1296. struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
  1297. int ret = _FAIL;
  1298. int i;
  1299. if (len < MAC_HIDDEN_RPT_2_LEN) {
  1300. RTW_WARN("%s len(%u) < %d\n", __func__, len, MAC_HIDDEN_RPT_2_LEN);
  1301. goto exit;
  1302. }
  1303. if (DBG_C2H_MAC_HIDDEN_RPT_HANDLE) {
  1304. for (i = 0; i < len; i++)
  1305. RTW_PRINT("%s: 0x%02X\n", __func__, *(data + i));
  1306. }
  1307. ret = _SUCCESS;
  1308. exit:
  1309. return ret;
  1310. }
  1311. int hal_read_mac_hidden_rpt(_adapter *adapter)
  1312. {
  1313. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
  1314. int ret = _FAIL;
  1315. int ret_fwdl;
  1316. u8 mac_hidden_rpt[MAC_HIDDEN_RPT_LEN + MAC_HIDDEN_RPT_2_LEN] = {0};
  1317. u32 start = rtw_get_current_time();
  1318. u32 cnt = 0;
  1319. u32 timeout_ms = 800;
  1320. u32 min_cnt = 10;
  1321. u8 id = C2H_DEFEATURE_RSVD;
  1322. int i;
  1323. #if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
  1324. u8 hci_type = rtw_get_intf_type(adapter);
  1325. if ((hci_type == RTW_USB || hci_type == RTW_PCIE)
  1326. && !rtw_is_hw_init_completed(adapter))
  1327. rtw_hal_power_on(adapter);
  1328. #endif
  1329. /* inform FW mac hidden rpt from reg is needed */
  1330. rtw_write8(adapter, REG_C2HEVT_MSG_NORMAL, C2H_DEFEATURE_RSVD);
  1331. /* download FW */
  1332. pHalData->not_xmitframe_fw_dl = 1;
  1333. ret_fwdl = rtw_hal_fw_dl(adapter, _FALSE);
  1334. pHalData->not_xmitframe_fw_dl = 0;
  1335. if (ret_fwdl != _SUCCESS)
  1336. goto mac_hidden_rpt_hdl;
  1337. /* polling for data ready */
  1338. start = rtw_get_current_time();
  1339. do {
  1340. cnt++;
  1341. id = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL);
  1342. if (id == C2H_MAC_HIDDEN_RPT || RTW_CANNOT_IO(adapter))
  1343. break;
  1344. rtw_msleep_os(10);
  1345. } while (rtw_get_passing_time_ms(start) < timeout_ms || cnt < min_cnt);
  1346. if (id == C2H_MAC_HIDDEN_RPT) {
  1347. /* read data */
  1348. for (i = 0; i < MAC_HIDDEN_RPT_LEN + MAC_HIDDEN_RPT_2_LEN; i++)
  1349. mac_hidden_rpt[i] = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 2 + i);
  1350. }
  1351. /* inform FW mac hidden rpt has read */
  1352. rtw_write8(adapter, REG_C2HEVT_MSG_NORMAL, C2H_DBG);
  1353. mac_hidden_rpt_hdl:
  1354. c2h_mac_hidden_rpt_hdl(adapter, mac_hidden_rpt, MAC_HIDDEN_RPT_LEN);
  1355. c2h_mac_hidden_rpt_2_hdl(adapter, mac_hidden_rpt + MAC_HIDDEN_RPT_LEN, MAC_HIDDEN_RPT_2_LEN);
  1356. if (ret_fwdl == _SUCCESS && id == C2H_MAC_HIDDEN_RPT)
  1357. ret = _SUCCESS;
  1358. exit:
  1359. #if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
  1360. if ((hci_type == RTW_USB || hci_type == RTW_PCIE)
  1361. && !rtw_is_hw_init_completed(adapter))
  1362. rtw_hal_power_off(adapter);
  1363. #endif
  1364. RTW_INFO("%s %s! (%u, %dms), fwdl:%d, id:0x%02x\n", __func__
  1365. , (ret == _SUCCESS) ? "OK" : "Fail", cnt, rtw_get_passing_time_ms(start), ret_fwdl, id);
  1366. return ret;
  1367. }
  1368. #endif /* CONFIG_RTW_MAC_HIDDEN_RPT */
  1369. int c2h_defeature_dbg_hdl(_adapter *adapter, u8 *data, u8 len)
  1370. {
  1371. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
  1372. struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
  1373. int ret = _FAIL;
  1374. int i;
  1375. if (len < DEFEATURE_DBG_LEN) {
  1376. RTW_WARN("%s len(%u) < %d\n", __func__, len, DEFEATURE_DBG_LEN);
  1377. goto exit;
  1378. }
  1379. for (i = 0; i < len; i++)
  1380. RTW_PRINT("%s: 0x%02X\n", __func__, *(data + i));
  1381. ret = _SUCCESS;
  1382. exit:
  1383. return ret;
  1384. }
  1385. #ifndef DBG_CUSTOMER_STR_RPT_HANDLE
  1386. #define DBG_CUSTOMER_STR_RPT_HANDLE 0
  1387. #endif
  1388. #ifdef CONFIG_RTW_CUSTOMER_STR
  1389. s32 rtw_hal_h2c_customer_str_req(_adapter *adapter)
  1390. {
  1391. u8 h2c_data[H2C_CUSTOMER_STR_REQ_LEN] = {0};
  1392. SET_H2CCMD_CUSTOMER_STR_REQ_EN(h2c_data, 1);
  1393. return rtw_hal_fill_h2c_cmd(adapter, H2C_CUSTOMER_STR_REQ, H2C_CUSTOMER_STR_REQ_LEN, h2c_data);
  1394. }
  1395. #define C2H_CUSTOMER_STR_RPT_BYTE0(_data) ((u8 *)(_data))
  1396. #define C2H_CUSTOMER_STR_RPT_2_BYTE8(_data) ((u8 *)(_data))
  1397. int c2h_customer_str_rpt_hdl(_adapter *adapter, u8 *data, u8 len)
  1398. {
  1399. struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
  1400. int ret = _FAIL;
  1401. int i;
  1402. if (len < CUSTOMER_STR_RPT_LEN) {
  1403. RTW_WARN("%s len(%u) < %d\n", __func__, len, CUSTOMER_STR_RPT_LEN);
  1404. goto exit;
  1405. }
  1406. if (DBG_CUSTOMER_STR_RPT_HANDLE)
  1407. RTW_PRINT_DUMP("customer_str_rpt: ", data, CUSTOMER_STR_RPT_LEN);
  1408. _enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
  1409. if (dvobj->customer_str_sctx != NULL) {
  1410. if (dvobj->customer_str_sctx->status != RTW_SCTX_SUBMITTED)
  1411. RTW_WARN("%s invalid sctx.status:%d\n", __func__, dvobj->customer_str_sctx->status);
  1412. _rtw_memcpy(dvobj->customer_str, C2H_CUSTOMER_STR_RPT_BYTE0(data), CUSTOMER_STR_RPT_LEN);
  1413. dvobj->customer_str_sctx->status = RTX_SCTX_CSTR_WAIT_RPT2;
  1414. } else
  1415. RTW_WARN("%s sctx not set\n", __func__);
  1416. _exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
  1417. ret = _SUCCESS;
  1418. exit:
  1419. return ret;
  1420. }
  1421. int c2h_customer_str_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len)
  1422. {
  1423. struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
  1424. int ret = _FAIL;
  1425. int i;
  1426. if (len < CUSTOMER_STR_RPT_2_LEN) {
  1427. RTW_WARN("%s len(%u) < %d\n", __func__, len, CUSTOMER_STR_RPT_2_LEN);
  1428. goto exit;
  1429. }
  1430. if (DBG_CUSTOMER_STR_RPT_HANDLE)
  1431. RTW_PRINT_DUMP("customer_str_rpt_2: ", data, CUSTOMER_STR_RPT_2_LEN);
  1432. _enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
  1433. if (dvobj->customer_str_sctx != NULL) {
  1434. if (dvobj->customer_str_sctx->status != RTX_SCTX_CSTR_WAIT_RPT2)
  1435. RTW_WARN("%s rpt not ready\n", __func__);
  1436. _rtw_memcpy(dvobj->customer_str + CUSTOMER_STR_RPT_LEN, C2H_CUSTOMER_STR_RPT_2_BYTE8(data), CUSTOMER_STR_RPT_2_LEN);
  1437. rtw_sctx_done(&dvobj->customer_str_sctx);
  1438. } else
  1439. RTW_WARN("%s sctx not set\n", __func__);
  1440. _exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
  1441. ret = _SUCCESS;
  1442. exit:
  1443. return ret;
  1444. }
  1445. /* read customer str */
  1446. s32 rtw_hal_customer_str_read(_adapter *adapter, u8 *cs)
  1447. {
  1448. struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
  1449. struct submit_ctx sctx;
  1450. s32 ret = _SUCCESS;
  1451. _enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
  1452. if (dvobj->customer_str_sctx != NULL)
  1453. ret = _FAIL;
  1454. else {
  1455. rtw_sctx_init(&sctx, 2 * 1000);
  1456. dvobj->customer_str_sctx = &sctx;
  1457. }
  1458. _exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
  1459. if (ret == _FAIL) {
  1460. RTW_WARN("%s another handle ongoing\n", __func__);
  1461. goto exit;
  1462. }
  1463. ret = rtw_customer_str_req_cmd(adapter);
  1464. if (ret != _SUCCESS) {
  1465. RTW_WARN("%s read cmd fail\n", __func__);
  1466. _enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
  1467. dvobj->customer_str_sctx = NULL;
  1468. _exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
  1469. goto exit;
  1470. }
  1471. /* wait till rpt done or timeout */
  1472. rtw_sctx_wait(&sctx, __func__);
  1473. _enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
  1474. dvobj->customer_str_sctx = NULL;
  1475. if (sctx.status == RTW_SCTX_DONE_SUCCESS)
  1476. _rtw_memcpy(cs, dvobj->customer_str, RTW_CUSTOMER_STR_LEN);
  1477. else
  1478. ret = _FAIL;
  1479. _exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
  1480. exit:
  1481. return ret;
  1482. }
  1483. s32 rtw_hal_h2c_customer_str_write(_adapter *adapter, const u8 *cs)
  1484. {
  1485. u8 h2c_data_w1[H2C_CUSTOMER_STR_W1_LEN] = {0};
  1486. u8 h2c_data_w2[H2C_CUSTOMER_STR_W2_LEN] = {0};
  1487. u8 h2c_data_w3[H2C_CUSTOMER_STR_W3_LEN] = {0};
  1488. s32 ret;
  1489. SET_H2CCMD_CUSTOMER_STR_W1_EN(h2c_data_w1, 1);
  1490. _rtw_memcpy(H2CCMD_CUSTOMER_STR_W1_BYTE0(h2c_data_w1), cs, 6);
  1491. SET_H2CCMD_CUSTOMER_STR_W2_EN(h2c_data_w2, 1);
  1492. _rtw_memcpy(H2CCMD_CUSTOMER_STR_W2_BYTE6(h2c_data_w2), cs + 6, 6);
  1493. SET_H2CCMD_CUSTOMER_STR_W3_EN(h2c_data_w3, 1);
  1494. _rtw_memcpy(H2CCMD_CUSTOMER_STR_W3_BYTE12(h2c_data_w3), cs + 6 + 6, 4);
  1495. ret = rtw_hal_fill_h2c_cmd(adapter, H2C_CUSTOMER_STR_W1, H2C_CUSTOMER_STR_W1_LEN, h2c_data_w1);
  1496. if (ret != _SUCCESS) {
  1497. RTW_WARN("%s w1 fail\n", __func__);
  1498. goto exit;
  1499. }
  1500. ret = rtw_hal_fill_h2c_cmd(adapter, H2C_CUSTOMER_STR_W2, H2C_CUSTOMER_STR_W2_LEN, h2c_data_w2);
  1501. if (ret != _SUCCESS) {
  1502. RTW_WARN("%s w2 fail\n", __func__);
  1503. goto exit;
  1504. }
  1505. ret = rtw_hal_fill_h2c_cmd(adapter, H2C_CUSTOMER_STR_W3, H2C_CUSTOMER_STR_W3_LEN, h2c_data_w3);
  1506. if (ret != _SUCCESS) {
  1507. RTW_WARN("%s w3 fail\n", __func__);
  1508. goto exit;
  1509. }
  1510. exit:
  1511. return ret;
  1512. }
  1513. /* write customer str and check if value reported is the same as requested */
  1514. s32 rtw_hal_customer_str_write(_adapter *adapter, const u8 *cs)
  1515. {
  1516. struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
  1517. struct submit_ctx sctx;
  1518. s32 ret = _SUCCESS;
  1519. _enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
  1520. if (dvobj->customer_str_sctx != NULL)
  1521. ret = _FAIL;
  1522. else {
  1523. rtw_sctx_init(&sctx, 2 * 1000);
  1524. dvobj->customer_str_sctx = &sctx;
  1525. }
  1526. _exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
  1527. if (ret == _FAIL) {
  1528. RTW_WARN("%s another handle ongoing\n", __func__);
  1529. goto exit;
  1530. }
  1531. ret = rtw_customer_str_write_cmd(adapter, cs);
  1532. if (ret != _SUCCESS) {
  1533. RTW_WARN("%s write cmd fail\n", __func__);
  1534. _enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
  1535. dvobj->customer_str_sctx = NULL;
  1536. _exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
  1537. goto exit;
  1538. }
  1539. ret = rtw_customer_str_req_cmd(adapter);
  1540. if (ret != _SUCCESS) {
  1541. RTW_WARN("%s read cmd fail\n", __func__);
  1542. _enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
  1543. dvobj->customer_str_sctx = NULL;
  1544. _exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
  1545. goto exit;
  1546. }
  1547. /* wait till rpt done or timeout */
  1548. rtw_sctx_wait(&sctx, __func__);
  1549. _enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
  1550. dvobj->customer_str_sctx = NULL;
  1551. if (sctx.status == RTW_SCTX_DONE_SUCCESS) {
  1552. if (_rtw_memcmp(cs, dvobj->customer_str, RTW_CUSTOMER_STR_LEN) != _TRUE) {
  1553. RTW_WARN("%s read back check fail\n", __func__);
  1554. RTW_INFO_DUMP("write req: ", cs, RTW_CUSTOMER_STR_LEN);
  1555. RTW_INFO_DUMP("read back: ", dvobj->customer_str, RTW_CUSTOMER_STR_LEN);
  1556. ret = _FAIL;
  1557. }
  1558. } else
  1559. ret = _FAIL;
  1560. _exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
  1561. exit:
  1562. return ret;
  1563. }
  1564. #endif /* CONFIG_RTW_CUSTOMER_STR */
  1565. u8 rtw_hal_networktype_to_raid(_adapter *adapter, struct sta_info *psta)
  1566. {
  1567. #ifdef CONFIG_GET_RAID_BY_DRV /*Just for 8188E now*/
  1568. if (IS_NEW_GENERATION_IC(adapter))
  1569. return networktype_to_raid_ex(adapter, psta);
  1570. else
  1571. return networktype_to_raid(adapter, psta);
  1572. #else
  1573. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
  1574. u8 bw;
  1575. bw = rtw_get_tx_bw_mode(adapter, psta);
  1576. return phydm_rate_id_mapping(&pHalData->odmpriv, psta->wireless_mode, pHalData->rf_type, bw);
  1577. #endif
  1578. }
  1579. u8 rtw_get_mgntframe_raid(_adapter *adapter, unsigned char network_type)
  1580. {
  1581. u8 raid;
  1582. if (IS_NEW_GENERATION_IC(adapter)) {
  1583. raid = (network_type & WIRELESS_11B) ? RATEID_IDX_B
  1584. : RATEID_IDX_G;
  1585. } else {
  1586. raid = (network_type & WIRELESS_11B) ? RATR_INX_WIRELESS_B
  1587. : RATR_INX_WIRELESS_G;
  1588. }
  1589. return raid;
  1590. }
  1591. void rtw_hal_update_sta_rate_mask(PADAPTER padapter, struct sta_info *psta)
  1592. {
  1593. struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
  1594. u8 i, rf_type, tx_nss;
  1595. u64 tx_ra_bitmap;
  1596. if (psta == NULL)
  1597. return;
  1598. tx_ra_bitmap = 0;
  1599. /* b/g mode ra_bitmap */
  1600. for (i = 0; i < sizeof(psta->bssrateset); i++) {
  1601. if (psta->bssrateset[i])
  1602. tx_ra_bitmap |= rtw_get_bit_value_from_ieee_value(psta->bssrateset[i] & 0x7f);
  1603. }
  1604. #ifdef CONFIG_80211N_HT
  1605. rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
  1606. tx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num);
  1607. #ifdef CONFIG_80211AC_VHT
  1608. if (psta->vhtpriv.vht_option) {
  1609. /* AC mode ra_bitmap */
  1610. tx_ra_bitmap |= (rtw_vht_mcs_map_to_bitmap(psta->vhtpriv.vht_mcs_map, tx_nss) << 12);
  1611. } else
  1612. #endif /* CONFIG_80211AC_VHT */
  1613. if (psta->htpriv.ht_option) {
  1614. /* n mode ra_bitmap */
  1615. /* Handling SMPS mode for AP MODE only*/
  1616. if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) {
  1617. /*0:static SMPS, 1:dynamic SMPS, 3:SMPS disabled, 2:reserved*/
  1618. if (psta->htpriv.smps_cap == 0 || psta->htpriv.smps_cap == 1) {
  1619. /*operate with only one active receive chain // 11n-MCS rate <= MSC7*/
  1620. tx_nss = rtw_min(tx_nss, 1);
  1621. }
  1622. }
  1623. tx_ra_bitmap |= (rtw_ht_mcs_set_to_bitmap(psta->htpriv.ht_cap.supp_mcs_set, tx_nss) << 12);
  1624. }
  1625. #endif /* CONFIG_80211N_HT */
  1626. psta->ra_mask = tx_ra_bitmap;
  1627. psta->init_rate = get_highest_rate_idx(tx_ra_bitmap) & 0x3f;
  1628. }
  1629. #ifndef SEC_CAM_ACCESS_TIMEOUT_MS
  1630. #define SEC_CAM_ACCESS_TIMEOUT_MS 200
  1631. #endif
  1632. #ifndef DBG_SEC_CAM_ACCESS
  1633. #define DBG_SEC_CAM_ACCESS 0
  1634. #endif
  1635. u32 rtw_sec_read_cam(_adapter *adapter, u8 addr)
  1636. {
  1637. _mutex *mutex = &adapter_to_dvobj(adapter)->cam_ctl.sec_cam_access_mutex;
  1638. u32 rdata;
  1639. u32 cnt = 0;
  1640. u32 start = 0, end = 0;
  1641. u8 timeout = 0;
  1642. u8 sr = 0;
  1643. _enter_critical_mutex(mutex, NULL);
  1644. rtw_write32(adapter, REG_CAMCMD, CAM_POLLINIG | addr);
  1645. start = rtw_get_current_time();
  1646. while (1) {
  1647. if (rtw_is_surprise_removed(adapter)) {
  1648. sr = 1;
  1649. break;
  1650. }
  1651. cnt++;
  1652. if (0 == (rtw_read32(adapter, REG_CAMCMD) & CAM_POLLINIG))
  1653. break;
  1654. if (rtw_get_passing_time_ms(start) > SEC_CAM_ACCESS_TIMEOUT_MS) {
  1655. timeout = 1;
  1656. break;
  1657. }
  1658. }
  1659. end = rtw_get_current_time();
  1660. rdata = rtw_read32(adapter, REG_CAMREAD);
  1661. _exit_critical_mutex(mutex, NULL);
  1662. if (DBG_SEC_CAM_ACCESS || timeout) {
  1663. RTW_INFO(FUNC_ADPT_FMT" addr:0x%02x, rdata:0x%08x, to:%u, polling:%u, %d ms\n"
  1664. , FUNC_ADPT_ARG(adapter), addr, rdata, timeout, cnt, rtw_get_time_interval_ms(start, end));
  1665. }
  1666. return rdata;
  1667. }
  1668. void rtw_sec_write_cam(_adapter *adapter, u8 addr, u32 wdata)
  1669. {
  1670. _mutex *mutex = &adapter_to_dvobj(adapter)->cam_ctl.sec_cam_access_mutex;
  1671. u32 cnt = 0;
  1672. u32 start = 0, end = 0;
  1673. u8 timeout = 0;
  1674. u8 sr = 0;
  1675. _enter_critical_mutex(mutex, NULL);
  1676. rtw_write32(adapter, REG_CAMWRITE, wdata);
  1677. rtw_write32(adapter, REG_CAMCMD, CAM_POLLINIG | CAM_WRITE | addr);
  1678. start = rtw_get_current_time();
  1679. while (1) {
  1680. if (rtw_is_surprise_removed(adapter)) {
  1681. sr = 1;
  1682. break;
  1683. }
  1684. cnt++;
  1685. if (0 == (rtw_read32(adapter, REG_CAMCMD) & CAM_POLLINIG))
  1686. break;
  1687. if (rtw_get_passing_time_ms(start) > SEC_CAM_ACCESS_TIMEOUT_MS) {
  1688. timeout = 1;
  1689. break;
  1690. }
  1691. }
  1692. end = rtw_get_current_time();
  1693. _exit_critical_mutex(mutex, NULL);
  1694. if (DBG_SEC_CAM_ACCESS || timeout) {
  1695. RTW_INFO(FUNC_ADPT_FMT" addr:0x%02x, wdata:0x%08x, to:%u, polling:%u, %d ms\n"
  1696. , FUNC_ADPT_ARG(adapter), addr, wdata, timeout, cnt, rtw_get_time_interval_ms(start, end));
  1697. }
  1698. }
  1699. void rtw_sec_read_cam_ent(_adapter *adapter, u8 id, u8 *ctrl, u8 *mac, u8 *key)
  1700. {
  1701. unsigned int val, addr;
  1702. u8 i;
  1703. u32 rdata;
  1704. u8 begin = 0;
  1705. u8 end = 5; /* TODO: consider other key length accordingly */
  1706. if (!ctrl && !mac && !key) {
  1707. rtw_warn_on(1);
  1708. goto exit;
  1709. }
  1710. /* TODO: check id range */
  1711. if (!ctrl && !mac)
  1712. begin = 2; /* read from key */
  1713. if (!key && !mac)
  1714. end = 0; /* read to ctrl */
  1715. else if (!key)
  1716. end = 2; /* read to mac */
  1717. for (i = begin; i <= end; i++) {
  1718. rdata = rtw_sec_read_cam(adapter, (id << 3) | i);
  1719. switch (i) {
  1720. case 0:
  1721. if (ctrl)
  1722. _rtw_memcpy(ctrl, (u8 *)(&rdata), 2);
  1723. if (mac)
  1724. _rtw_memcpy(mac, ((u8 *)(&rdata)) + 2, 2);
  1725. break;
  1726. case 1:
  1727. if (mac)
  1728. _rtw_memcpy(mac + 2, (u8 *)(&rdata), 4);
  1729. break;
  1730. default:
  1731. if (key)
  1732. _rtw_memcpy(key + (i - 2) * 4, (u8 *)(&rdata), 4);
  1733. break;
  1734. }
  1735. }
  1736. exit:
  1737. return;
  1738. }
  1739. void rtw_sec_write_cam_ent(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key)
  1740. {
  1741. unsigned int i;
  1742. int j;
  1743. u8 addr;
  1744. u32 wdata;
  1745. /* TODO: consider other key length accordingly */
  1746. #if 0
  1747. switch ((ctrl & 0x1c) >> 2) {
  1748. case _WEP40_:
  1749. case _TKIP_:
  1750. case _AES_:
  1751. case _WEP104_:
  1752. }
  1753. #else
  1754. j = 7;
  1755. #endif
  1756. for (; j >= 0; j--) {
  1757. switch (j) {
  1758. case 0:
  1759. wdata = (ctrl | (mac[0] << 16) | (mac[1] << 24));
  1760. break;
  1761. case 1:
  1762. wdata = (mac[2] | (mac[3] << 8) | (mac[4] << 16) | (mac[5] << 24));
  1763. break;
  1764. case 6:
  1765. case 7:
  1766. wdata = 0;
  1767. break;
  1768. default:
  1769. i = (j - 2) << 2;
  1770. wdata = (key[i] | (key[i + 1] << 8) | (key[i + 2] << 16) | (key[i + 3] << 24));
  1771. break;
  1772. }
  1773. addr = (id << 3) + j;
  1774. rtw_sec_write_cam(adapter, addr, wdata);
  1775. }
  1776. }
  1777. void rtw_sec_clr_cam_ent(_adapter *adapter, u8 id)
  1778. {
  1779. u8 addr;
  1780. addr = (id << 3);
  1781. rtw_sec_write_cam(adapter, addr, 0);
  1782. }
  1783. bool rtw_sec_read_cam_is_gk(_adapter *adapter, u8 id)
  1784. {
  1785. bool res;
  1786. u16 ctrl;
  1787. rtw_sec_read_cam_ent(adapter, id, (u8 *)&ctrl, NULL, NULL);
  1788. res = (ctrl & BIT6) ? _TRUE : _FALSE;
  1789. return res;
  1790. }
  1791. #ifdef CONFIG_MBSSID_CAM
  1792. void rtw_mbid_cam_init(struct dvobj_priv *dvobj)
  1793. {
  1794. struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
  1795. _rtw_spinlock_init(&mbid_cam_ctl->lock);
  1796. mbid_cam_ctl->bitmap = 0;
  1797. ATOMIC_SET(&mbid_cam_ctl->mbid_entry_num, 0);
  1798. _rtw_memset(&dvobj->mbid_cam_cache, 0, sizeof(dvobj->mbid_cam_cache));
  1799. }
  1800. void rtw_mbid_cam_deinit(struct dvobj_priv *dvobj)
  1801. {
  1802. struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
  1803. _rtw_spinlock_free(&mbid_cam_ctl->lock);
  1804. }
  1805. void rtw_mbid_cam_reset(_adapter *adapter)
  1806. {
  1807. _irqL irqL;
  1808. struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
  1809. struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
  1810. _enter_critical_bh(&mbid_cam_ctl->lock, &irqL);
  1811. mbid_cam_ctl->bitmap = 0;
  1812. _rtw_memset(&dvobj->mbid_cam_cache, 0, sizeof(dvobj->mbid_cam_cache));
  1813. _exit_critical_bh(&mbid_cam_ctl->lock, &irqL);
  1814. ATOMIC_SET(&mbid_cam_ctl->mbid_entry_num, 0);
  1815. }
  1816. static u8 _rtw_mbid_cam_search_by_macaddr(_adapter *adapter, u8 *mac_addr)
  1817. {
  1818. u8 i;
  1819. u8 cam_id = INVALID_CAM_ID;
  1820. struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
  1821. for (i = 0; i < TOTAL_MBID_CAM_NUM; i++) {
  1822. if (mac_addr && _rtw_memcmp(dvobj->mbid_cam_cache[i].mac_addr, mac_addr, ETH_ALEN) == _TRUE) {
  1823. cam_id = i;
  1824. break;
  1825. }
  1826. }
  1827. RTW_INFO("%s mac:"MAC_FMT" - cam_id:%d\n", __func__, MAC_ARG(mac_addr), cam_id);
  1828. return cam_id;
  1829. }
  1830. u8 rtw_mbid_cam_search_by_macaddr(_adapter *adapter, u8 *mac_addr)
  1831. {
  1832. _irqL irqL;
  1833. u8 cam_id = INVALID_CAM_ID;
  1834. struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
  1835. struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
  1836. _enter_critical_bh(&mbid_cam_ctl->lock, &irqL);
  1837. cam_id = _rtw_mbid_cam_search_by_macaddr(adapter, mac_addr);
  1838. _exit_critical_bh(&mbid_cam_ctl->lock, &irqL);
  1839. return cam_id;
  1840. }
  1841. static u8 _rtw_mbid_cam_search_by_ifaceid(_adapter *adapter, u8 iface_id)
  1842. {
  1843. u8 i;
  1844. u8 cam_id = INVALID_CAM_ID;
  1845. struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
  1846. for (i = 0; i < TOTAL_MBID_CAM_NUM; i++) {
  1847. if (iface_id == dvobj->mbid_cam_cache[i].iface_id) {
  1848. cam_id = i;
  1849. break;
  1850. }
  1851. }
  1852. if (cam_id != INVALID_CAM_ID)
  1853. RTW_INFO("%s iface_id:%d mac:"MAC_FMT" - cam_id:%d\n",
  1854. __func__, iface_id, MAC_ARG(dvobj->mbid_cam_cache[cam_id].mac_addr), cam_id);
  1855. return cam_id;
  1856. }
  1857. u8 rtw_mbid_cam_search_by_ifaceid(_adapter *adapter, u8 iface_id)
  1858. {
  1859. _irqL irqL;
  1860. u8 cam_id = INVALID_CAM_ID;
  1861. struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
  1862. struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
  1863. _enter_critical_bh(&mbid_cam_ctl->lock, &irqL);
  1864. cam_id = _rtw_mbid_cam_search_by_ifaceid(adapter, iface_id);
  1865. _exit_critical_bh(&mbid_cam_ctl->lock, &irqL);
  1866. return cam_id;
  1867. }
  1868. u8 rtw_get_max_mbid_cam_id(_adapter *adapter)
  1869. {
  1870. _irqL irqL;
  1871. s8 i;
  1872. u8 cam_id = INVALID_CAM_ID;
  1873. struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
  1874. struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
  1875. _enter_critical_bh(&mbid_cam_ctl->lock, &irqL);
  1876. for (i = (TOTAL_MBID_CAM_NUM - 1); i >= 0; i--) {
  1877. if (mbid_cam_ctl->bitmap & BIT(i)) {
  1878. cam_id = i;
  1879. break;
  1880. }
  1881. }
  1882. _exit_critical_bh(&mbid_cam_ctl->lock, &irqL);
  1883. /*RTW_INFO("%s max cam_id:%d\n", __func__, cam_id);*/
  1884. return cam_id;
  1885. }
  1886. inline u8 rtw_get_mbid_cam_entry_num(_adapter *adapter)
  1887. {
  1888. struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
  1889. struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
  1890. return ATOMIC_READ(&mbid_cam_ctl->mbid_entry_num);
  1891. }
  1892. static inline void mbid_cam_cache_init(_adapter *adapter, struct mbid_cam_cache *pmbid_cam, u8 *mac_addr)
  1893. {
  1894. if (adapter && pmbid_cam && mac_addr) {
  1895. _rtw_memcpy(pmbid_cam->mac_addr, mac_addr, ETH_ALEN);
  1896. pmbid_cam->iface_id = adapter->iface_id;
  1897. }
  1898. }
  1899. static inline void mbid_cam_cache_clr(struct mbid_cam_cache *pmbid_cam)
  1900. {
  1901. if (pmbid_cam) {
  1902. _rtw_memset(pmbid_cam->mac_addr, 0, ETH_ALEN);
  1903. pmbid_cam->iface_id = CONFIG_IFACE_NUMBER;
  1904. }
  1905. }
  1906. u8 rtw_mbid_camid_alloc(_adapter *adapter, u8 *mac_addr)
  1907. {
  1908. _irqL irqL;
  1909. u8 cam_id = INVALID_CAM_ID, i;
  1910. struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
  1911. struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
  1912. u8 entry_num = ATOMIC_READ(&mbid_cam_ctl->mbid_entry_num);
  1913. if (entry_num >= TOTAL_MBID_CAM_NUM) {
  1914. RTW_INFO(FUNC_ADPT_FMT" failed !! MBSSID number :%d over TOTAL_CAM_ENTRY(8)\n", FUNC_ADPT_ARG(adapter), entry_num);
  1915. rtw_warn_on(1);
  1916. }
  1917. if (INVALID_CAM_ID != rtw_mbid_cam_search_by_macaddr(adapter, mac_addr))
  1918. goto exit;
  1919. _enter_critical_bh(&mbid_cam_ctl->lock, &irqL);
  1920. for (i = 0; i < TOTAL_MBID_CAM_NUM; i++) {
  1921. if (!(mbid_cam_ctl->bitmap & BIT(i))) {
  1922. mbid_cam_ctl->bitmap |= BIT(i);
  1923. cam_id = i;
  1924. break;
  1925. }
  1926. }
  1927. if ((cam_id != INVALID_CAM_ID) && (mac_addr))
  1928. mbid_cam_cache_init(adapter, &dvobj->mbid_cam_cache[cam_id], mac_addr);
  1929. _exit_critical_bh(&mbid_cam_ctl->lock, &irqL);
  1930. if (cam_id != INVALID_CAM_ID) {
  1931. ATOMIC_INC(&mbid_cam_ctl->mbid_entry_num);
  1932. RTW_INFO("%s mac:"MAC_FMT" - cam_id:%d\n", __func__, MAC_ARG(mac_addr), cam_id);
  1933. #ifdef DBG_MBID_CAM_DUMP
  1934. rtw_mbid_cam_cache_dump(RTW_DBGDUMP, __func__, adapter);
  1935. #endif
  1936. } else
  1937. RTW_INFO("%s [WARN] "MAC_FMT" - invalid cam_id:%d\n", __func__, MAC_ARG(mac_addr), cam_id);
  1938. exit:
  1939. return cam_id;
  1940. }
  1941. u8 rtw_mbid_cam_info_change(_adapter *adapter, u8 *mac_addr)
  1942. {
  1943. _irqL irqL;
  1944. u8 entry_id = INVALID_CAM_ID;
  1945. struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
  1946. struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
  1947. _enter_critical_bh(&mbid_cam_ctl->lock, &irqL);
  1948. entry_id = _rtw_mbid_cam_search_by_ifaceid(adapter, adapter->iface_id);
  1949. if (entry_id != INVALID_CAM_ID)
  1950. mbid_cam_cache_init(adapter, &dvobj->mbid_cam_cache[entry_id], mac_addr);
  1951. _exit_critical_bh(&mbid_cam_ctl->lock, &irqL);
  1952. return entry_id;
  1953. }
  1954. u8 rtw_mbid_cam_assign(_adapter *adapter, u8 *mac_addr, u8 camid)
  1955. {
  1956. _irqL irqL;
  1957. u8 ret = _FALSE;
  1958. struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
  1959. struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
  1960. if ((camid >= TOTAL_MBID_CAM_NUM) || (camid == INVALID_CAM_ID)) {
  1961. RTW_INFO(FUNC_ADPT_FMT" failed !! invlaid mbid_canid :%d\n", FUNC_ADPT_ARG(adapter), camid);
  1962. rtw_warn_on(1);
  1963. }
  1964. if (INVALID_CAM_ID != rtw_mbid_cam_search_by_macaddr(adapter, mac_addr))
  1965. goto exit;
  1966. _enter_critical_bh(&mbid_cam_ctl->lock, &irqL);
  1967. if (!(mbid_cam_ctl->bitmap & BIT(camid))) {
  1968. if (mac_addr) {
  1969. mbid_cam_ctl->bitmap |= BIT(camid);
  1970. mbid_cam_cache_init(adapter, &dvobj->mbid_cam_cache[camid], mac_addr);
  1971. ret = _TRUE;
  1972. }
  1973. }
  1974. _exit_critical_bh(&mbid_cam_ctl->lock, &irqL);
  1975. if (ret == _TRUE) {
  1976. ATOMIC_INC(&mbid_cam_ctl->mbid_entry_num);
  1977. RTW_INFO("%s mac:"MAC_FMT" - cam_id:%d\n", __func__, MAC_ARG(mac_addr), camid);
  1978. #ifdef DBG_MBID_CAM_DUMP
  1979. rtw_mbid_cam_cache_dump(RTW_DBGDUMP, __func__, adapter);
  1980. #endif
  1981. } else
  1982. RTW_INFO("%s [WARN] mac:"MAC_FMT" - cam_id:%d assigned failed\n", __func__, MAC_ARG(mac_addr), camid);
  1983. exit:
  1984. return ret;
  1985. }
  1986. void rtw_mbid_camid_clean(_adapter *adapter, u8 mbss_canid)
  1987. {
  1988. _irqL irqL;
  1989. struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
  1990. struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
  1991. if ((mbss_canid >= TOTAL_MBID_CAM_NUM) || (mbss_canid == INVALID_CAM_ID)) {
  1992. RTW_INFO(FUNC_ADPT_FMT" failed !! invlaid mbid_canid :%d\n", FUNC_ADPT_ARG(adapter), mbss_canid);
  1993. rtw_warn_on(1);
  1994. }
  1995. _enter_critical_bh(&mbid_cam_ctl->lock, &irqL);
  1996. mbid_cam_cache_clr(&dvobj->mbid_cam_cache[mbss_canid]);
  1997. mbid_cam_ctl->bitmap &= (~BIT(mbss_canid));
  1998. _exit_critical_bh(&mbid_cam_ctl->lock, &irqL);
  1999. ATOMIC_DEC(&mbid_cam_ctl->mbid_entry_num);
  2000. RTW_INFO("%s - cam_id:%d\n", __func__, mbss_canid);
  2001. }
  2002. int rtw_mbid_cam_cache_dump(void *sel, const char *fun_name, _adapter *adapter)
  2003. {
  2004. _irqL irqL;
  2005. u8 i;
  2006. _adapter *iface;
  2007. u8 iface_id;
  2008. struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
  2009. struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
  2010. u8 entry_num = ATOMIC_READ(&mbid_cam_ctl->mbid_entry_num);
  2011. u8 max_cam_id = rtw_get_max_mbid_cam_id(adapter);
  2012. RTW_PRINT_SEL(sel, "== MBSSID CAM DUMP (%s)==\n", fun_name);
  2013. _enter_critical_bh(&mbid_cam_ctl->lock, &irqL);
  2014. RTW_PRINT_SEL(sel, "Entry numbers:%d, max_camid:%d, bitmap:0x%08x\n", entry_num, max_cam_id, mbid_cam_ctl->bitmap);
  2015. for (i = 0; i < TOTAL_MBID_CAM_NUM; i++) {
  2016. RTW_PRINT_SEL(sel, "CAM_ID = %d\t", i);
  2017. if (mbid_cam_ctl->bitmap & BIT(i)) {
  2018. iface_id = dvobj->mbid_cam_cache[i].iface_id;
  2019. RTW_PRINT_SEL(sel, "IF_ID:%d\t", iface_id);
  2020. RTW_PRINT_SEL(sel, "MAC Addr:"MAC_FMT"\t", MAC_ARG(dvobj->mbid_cam_cache[i].mac_addr));
  2021. iface = dvobj->padapters[iface_id];
  2022. if (iface) {
  2023. if (check_fwstate(&iface->mlmepriv, WIFI_STATION_STATE) == _TRUE)
  2024. RTW_PRINT_SEL(sel, "ROLE:%s\n", "STA");
  2025. else if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE)
  2026. RTW_PRINT_SEL(sel, "ROLE:%s\n", "AP");
  2027. else
  2028. RTW_PRINT_SEL(sel, "ROLE:%s\n", "NONE");
  2029. }
  2030. } else
  2031. RTW_PRINT_SEL(sel, "N/A\n");
  2032. }
  2033. _exit_critical_bh(&mbid_cam_ctl->lock, &irqL);
  2034. return 0;
  2035. }
  2036. static void read_mbssid_cam(_adapter *padapter, u8 cam_addr, u8 *mac)
  2037. {
  2038. u8 poll = 1;
  2039. u8 cam_ready = _FALSE;
  2040. u32 cam_data1 = 0;
  2041. u16 cam_data2 = 0;
  2042. if (RTW_CANNOT_RUN(padapter))
  2043. return;
  2044. rtw_write32(padapter, REG_MBIDCAMCFG_2, BIT_MBIDCAM_POLL | ((cam_addr & MBIDCAM_ADDR_MASK) << MBIDCAM_ADDR_SHIFT));
  2045. do {
  2046. if (0 == (rtw_read32(padapter, REG_MBIDCAMCFG_2) & BIT_MBIDCAM_POLL)) {
  2047. cam_ready = _TRUE;
  2048. break;
  2049. }
  2050. poll++;
  2051. } while ((poll % 10) != 0 && !RTW_CANNOT_RUN(padapter));
  2052. if (cam_ready) {
  2053. cam_data1 = rtw_read32(padapter, REG_MBIDCAMCFG_1);
  2054. mac[0] = cam_data1 & 0xFF;
  2055. mac[1] = (cam_data1 >> 8) & 0xFF;
  2056. mac[2] = (cam_data1 >> 16) & 0xFF;
  2057. mac[3] = (cam_data1 >> 24) & 0xFF;
  2058. cam_data2 = rtw_read16(padapter, REG_MBIDCAMCFG_2);
  2059. mac[4] = cam_data2 & 0xFF;
  2060. mac[5] = (cam_data2 >> 8) & 0xFF;
  2061. }
  2062. }
  2063. int rtw_mbid_cam_dump(void *sel, const char *fun_name, _adapter *adapter)
  2064. {
  2065. /*_irqL irqL;*/
  2066. u8 i;
  2067. u8 mac_addr[ETH_ALEN];
  2068. struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
  2069. struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
  2070. RTW_PRINT_SEL(sel, "\n== MBSSID HW-CAM DUMP (%s)==\n", fun_name);
  2071. /*_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);*/
  2072. for (i = 0; i < TOTAL_MBID_CAM_NUM; i++) {
  2073. RTW_PRINT_SEL(sel, "CAM_ID = %d\t", i);
  2074. _rtw_memset(mac_addr, 0, ETH_ALEN);
  2075. read_mbssid_cam(adapter, i, mac_addr);
  2076. RTW_PRINT_SEL(sel, "MAC Addr:"MAC_FMT"\n", MAC_ARG(mac_addr));
  2077. }
  2078. /*_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);*/
  2079. return 0;
  2080. }
  2081. static void write_mbssid_cam(_adapter *padapter, u8 cam_addr, u8 *mac)
  2082. {
  2083. u32 cam_val[2] = {0};
  2084. cam_val[0] = (mac[3] << 24) | (mac[2] << 16) | (mac[1] << 8) | mac[0];
  2085. cam_val[1] = ((cam_addr & MBIDCAM_ADDR_MASK) << MBIDCAM_ADDR_SHIFT) | (mac[5] << 8) | mac[4];
  2086. rtw_hal_set_hwreg(padapter, HW_VAR_MBSSID_CAM_WRITE, (u8 *)cam_val);
  2087. }
  2088. static void clear_mbssid_cam(_adapter *padapter, u8 cam_addr)
  2089. {
  2090. rtw_hal_set_hwreg(padapter, HW_VAR_MBSSID_CAM_CLEAR, &cam_addr);
  2091. }
  2092. static void enable_mbssid_cam(_adapter *adapter)
  2093. {
  2094. u8 max_cam_id = rtw_get_max_mbid_cam_id(adapter);
  2095. /*enable MBSSID*/
  2096. rtw_write32(adapter, REG_RCR, rtw_read32(adapter, REG_RCR) | RCR_ENMBID);
  2097. if (max_cam_id != INVALID_CAM_ID) {
  2098. rtw_write8(adapter, REG_MBID_NUM,
  2099. ((rtw_read8(adapter, REG_MBID_NUM) & 0xF8) | (max_cam_id & 0x07)));
  2100. }
  2101. }
  2102. void rtw_mbid_cam_restore(_adapter *adapter)
  2103. {
  2104. u8 i;
  2105. struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
  2106. struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
  2107. #ifdef DBG_MBID_CAM_DUMP
  2108. rtw_mbid_cam_cache_dump(RTW_DBGDUMP, __func__, adapter);
  2109. #endif
  2110. for (i = 0; i < TOTAL_MBID_CAM_NUM; i++) {
  2111. if (mbid_cam_ctl->bitmap & BIT(i)) {
  2112. write_mbssid_cam(adapter, i, dvobj->mbid_cam_cache[i].mac_addr);
  2113. RTW_INFO("%s - cam_id:%d => mac:"MAC_FMT"\n", __func__, i, MAC_ARG(dvobj->mbid_cam_cache[i].mac_addr));
  2114. }
  2115. }
  2116. enable_mbssid_cam(adapter);
  2117. }
  2118. #endif /*CONFIG_MBSSID_CAM*/
  2119. #ifdef CONFIG_MI_WITH_MBSSID_CAM
  2120. void rtw_hal_set_macaddr_mbid(_adapter *adapter, u8 *mac_addr)
  2121. {
  2122. #if 0 /*TODO - modify for more flexible*/
  2123. u8 idx = 0;
  2124. if ((check_fwstate(&adapter->mlmepriv, WIFI_STATION_STATE) == _TRUE) &&
  2125. (DEV_STA_NUM(adapter_to_dvobj(adapter)) == 1)) {
  2126. for (idx = 0; idx < 6; idx++)
  2127. rtw_write8(GET_PRIMARY_ADAPTER(adapter), (REG_MACID + idx), val[idx]);
  2128. } else {
  2129. /*MBID entry_id = 0~7 ,0 for root AP, 1~7 for VAP*/
  2130. u8 entry_id;
  2131. if ((check_fwstate(&adapter->mlmepriv, WIFI_AP_STATE) == _TRUE) &&
  2132. (DEV_AP_NUM(adapter_to_dvobj(adapter)) == 1)) {
  2133. entry_id = 0;
  2134. if (rtw_mbid_cam_assign(adapter, val, entry_id)) {
  2135. RTW_INFO(FUNC_ADPT_FMT" Root AP assigned success\n", FUNC_ADPT_ARG(adapter));
  2136. write_mbssid_cam(adapter, entry_id, val);
  2137. }
  2138. } else {
  2139. entry_id = rtw_mbid_camid_alloc(adapter, val);
  2140. if (entry_id != INVALID_CAM_ID)
  2141. write_mbssid_cam(adapter, entry_id, val);
  2142. }
  2143. }
  2144. #else
  2145. {
  2146. /*
  2147. MBID entry_id = 0~7 ,for IFACE_ID0 ~ IFACE_IDx
  2148. */
  2149. u8 entry_id = rtw_mbid_camid_alloc(adapter, mac_addr);
  2150. if (entry_id != INVALID_CAM_ID) {
  2151. write_mbssid_cam(adapter, entry_id, mac_addr);
  2152. enable_mbssid_cam(adapter);
  2153. }
  2154. }
  2155. #endif
  2156. }
  2157. void rtw_hal_change_macaddr_mbid(_adapter *adapter, u8 *mac_addr)
  2158. {
  2159. u8 idx = 0;
  2160. struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
  2161. u8 entry_id;
  2162. if (!mac_addr) {
  2163. rtw_warn_on(1);
  2164. return;
  2165. }
  2166. entry_id = rtw_mbid_cam_info_change(adapter, mac_addr);
  2167. if (entry_id != INVALID_CAM_ID)
  2168. write_mbssid_cam(adapter, entry_id, mac_addr);
  2169. }
  2170. #endif/*#ifdef CONFIG_MI_WITH_MBSSID_CAM*/
  2171. void rtw_hal_set_macaddr_port(_adapter *adapter, u8 *val)
  2172. {
  2173. u8 idx = 0;
  2174. u32 reg_macid = 0;
  2175. if (val == NULL)
  2176. return;
  2177. RTW_INFO("%s "ADPT_FMT"- hw port(%d) mac_addr ="MAC_FMT"\n", __func__,
  2178. ADPT_ARG(adapter), adapter->hw_port, MAC_ARG(val));
  2179. switch (adapter->hw_port) {
  2180. case HW_PORT0:
  2181. default:
  2182. reg_macid = REG_MACID;
  2183. break;
  2184. case HW_PORT1:
  2185. reg_macid = REG_MACID1;
  2186. break;
  2187. #if defined(CONFIG_RTL8814A)
  2188. case HW_PORT2:
  2189. reg_macid = REG_MACID2;
  2190. break;
  2191. case HW_PORT3:
  2192. reg_macid = REG_MACID3;
  2193. break;
  2194. case HW_PORT4:
  2195. reg_macid = REG_MACID4;
  2196. break;
  2197. #endif/*defined(CONFIG_RTL8814A)*/
  2198. }
  2199. for (idx = 0; idx < 6; idx++)
  2200. rtw_write8(GET_PRIMARY_ADAPTER(adapter), (reg_macid + idx), val[idx]);
  2201. }
  2202. void rtw_hal_get_macaddr_port(_adapter *adapter, u8 *mac_addr)
  2203. {
  2204. u8 idx = 0;
  2205. u32 reg_macid = 0;
  2206. if (mac_addr == NULL)
  2207. return;
  2208. _rtw_memset(mac_addr, 0, ETH_ALEN);
  2209. switch (adapter->hw_port) {
  2210. case HW_PORT0:
  2211. default:
  2212. reg_macid = REG_MACID;
  2213. break;
  2214. case HW_PORT1:
  2215. reg_macid = REG_MACID1;
  2216. break;
  2217. #if defined(CONFIG_RTL8814A)
  2218. case HW_PORT2:
  2219. reg_macid = REG_MACID2;
  2220. break;
  2221. case HW_PORT3:
  2222. reg_macid = REG_MACID3;
  2223. break;
  2224. case HW_PORT4:
  2225. reg_macid = REG_MACID4;
  2226. break;
  2227. #endif /*defined(CONFIG_RTL8814A)*/
  2228. }
  2229. for (idx = 0; idx < 6; idx++)
  2230. mac_addr[idx] = rtw_read8(GET_PRIMARY_ADAPTER(adapter), (reg_macid + idx));
  2231. RTW_INFO("%s "ADPT_FMT"- hw port(%d) mac_addr ="MAC_FMT"\n", __func__,
  2232. ADPT_ARG(adapter), adapter->hw_port, MAC_ARG(mac_addr));
  2233. }
  2234. void rtw_hal_set_bssid(_adapter *adapter, u8 *val)
  2235. {
  2236. u8 idx = 0;
  2237. u32 reg_bssid = 0;
  2238. switch (adapter->hw_port) {
  2239. case HW_PORT0:
  2240. default:
  2241. reg_bssid = REG_BSSID;
  2242. break;
  2243. case HW_PORT1:
  2244. reg_bssid = REG_BSSID1;
  2245. break;
  2246. #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B)
  2247. case HW_PORT2:
  2248. reg_bssid = REG_BSSID2;
  2249. break;
  2250. case HW_PORT3:
  2251. reg_bssid = REG_BSSID3;
  2252. break;
  2253. case HW_PORT4:
  2254. reg_bssid = REG_BSSID4;
  2255. break;
  2256. #endif/*defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B)*/
  2257. }
  2258. for (idx = 0 ; idx < 6; idx++)
  2259. rtw_write8(adapter, (reg_bssid + idx), val[idx]);
  2260. RTW_INFO("%s "ADPT_FMT"- hw port -%d BSSID: "MAC_FMT"\n", __func__, ADPT_ARG(adapter), adapter->hw_port, MAC_ARG(val));
  2261. }
  2262. void rtw_hal_get_msr(_adapter *adapter, u8 *net_type)
  2263. {
  2264. switch (adapter->hw_port) {
  2265. case HW_PORT0:
  2266. /*REG_CR - BIT[17:16]-Network Type for port 1*/
  2267. *net_type = rtw_read8(adapter, MSR) & 0x03;
  2268. break;
  2269. case HW_PORT1:
  2270. /*REG_CR - BIT[19:18]-Network Type for port 1*/
  2271. *net_type = (rtw_read8(adapter, MSR) & 0x0C) >> 2;
  2272. break;
  2273. #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B)
  2274. case HW_PORT2:
  2275. /*REG_CR_EXT- BIT[1:0]-Network Type for port 2*/
  2276. *net_type = rtw_read8(adapter, MSR1) & 0x03;
  2277. break;
  2278. case HW_PORT3:
  2279. /*REG_CR_EXT- BIT[3:2]-Network Type for port 3*/
  2280. *net_type = (rtw_read8(adapter, MSR1) & 0x0C) >> 2;
  2281. break;
  2282. case HW_PORT4:
  2283. /*REG_CR_EXT- BIT[5:4]-Network Type for port 4*/
  2284. *net_type = (rtw_read8(adapter, MSR1) & 0x30) >> 4;
  2285. break;
  2286. #endif /*#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B)*/
  2287. default:
  2288. RTW_INFO("[WARN] "ADPT_FMT"- invalid hw port -%d\n",
  2289. ADPT_ARG(adapter), adapter->hw_port);
  2290. rtw_warn_on(1);
  2291. break;
  2292. }
  2293. }
  2294. void rtw_hal_set_msr(_adapter *adapter, u8 net_type)
  2295. {
  2296. u8 val8 = 0;
  2297. switch (adapter->hw_port) {
  2298. case HW_PORT0:
  2299. #if defined(CONFIG_MI_WITH_MBSSID_CAM) && defined(CONFIG_MBSSID_CAM) /*For 2 hw ports - 88E/92E/8812/8821/8723B*/
  2300. if (rtw_get_mbid_cam_entry_num(adapter)) {
  2301. if (net_type != _HW_STATE_NOLINK_)
  2302. net_type = _HW_STATE_AP_;
  2303. }
  2304. #endif
  2305. /*REG_CR - BIT[17:16]-Network Type for port 0*/
  2306. val8 = rtw_read8(adapter, MSR) & 0x0C;
  2307. val8 |= net_type;
  2308. rtw_write8(adapter, MSR, val8);
  2309. break;
  2310. case HW_PORT1:
  2311. /*REG_CR - BIT[19:18]-Network Type for port 1*/
  2312. val8 = rtw_read8(adapter, MSR) & 0x03;
  2313. val8 |= net_type << 2;
  2314. rtw_write8(adapter, MSR, val8);
  2315. break;
  2316. #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
  2317. case HW_PORT2:
  2318. /*REG_CR_EXT- BIT[1:0]-Network Type for port 2*/
  2319. val8 = rtw_read8(adapter, MSR1) & 0xFC;
  2320. val8 |= net_type;
  2321. rtw_write8(adapter, MSR1, val8);
  2322. break;
  2323. case HW_PORT3:
  2324. /*REG_CR_EXT- BIT[3:2]-Network Type for port 3*/
  2325. val8 = rtw_read8(adapter, MSR1) & 0xF3;
  2326. val8 |= net_type << 2;
  2327. rtw_write8(adapter, MSR1, val8);
  2328. break;
  2329. case HW_PORT4:
  2330. /*REG_CR_EXT- BIT[5:4]-Network Type for port 4*/
  2331. val8 = rtw_read8(adapter, MSR1) & 0xCF;
  2332. val8 |= net_type << 4;
  2333. rtw_write8(adapter, MSR1, val8);
  2334. break;
  2335. #endif /* CONFIG_RTL8814A | CONFIG_RTL8822B */
  2336. default:
  2337. RTW_INFO("[WARN] "ADPT_FMT"- invalid hw port -%d\n",
  2338. ADPT_ARG(adapter), adapter->hw_port);
  2339. rtw_warn_on(1);
  2340. break;
  2341. }
  2342. }
  2343. void hw_var_port_switch(_adapter *adapter)
  2344. {
  2345. #ifdef CONFIG_CONCURRENT_MODE
  2346. #ifdef CONFIG_RUNTIME_PORT_SWITCH
  2347. /*
  2348. 0x102: MSR
  2349. 0x550: REG_BCN_CTRL
  2350. 0x551: REG_BCN_CTRL_1
  2351. 0x55A: REG_ATIMWND
  2352. 0x560: REG_TSFTR
  2353. 0x568: REG_TSFTR1
  2354. 0x570: REG_ATIMWND_1
  2355. 0x610: REG_MACID
  2356. 0x618: REG_BSSID
  2357. 0x700: REG_MACID1
  2358. 0x708: REG_BSSID1
  2359. */
  2360. int i;
  2361. u8 msr;
  2362. u8 bcn_ctrl;
  2363. u8 bcn_ctrl_1;
  2364. u8 atimwnd[2];
  2365. u8 atimwnd_1[2];
  2366. u8 tsftr[8];
  2367. u8 tsftr_1[8];
  2368. u8 macid[6];
  2369. u8 bssid[6];
  2370. u8 macid_1[6];
  2371. u8 bssid_1[6];
  2372. u8 hw_port;
  2373. struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
  2374. _adapter *iface = NULL;
  2375. msr = rtw_read8(adapter, MSR);
  2376. bcn_ctrl = rtw_read8(adapter, REG_BCN_CTRL);
  2377. bcn_ctrl_1 = rtw_read8(adapter, REG_BCN_CTRL_1);
  2378. for (i = 0; i < 2; i++)
  2379. atimwnd[i] = rtw_read8(adapter, REG_ATIMWND + i);
  2380. for (i = 0; i < 2; i++)
  2381. atimwnd_1[i] = rtw_read8(adapter, REG_ATIMWND_1 + i);
  2382. for (i = 0; i < 8; i++)
  2383. tsftr[i] = rtw_read8(adapter, REG_TSFTR + i);
  2384. for (i = 0; i < 8; i++)
  2385. tsftr_1[i] = rtw_read8(adapter, REG_TSFTR1 + i);
  2386. for (i = 0; i < 6; i++)
  2387. macid[i] = rtw_read8(adapter, REG_MACID + i);
  2388. for (i = 0; i < 6; i++)
  2389. bssid[i] = rtw_read8(adapter, REG_BSSID + i);
  2390. for (i = 0; i < 6; i++)
  2391. macid_1[i] = rtw_read8(adapter, REG_MACID1 + i);
  2392. for (i = 0; i < 6; i++)
  2393. bssid_1[i] = rtw_read8(adapter, REG_BSSID1 + i);
  2394. #ifdef DBG_RUNTIME_PORT_SWITCH
  2395. RTW_INFO(FUNC_ADPT_FMT" before switch\n"
  2396. "msr:0x%02x\n"
  2397. "bcn_ctrl:0x%02x\n"
  2398. "bcn_ctrl_1:0x%02x\n"
  2399. "atimwnd:0x%04x\n"
  2400. "atimwnd_1:0x%04x\n"
  2401. "tsftr:%llu\n"
  2402. "tsftr1:%llu\n"
  2403. "macid:"MAC_FMT"\n"
  2404. "bssid:"MAC_FMT"\n"
  2405. "macid_1:"MAC_FMT"\n"
  2406. "bssid_1:"MAC_FMT"\n"
  2407. , FUNC_ADPT_ARG(adapter)
  2408. , msr
  2409. , bcn_ctrl
  2410. , bcn_ctrl_1
  2411. , *((u16 *)atimwnd)
  2412. , *((u16 *)atimwnd_1)
  2413. , *((u64 *)tsftr)
  2414. , *((u64 *)tsftr_1)
  2415. , MAC_ARG(macid)
  2416. , MAC_ARG(bssid)
  2417. , MAC_ARG(macid_1)
  2418. , MAC_ARG(bssid_1)
  2419. );
  2420. #endif /* DBG_RUNTIME_PORT_SWITCH */
  2421. /* disable bcn function, disable update TSF */
  2422. rtw_write8(adapter, REG_BCN_CTRL, (bcn_ctrl & (~EN_BCN_FUNCTION)) | DIS_TSF_UDT);
  2423. rtw_write8(adapter, REG_BCN_CTRL_1, (bcn_ctrl_1 & (~EN_BCN_FUNCTION)) | DIS_TSF_UDT);
  2424. /* switch msr */
  2425. msr = (msr & 0xf0) | ((msr & 0x03) << 2) | ((msr & 0x0c) >> 2);
  2426. rtw_write8(adapter, MSR, msr);
  2427. /* write port0 */
  2428. rtw_write8(adapter, REG_BCN_CTRL, bcn_ctrl_1 & ~EN_BCN_FUNCTION);
  2429. for (i = 0; i < 2; i++)
  2430. rtw_write8(adapter, REG_ATIMWND + i, atimwnd_1[i]);
  2431. for (i = 0; i < 8; i++)
  2432. rtw_write8(adapter, REG_TSFTR + i, tsftr_1[i]);
  2433. for (i = 0; i < 6; i++)
  2434. rtw_write8(adapter, REG_MACID + i, macid_1[i]);
  2435. for (i = 0; i < 6; i++)
  2436. rtw_write8(adapter, REG_BSSID + i, bssid_1[i]);
  2437. /* write port1 */
  2438. rtw_write8(adapter, REG_BCN_CTRL_1, bcn_ctrl & ~EN_BCN_FUNCTION);
  2439. for (i = 0; i < 2; i++)
  2440. rtw_write8(adapter, REG_ATIMWND_1 + i, atimwnd[i]);
  2441. for (i = 0; i < 8; i++)
  2442. rtw_write8(adapter, REG_TSFTR1 + i, tsftr[i]);
  2443. for (i = 0; i < 6; i++)
  2444. rtw_write8(adapter, REG_MACID1 + i, macid[i]);
  2445. for (i = 0; i < 6; i++)
  2446. rtw_write8(adapter, REG_BSSID1 + i, bssid[i]);
  2447. /* write bcn ctl */
  2448. #ifdef CONFIG_BT_COEXIST
  2449. /* always enable port0 beacon function for PSTDMA */
  2450. if (IS_HARDWARE_TYPE_8723B(adapter) || IS_HARDWARE_TYPE_8703B(adapter)
  2451. || IS_HARDWARE_TYPE_8723D(adapter))
  2452. bcn_ctrl_1 |= EN_BCN_FUNCTION;
  2453. /* always disable port1 beacon function for PSTDMA */
  2454. if (IS_HARDWARE_TYPE_8723B(adapter) || IS_HARDWARE_TYPE_8703B(adapter))
  2455. bcn_ctrl &= ~EN_BCN_FUNCTION;
  2456. #endif
  2457. rtw_write8(adapter, REG_BCN_CTRL, bcn_ctrl_1);
  2458. rtw_write8(adapter, REG_BCN_CTRL_1, bcn_ctrl);
  2459. if (adapter->iface_id == IFACE_ID0)
  2460. iface = dvobj->padapters[IFACE_ID1];
  2461. else if (adapter->iface_id == IFACE_ID1)
  2462. iface = dvobj->padapters[IFACE_ID0];
  2463. if (adapter->hw_port == HW_PORT0) {
  2464. adapter->hw_port = HW_PORT1;
  2465. iface->hw_port = HW_PORT0;
  2466. RTW_PRINT("port switch - port0("ADPT_FMT"), port1("ADPT_FMT")\n",
  2467. ADPT_ARG(iface), ADPT_ARG(adapter));
  2468. } else {
  2469. adapter->hw_port = HW_PORT0;
  2470. iface->hw_port = HW_PORT1;
  2471. RTW_PRINT("port switch - port0("ADPT_FMT"), port1("ADPT_FMT")\n",
  2472. ADPT_ARG(adapter), ADPT_ARG(iface));
  2473. }
  2474. #ifdef DBG_RUNTIME_PORT_SWITCH
  2475. msr = rtw_read8(adapter, MSR);
  2476. bcn_ctrl = rtw_read8(adapter, REG_BCN_CTRL);
  2477. bcn_ctrl_1 = rtw_read8(adapter, REG_BCN_CTRL_1);
  2478. for (i = 0; i < 2; i++)
  2479. atimwnd[i] = rtw_read8(adapter, REG_ATIMWND + i);
  2480. for (i = 0; i < 2; i++)
  2481. atimwnd_1[i] = rtw_read8(adapter, REG_ATIMWND_1 + i);
  2482. for (i = 0; i < 8; i++)
  2483. tsftr[i] = rtw_read8(adapter, REG_TSFTR + i);
  2484. for (i = 0; i < 8; i++)
  2485. tsftr_1[i] = rtw_read8(adapter, REG_TSFTR1 + i);
  2486. for (i = 0; i < 6; i++)
  2487. macid[i] = rtw_read8(adapter, REG_MACID + i);
  2488. for (i = 0; i < 6; i++)
  2489. bssid[i] = rtw_read8(adapter, REG_BSSID + i);
  2490. for (i = 0; i < 6; i++)
  2491. macid_1[i] = rtw_read8(adapter, REG_MACID1 + i);
  2492. for (i = 0; i < 6; i++)
  2493. bssid_1[i] = rtw_read8(adapter, REG_BSSID1 + i);
  2494. RTW_INFO(FUNC_ADPT_FMT" after switch\n"
  2495. "msr:0x%02x\n"
  2496. "bcn_ctrl:0x%02x\n"
  2497. "bcn_ctrl_1:0x%02x\n"
  2498. "atimwnd:%u\n"
  2499. "atimwnd_1:%u\n"
  2500. "tsftr:%llu\n"
  2501. "tsftr1:%llu\n"
  2502. "macid:"MAC_FMT"\n"
  2503. "bssid:"MAC_FMT"\n"
  2504. "macid_1:"MAC_FMT"\n"
  2505. "bssid_1:"MAC_FMT"\n"
  2506. , FUNC_ADPT_ARG(adapter)
  2507. , msr
  2508. , bcn_ctrl
  2509. , bcn_ctrl_1
  2510. , *((u16 *)atimwnd)
  2511. , *((u16 *)atimwnd_1)
  2512. , *((u64 *)tsftr)
  2513. , *((u64 *)tsftr_1)
  2514. , MAC_ARG(macid)
  2515. , MAC_ARG(bssid)
  2516. , MAC_ARG(macid_1)
  2517. , MAC_ARG(bssid_1)
  2518. );
  2519. #endif /* DBG_RUNTIME_PORT_SWITCH */
  2520. #endif /* CONFIG_RUNTIME_PORT_SWITCH */
  2521. #endif /* CONFIG_CONCURRENT_MODE */
  2522. }
  2523. const char *const _h2c_msr_role_str[] = {
  2524. "RSVD",
  2525. "STA",
  2526. "AP",
  2527. "GC",
  2528. "GO",
  2529. "TDLS",
  2530. "ADHOC",
  2531. "INVALID",
  2532. };
  2533. #ifdef CONFIG_FW_MULTI_PORT_SUPPORT
  2534. s32 rtw_hal_set_default_port_id_cmd(_adapter *adapter, u8 mac_id)
  2535. {
  2536. s32 ret = _SUCCESS;
  2537. u8 parm[H2C_DEFAULT_PORT_ID_LEN] = {0};
  2538. struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
  2539. SET_H2CCMD_DFTPID_PORT_ID(parm, adapter->hw_port);
  2540. SET_H2CCMD_DFTPID_MAC_ID(parm, mac_id);
  2541. RTW_DBG_DUMP("DFT port id parm:", parm, H2C_DEFAULT_PORT_ID_LEN);
  2542. RTW_INFO("%s port_id :%d, mad_id:%d\n", __func__, adapter->hw_port, mac_id);
  2543. ret = rtw_hal_fill_h2c_cmd(adapter, H2C_DEFAULT_PORT_ID, H2C_DEFAULT_PORT_ID_LEN, parm);
  2544. dvobj->default_port_id = adapter->hw_port;
  2545. return ret;
  2546. }
  2547. s32 rtw_set_default_port_id(_adapter *adapter)
  2548. {
  2549. s32 ret = _SUCCESS;
  2550. struct sta_info *psta;
  2551. struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
  2552. struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
  2553. if (adapter->hw_port == dvobj->default_port_id)
  2554. return ret;
  2555. if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) {
  2556. psta = rtw_get_stainfo(&adapter->stapriv, get_bssid(pmlmepriv));
  2557. if (psta)
  2558. ret = rtw_hal_set_default_port_id_cmd(adapter, psta->mac_id);
  2559. } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) {
  2560. } else {
  2561. }
  2562. return ret;
  2563. }
  2564. s32 rtw_set_ps_rsvd_page(_adapter *adapter)
  2565. {
  2566. s32 ret = _SUCCESS;
  2567. u16 media_status_rpt = RT_MEDIA_CONNECT;
  2568. struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
  2569. if (adapter->hw_port == dvobj->default_port_id)
  2570. return ret;
  2571. rtw_hal_set_hwreg(adapter, HW_VAR_H2C_FW_JOINBSSRPT,
  2572. (u8 *)&media_status_rpt);
  2573. return ret;
  2574. }
  2575. #endif
  2576. #ifdef CONFIG_P2P_PS
  2577. #ifdef RTW_HALMAC
  2578. void rtw_set_p2p_ps_offload_cmd(_adapter *adapter, u8 p2p_ps_state)
  2579. {
  2580. PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
  2581. struct wifidirect_info *pwdinfo = &adapter->wdinfo;
  2582. struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
  2583. struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
  2584. WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
  2585. struct sta_priv *pstapriv = &adapter->stapriv;
  2586. struct sta_info *psta;
  2587. HAL_P2P_PS_PARA p2p_ps_para;
  2588. int status = -1;
  2589. u8 i;
  2590. _rtw_memset(&p2p_ps_para, 0, sizeof(HAL_P2P_PS_PARA));
  2591. _rtw_memcpy((&p2p_ps_para) , &hal->p2p_ps_offload , sizeof(hal->p2p_ps_offload));
  2592. (&p2p_ps_para)->p2p_port_id = adapter->hw_port;
  2593. (&p2p_ps_para)->p2p_group = 0;
  2594. psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress);
  2595. if (psta) {
  2596. (&p2p_ps_para)->p2p_macid = psta->mac_id;
  2597. } else {
  2598. if (p2p_ps_state != P2P_PS_DISABLE) {
  2599. RTW_ERR("%s , psta was NULL\n", __func__);
  2600. return;
  2601. }
  2602. }
  2603. switch (p2p_ps_state) {
  2604. case P2P_PS_DISABLE:
  2605. RTW_INFO("P2P_PS_DISABLE\n");
  2606. _rtw_memset(&p2p_ps_para , 0, sizeof(HAL_P2P_PS_PARA));
  2607. break;
  2608. case P2P_PS_ENABLE:
  2609. RTW_INFO("P2P_PS_ENABLE\n");
  2610. /* update CTWindow value. */
  2611. if (pwdinfo->ctwindow > 0) {
  2612. (&p2p_ps_para)->ctwindow_en = 1;
  2613. (&p2p_ps_para)->ctwindow_length = pwdinfo->ctwindow;
  2614. /*RTW_INFO("%s , ctwindow_length = %d\n" , __func__ , (&p2p_ps_para)->ctwindow_length);*/
  2615. }
  2616. if ((pwdinfo->opp_ps == 1) || (pwdinfo->noa_num > 0)) {
  2617. (&p2p_ps_para)->offload_en = 1;
  2618. if (pwdinfo->role == P2P_ROLE_GO) {
  2619. (&p2p_ps_para)->role = 1;
  2620. (&p2p_ps_para)->all_sta_sleep = 0;
  2621. } else
  2622. (&p2p_ps_para)->role = 0;
  2623. (&p2p_ps_para)->discovery = 0;
  2624. }
  2625. /* hw only support 2 set of NoA */
  2626. for (i = 0; i < pwdinfo->noa_num; i++) {
  2627. /* To control the register setting for which NOA */
  2628. (&p2p_ps_para)->noa_sel = i;
  2629. (&p2p_ps_para)->noa_en = 1;
  2630. /* config P2P NoA Descriptor Register */
  2631. /* config NOA duration */
  2632. (&p2p_ps_para)->noa_duration_para = pwdinfo->noa_duration[i];
  2633. /* config NOA interval */
  2634. (&p2p_ps_para)->noa_interval_para = pwdinfo->noa_interval[i];
  2635. /* config NOA start time */
  2636. (&p2p_ps_para)->noa_start_time_para = pwdinfo->noa_start_time[i];
  2637. /* config NOA count */
  2638. (&p2p_ps_para)->noa_count_para = pwdinfo->noa_count[i];
  2639. /*RTW_INFO("%s , noa_duration_para = %d , noa_interval_para = %d , noa_start_time_para = %d , noa_count_para = %d\n" , __func__ ,
  2640. (&p2p_ps_para)->noa_duration_para , (&p2p_ps_para)->noa_interval_para ,
  2641. (&p2p_ps_para)->noa_start_time_para , (&p2p_ps_para)->noa_count_para);*/
  2642. status = rtw_halmac_p2pps(adapter_to_dvobj(adapter) , (&p2p_ps_para));
  2643. if (status == -1)
  2644. RTW_ERR("%s , rtw_halmac_p2pps fail\n", __func__);
  2645. }
  2646. break;
  2647. case P2P_PS_SCAN:
  2648. /*This feature FW not ready 20161116 YiWei*/
  2649. return;
  2650. RTW_INFO("P2P_PS_SCAN\n");
  2651. (&p2p_ps_para)->discovery = 1;
  2652. /*
  2653. (&p2p_ps_para)->ctwindow_length = pwdinfo->ctwindow;
  2654. (&p2p_ps_para)->noa_duration_para = pwdinfo->noa_duration[0];
  2655. (&p2p_ps_para)->noa_interval_para = pwdinfo->noa_interval[0];
  2656. (&p2p_ps_para)->noa_start_time_para = pwdinfo->noa_start_time[0];
  2657. (&p2p_ps_para)->noa_count_para = pwdinfo->noa_count[0];
  2658. */
  2659. break;
  2660. case P2P_PS_SCAN_DONE:
  2661. /*This feature FW not ready 20161116 YiWei*/
  2662. return;
  2663. RTW_INFO("P2P_PS_SCAN_DONE\n");
  2664. (&p2p_ps_para)->discovery = 0;
  2665. /*
  2666. pwdinfo->p2p_ps_state = P2P_PS_ENABLE;
  2667. (&p2p_ps_para)->ctwindow_length = pwdinfo->ctwindow;
  2668. (&p2p_ps_para)->noa_duration_para = pwdinfo->noa_duration[0];
  2669. (&p2p_ps_para)->noa_interval_para = pwdinfo->noa_interval[0];
  2670. (&p2p_ps_para)->noa_start_time_para = pwdinfo->noa_start_time[0];
  2671. (&p2p_ps_para)->noa_count_para = pwdinfo->noa_count[0];
  2672. */
  2673. break;
  2674. default:
  2675. break;
  2676. }
  2677. if (p2p_ps_state != P2P_PS_ENABLE || (&p2p_ps_para)->noa_en == 0) {
  2678. status = rtw_halmac_p2pps(adapter_to_dvobj(adapter) , (&p2p_ps_para));
  2679. if (status == -1)
  2680. RTW_ERR("%s , rtw_halmac_p2pps fail\n", __func__);
  2681. }
  2682. _rtw_memcpy(&hal->p2p_ps_offload , (&p2p_ps_para) , sizeof(hal->p2p_ps_offload));
  2683. }
  2684. #endif /* RTW_HALMAC */
  2685. #endif /* CONFIG_P2P */
  2686. /*
  2687. * rtw_hal_set_FwMediaStatusRpt_cmd -
  2688. *
  2689. * @adapter:
  2690. * @opmode: 0:disconnect, 1:connect
  2691. * @miracast: 0:it's not in miracast scenario. 1:it's in miracast scenario
  2692. * @miracast_sink: 0:source. 1:sink
  2693. * @role: The role of this macid. 0:rsvd. 1:STA. 2:AP. 3:GC. 4:GO. 5:TDLS
  2694. * @macid:
  2695. * @macid_ind: 0:update Media Status to macid. 1:update Media Status from macid to macid_end
  2696. * @macid_end:
  2697. */
  2698. s32 rtw_hal_set_FwMediaStatusRpt_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid, bool macid_ind, u8 macid_end)
  2699. {
  2700. struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl;
  2701. u8 parm[H2C_MEDIA_STATUS_RPT_LEN] = {0};
  2702. int i;
  2703. s32 ret;
  2704. SET_H2CCMD_MSRRPT_PARM_OPMODE(parm, opmode);
  2705. SET_H2CCMD_MSRRPT_PARM_MACID_IND(parm, macid_ind);
  2706. SET_H2CCMD_MSRRPT_PARM_MIRACAST(parm, miracast);
  2707. SET_H2CCMD_MSRRPT_PARM_MIRACAST_SINK(parm, miracast_sink);
  2708. SET_H2CCMD_MSRRPT_PARM_ROLE(parm, role);
  2709. SET_H2CCMD_MSRRPT_PARM_MACID(parm, macid);
  2710. SET_H2CCMD_MSRRPT_PARM_MACID_END(parm, macid_end);
  2711. #ifdef CONFIG_FW_MULTI_PORT_SUPPORT
  2712. SET_H2CCMD_MSRRPT_PARM_PORT_NUM(parm, adapter->hw_port);
  2713. #endif
  2714. RTW_DBG_DUMP("MediaStatusRpt parm:", parm, H2C_MEDIA_STATUS_RPT_LEN);
  2715. ret = rtw_hal_fill_h2c_cmd(adapter, H2C_MEDIA_STATUS_RPT, H2C_MEDIA_STATUS_RPT_LEN, parm);
  2716. if (ret != _SUCCESS)
  2717. goto exit;
  2718. #if defined(CONFIG_RTL8188E)
  2719. if (rtw_get_chip_type(adapter) == RTL8188E) {
  2720. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
  2721. /* 8188E FW doesn't set macid no link, driver does it by self */
  2722. if (opmode)
  2723. rtw_hal_set_hwreg(adapter, HW_VAR_MACID_LINK, &macid);
  2724. else
  2725. rtw_hal_set_hwreg(adapter, HW_VAR_MACID_NOLINK, &macid);
  2726. /* for 8188E RA */
  2727. #if (RATE_ADAPTIVE_SUPPORT == 1)
  2728. if (hal_data->fw_ractrl == _FALSE) {
  2729. u8 max_macid;
  2730. max_macid = rtw_search_max_mac_id(adapter);
  2731. rtw_hal_set_hwreg(adapter, HW_VAR_TX_RPT_MAX_MACID, &max_macid);
  2732. }
  2733. #endif
  2734. }
  2735. #endif
  2736. #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
  2737. /* TODO: this should move to IOT issue area */
  2738. if (rtw_get_chip_type(adapter) == RTL8812
  2739. || rtw_get_chip_type(adapter) == RTL8821
  2740. ) {
  2741. if (MLME_IS_STA(adapter))
  2742. Hal_PatchwithJaguar_8812(adapter, opmode);
  2743. }
  2744. #endif
  2745. SET_H2CCMD_MSRRPT_PARM_MACID_IND(parm, 0);
  2746. if (macid_ind == 0)
  2747. macid_end = macid;
  2748. for (i = macid; macid <= macid_end; macid++) {
  2749. rtw_macid_ctl_set_h2c_msr(macid_ctl, macid, parm[0]);
  2750. if (!opmode) {
  2751. rtw_macid_ctl_set_bw(macid_ctl, macid, CHANNEL_WIDTH_20);
  2752. rtw_macid_ctl_set_vht_en(macid_ctl, macid, 0);
  2753. rtw_macid_ctl_set_rate_bmp0(macid_ctl, macid, 0);
  2754. rtw_macid_ctl_set_rate_bmp1(macid_ctl, macid, 0);
  2755. }
  2756. }
  2757. if (!opmode)
  2758. rtw_update_tx_rate_bmp(adapter_to_dvobj(adapter));
  2759. exit:
  2760. return ret;
  2761. }
  2762. inline s32 rtw_hal_set_FwMediaStatusRpt_single_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid)
  2763. {
  2764. return rtw_hal_set_FwMediaStatusRpt_cmd(adapter, opmode, miracast, miracast_sink, role, macid, 0, 0);
  2765. }
  2766. inline s32 rtw_hal_set_FwMediaStatusRpt_range_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid, u8 macid_end)
  2767. {
  2768. return rtw_hal_set_FwMediaStatusRpt_cmd(adapter, opmode, miracast, miracast_sink, role, macid, 1, macid_end);
  2769. }
  2770. void rtw_hal_set_FwRsvdPage_cmd(PADAPTER padapter, PRSVDPAGE_LOC rsvdpageloc)
  2771. {
  2772. struct hal_ops *pHalFunc = &padapter->hal_func;
  2773. u8 u1H2CRsvdPageParm[H2C_RSVDPAGE_LOC_LEN] = {0};
  2774. u8 ret = 0;
  2775. RTW_INFO("RsvdPageLoc: ProbeRsp=%d PsPoll=%d Null=%d QoSNull=%d BTNull=%d\n",
  2776. rsvdpageloc->LocProbeRsp, rsvdpageloc->LocPsPoll,
  2777. rsvdpageloc->LocNullData, rsvdpageloc->LocQosNull,
  2778. rsvdpageloc->LocBTQosNull);
  2779. SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(u1H2CRsvdPageParm, rsvdpageloc->LocProbeRsp);
  2780. SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1H2CRsvdPageParm, rsvdpageloc->LocPsPoll);
  2781. SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1H2CRsvdPageParm, rsvdpageloc->LocNullData);
  2782. SET_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(u1H2CRsvdPageParm, rsvdpageloc->LocQosNull);
  2783. SET_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(u1H2CRsvdPageParm, rsvdpageloc->LocBTQosNull);
  2784. ret = rtw_hal_fill_h2c_cmd(padapter,
  2785. H2C_RSVD_PAGE,
  2786. H2C_RSVDPAGE_LOC_LEN,
  2787. u1H2CRsvdPageParm);
  2788. }
  2789. #ifdef CONFIG_GPIO_WAKEUP
  2790. void rtw_hal_switch_gpio_wl_ctrl(_adapter *padapter, u8 index, u8 enable)
  2791. {
  2792. PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
  2793. if (IS_8723D_SERIES(pHalData->version_id) || IS_8822B_SERIES(pHalData->version_id))
  2794. rtw_hal_set_hwreg(padapter, HW_SET_GPIO_WL_CTRL, (u8 *)(&enable));
  2795. /*
  2796. * Switch GPIO_13, GPIO_14 to wlan control, or pull GPIO_13,14 MUST fail.
  2797. * It happended at 8723B/8192E/8821A. New IC will check multi function GPIO,
  2798. * and implement HAL function.
  2799. * TODO: GPIO_8 multi function?
  2800. */
  2801. if (index == 13 || index == 14)
  2802. rtw_hal_set_hwreg(padapter, HW_SET_GPIO_WL_CTRL, (u8 *)(&enable));
  2803. }
  2804. void rtw_hal_set_output_gpio(_adapter *padapter, u8 index, u8 outputval)
  2805. {
  2806. if (index <= 7) {
  2807. /* config GPIO mode */
  2808. rtw_write8(padapter, REG_GPIO_PIN_CTRL + 3,
  2809. rtw_read8(padapter, REG_GPIO_PIN_CTRL + 3) & ~BIT(index));
  2810. /* config GPIO Sel */
  2811. /* 0: input */
  2812. /* 1: output */
  2813. rtw_write8(padapter, REG_GPIO_PIN_CTRL + 2,
  2814. rtw_read8(padapter, REG_GPIO_PIN_CTRL + 2) | BIT(index));
  2815. /* set output value */
  2816. if (outputval) {
  2817. rtw_write8(padapter, REG_GPIO_PIN_CTRL + 1,
  2818. rtw_read8(padapter, REG_GPIO_PIN_CTRL + 1) | BIT(index));
  2819. } else {
  2820. rtw_write8(padapter, REG_GPIO_PIN_CTRL + 1,
  2821. rtw_read8(padapter, REG_GPIO_PIN_CTRL + 1) & ~BIT(index));
  2822. }
  2823. } else if (index <= 15) {
  2824. /* 88C Series: */
  2825. /* index: 11~8 transform to 3~0 */
  2826. /* 8723 Series: */
  2827. /* index: 12~8 transform to 4~0 */
  2828. index -= 8;
  2829. /* config GPIO mode */
  2830. rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 3,
  2831. rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 3) & ~BIT(index));
  2832. /* config GPIO Sel */
  2833. /* 0: input */
  2834. /* 1: output */
  2835. rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 2,
  2836. rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 2) | BIT(index));
  2837. /* set output value */
  2838. if (outputval) {
  2839. rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 1,
  2840. rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 1) | BIT(index));
  2841. } else {
  2842. rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 1,
  2843. rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 1) & ~BIT(index));
  2844. }
  2845. } else {
  2846. RTW_INFO("%s: invalid GPIO%d=%d\n",
  2847. __FUNCTION__, index, outputval);
  2848. }
  2849. }
  2850. void rtw_hal_set_input_gpio(_adapter *padapter, u8 index)
  2851. {
  2852. if (index <= 7) {
  2853. /* config GPIO mode */
  2854. rtw_write8(padapter, REG_GPIO_PIN_CTRL + 3,
  2855. rtw_read8(padapter, REG_GPIO_PIN_CTRL + 3) & ~BIT(index));
  2856. /* config GPIO Sel */
  2857. /* 0: input */
  2858. /* 1: output */
  2859. rtw_write8(padapter, REG_GPIO_PIN_CTRL + 2,
  2860. rtw_read8(padapter, REG_GPIO_PIN_CTRL + 2) & ~BIT(index));
  2861. } else if (index <= 15) {
  2862. /* 88C Series: */
  2863. /* index: 11~8 transform to 3~0 */
  2864. /* 8723 Series: */
  2865. /* index: 12~8 transform to 4~0 */
  2866. index -= 8;
  2867. /* config GPIO mode */
  2868. rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 3,
  2869. rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 3) & ~BIT(index));
  2870. /* config GPIO Sel */
  2871. /* 0: input */
  2872. /* 1: output */
  2873. rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 2,
  2874. rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 2) & ~BIT(index));
  2875. } else
  2876. RTW_INFO("%s: invalid GPIO%d\n", __func__, index);
  2877. }
  2878. #endif
  2879. void rtw_hal_set_FwAoacRsvdPage_cmd(PADAPTER padapter, PRSVDPAGE_LOC rsvdpageloc)
  2880. {
  2881. struct hal_ops *pHalFunc = &padapter->hal_func;
  2882. struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
  2883. struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
  2884. u8 res = 0, count = 0, ret = 0;
  2885. #ifdef CONFIG_WOWLAN
  2886. u8 u1H2CAoacRsvdPageParm[H2C_AOAC_RSVDPAGE_LOC_LEN] = {0};
  2887. RTW_INFO("AOACRsvdPageLoc: RWC=%d ArpRsp=%d NbrAdv=%d GtkRsp=%d GtkInfo=%d ProbeReq=%d NetworkList=%d\n",
  2888. rsvdpageloc->LocRemoteCtrlInfo, rsvdpageloc->LocArpRsp,
  2889. rsvdpageloc->LocNbrAdv, rsvdpageloc->LocGTKRsp,
  2890. rsvdpageloc->LocGTKInfo, rsvdpageloc->LocProbeReq,
  2891. rsvdpageloc->LocNetList);
  2892. if (check_fwstate(pmlmepriv, _FW_LINKED)) {
  2893. SET_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(u1H2CAoacRsvdPageParm, rsvdpageloc->LocRemoteCtrlInfo);
  2894. SET_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(u1H2CAoacRsvdPageParm, rsvdpageloc->LocArpRsp);
  2895. /* SET_H2CCMD_AOAC_RSVDPAGE_LOC_NEIGHBOR_ADV(u1H2CAoacRsvdPageParm, rsvdpageloc->LocNbrAdv); */
  2896. #ifdef CONFIG_GTK_OL
  2897. SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_RSP(u1H2CAoacRsvdPageParm, rsvdpageloc->LocGTKRsp);
  2898. SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_INFO(u1H2CAoacRsvdPageParm, rsvdpageloc->LocGTKInfo);
  2899. SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_EXT_MEM(u1H2CAoacRsvdPageParm, rsvdpageloc->LocGTKEXTMEM);
  2900. #endif /* CONFIG_GTK_OL */
  2901. ret = rtw_hal_fill_h2c_cmd(padapter,
  2902. H2C_AOAC_RSVD_PAGE,
  2903. H2C_AOAC_RSVDPAGE_LOC_LEN,
  2904. u1H2CAoacRsvdPageParm);
  2905. RTW_INFO("AOAC Report=%d\n", rsvdpageloc->LocAOACReport);
  2906. _rtw_memset(&u1H2CAoacRsvdPageParm, 0, sizeof(u1H2CAoacRsvdPageParm));
  2907. SET_H2CCMD_AOAC_RSVDPAGE_LOC_AOAC_REPORT(u1H2CAoacRsvdPageParm,
  2908. rsvdpageloc->LocAOACReport);
  2909. ret = rtw_hal_fill_h2c_cmd(padapter,
  2910. H2C_AOAC_RSVDPAGE3,
  2911. H2C_AOAC_RSVDPAGE_LOC_LEN,
  2912. u1H2CAoacRsvdPageParm);
  2913. pwrpriv->wowlan_aoac_rpt_loc = rsvdpageloc->LocAOACReport;
  2914. }
  2915. #ifdef CONFIG_PNO_SUPPORT
  2916. else {
  2917. if (!pwrpriv->wowlan_in_resume) {
  2918. RTW_INFO("NLO_INFO=%d\n", rsvdpageloc->LocPNOInfo);
  2919. _rtw_memset(&u1H2CAoacRsvdPageParm, 0,
  2920. sizeof(u1H2CAoacRsvdPageParm));
  2921. SET_H2CCMD_AOAC_RSVDPAGE_LOC_NLO_INFO(u1H2CAoacRsvdPageParm,
  2922. rsvdpageloc->LocPNOInfo);
  2923. ret = rtw_hal_fill_h2c_cmd(padapter,
  2924. H2C_AOAC_RSVDPAGE3,
  2925. H2C_AOAC_RSVDPAGE_LOC_LEN,
  2926. u1H2CAoacRsvdPageParm);
  2927. }
  2928. }
  2929. #endif /* CONFIG_PNO_SUPPORT */
  2930. #endif /* CONFIG_WOWLAN */
  2931. }
  2932. /*#define DBG_GET_RSVD_PAGE*/
  2933. int rtw_hal_get_rsvd_page(_adapter *adapter, u32 page_offset,
  2934. u32 page_num, u8 *buffer, u32 buffer_size)
  2935. {
  2936. u32 addr = 0, size = 0, count = 0;
  2937. u32 page_size = 0, data_low = 0, data_high = 0;
  2938. u16 txbndy = 0, offset = 0;
  2939. u8 i = 0;
  2940. bool rst = _FALSE;
  2941. rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, &page_size);
  2942. addr = page_offset * page_size;
  2943. size = page_num * page_size;
  2944. if (buffer_size < size) {
  2945. RTW_ERR("%s buffer_size(%d) < get page total size(%d)\n",
  2946. __func__, buffer_size, size);
  2947. return rst;
  2948. }
  2949. #ifdef RTW_HALMAC
  2950. if (rtw_halmac_dump_fifo(adapter_to_dvobj(adapter), 2, addr, size, buffer) < 0)
  2951. rst = _FALSE;
  2952. else
  2953. rst = _TRUE;
  2954. #else
  2955. txbndy = rtw_read8(adapter, REG_TDECTRL + 1);
  2956. offset = (txbndy + page_offset) << 4;
  2957. count = (buffer_size / 8) + 1;
  2958. rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, 0x69);
  2959. for (i = 0 ; i < count ; i++) {
  2960. rtw_write32(adapter, REG_PKTBUF_DBG_CTRL, offset + i);
  2961. data_low = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_L);
  2962. data_high = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H);
  2963. _rtw_memcpy(buffer + (i * 8),
  2964. &data_low, sizeof(data_low));
  2965. _rtw_memcpy(buffer + ((i * 8) + 4),
  2966. &data_high, sizeof(data_high));
  2967. }
  2968. rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, 0x0);
  2969. rst = _TRUE;
  2970. #endif /*RTW_HALMAC*/
  2971. #ifdef DBG_GET_RSVD_PAGE
  2972. RTW_INFO("%s [page_offset:%d , page_num:%d][start_addr:0x%04x , size:%d]\n",
  2973. __func__, page_offset, page_num, addr, size);
  2974. RTW_INFO_DUMP("\n", buffer, size);
  2975. RTW_INFO(" ==================================================\n");
  2976. #endif
  2977. return rst;
  2978. }
  2979. void rtw_dump_rsvd_page(void *sel, _adapter *adapter, u8 page_offset, u8 page_num)
  2980. {
  2981. u32 page_size = 0;
  2982. u8 *buffer = NULL;
  2983. u32 buf_size = 0;
  2984. if (page_num == 0)
  2985. return;
  2986. RTW_PRINT_SEL(sel, "======= RSVG PAGE DUMP =======\n");
  2987. RTW_PRINT_SEL(sel, "page_offset:%d, page_num:%d\n", page_offset, page_num);
  2988. rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, &page_size);
  2989. if (page_size) {
  2990. buf_size = page_size * page_num;
  2991. buffer = rtw_zvmalloc(buf_size);
  2992. if (buffer) {
  2993. rtw_hal_get_rsvd_page(adapter, page_offset, page_num, buffer, buf_size);
  2994. _RTW_DUMP_SEL(sel, buffer, buf_size);
  2995. rtw_vmfree(buffer, buf_size);
  2996. } else
  2997. RTW_PRINT_SEL(sel, "ERROR - rsvd_buf mem allocate failed\n");
  2998. } else
  2999. RTW_PRINT_SEL(sel, "ERROR - Tx page size is zero ??\n");
  3000. RTW_PRINT_SEL(sel, "==========================\n");
  3001. }
  3002. #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
  3003. static void rtw_hal_force_enable_rxdma(_adapter *adapter)
  3004. {
  3005. RTW_INFO("%s: Set 0x690=0x00\n", __func__);
  3006. rtw_write8(adapter, REG_WOW_CTRL,
  3007. (rtw_read8(adapter, REG_WOW_CTRL) & 0xf0));
  3008. RTW_PRINT("%s: Release RXDMA\n", __func__);
  3009. rtw_write32(adapter, REG_RXPKT_NUM,
  3010. (rtw_read32(adapter, REG_RXPKT_NUM) & (~RW_RELEASE_EN)));
  3011. }
  3012. #if defined(CONFIG_RTL8188E)
  3013. static void rtw_hal_disable_tx_report(_adapter *adapter)
  3014. {
  3015. rtw_write8(adapter, REG_TX_RPT_CTRL,
  3016. ((rtw_read8(adapter, REG_TX_RPT_CTRL) & ~BIT(1))) & ~BIT(5));
  3017. RTW_INFO("disable TXRPT:0x%02x\n", rtw_read8(adapter, REG_TX_RPT_CTRL));
  3018. }
  3019. static void rtw_hal_enable_tx_report(_adapter *adapter)
  3020. {
  3021. rtw_write8(adapter, REG_TX_RPT_CTRL,
  3022. ((rtw_read8(adapter, REG_TX_RPT_CTRL) | BIT(1))) | BIT(5));
  3023. RTW_INFO("enable TX_RPT:0x%02x\n", rtw_read8(adapter, REG_TX_RPT_CTRL));
  3024. }
  3025. #endif
  3026. static void rtw_hal_release_rx_dma(_adapter *adapter)
  3027. {
  3028. u32 val32 = 0;
  3029. val32 = rtw_read32(adapter, REG_RXPKT_NUM);
  3030. rtw_write32(adapter, REG_RXPKT_NUM, (val32 & (~RW_RELEASE_EN)));
  3031. RTW_INFO("%s, [0x%04x]: 0x%08x\n",
  3032. __func__, REG_RXPKT_NUM, (val32 & (~RW_RELEASE_EN)));
  3033. }
  3034. static u8 rtw_hal_pause_rx_dma(_adapter *adapter)
  3035. {
  3036. PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
  3037. u8 ret = 0;
  3038. s8 trycnt = 100;
  3039. u32 tmp = 0;
  3040. int res = 0;
  3041. /* RX DMA stop */
  3042. RTW_PRINT("Pause DMA\n");
  3043. rtw_write32(adapter, REG_RXPKT_NUM,
  3044. (rtw_read32(adapter, REG_RXPKT_NUM) | RW_RELEASE_EN));
  3045. do {
  3046. if ((rtw_read32(adapter, REG_RXPKT_NUM) & RXDMA_IDLE)) {
  3047. #ifdef CONFIG_USB_HCI
  3048. /* stop interface before leave */
  3049. if (_TRUE == hal->usb_intf_start) {
  3050. rtw_intf_stop(adapter);
  3051. RTW_ENABLE_FUNC(adapter, DF_RX_BIT);
  3052. RTW_ENABLE_FUNC(adapter, DF_TX_BIT);
  3053. }
  3054. #endif /* CONFIG_USB_HCI */
  3055. RTW_PRINT("RX_DMA_IDLE is true\n");
  3056. ret = _SUCCESS;
  3057. break;
  3058. }
  3059. #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
  3060. else {
  3061. res = RecvOnePkt(adapter);
  3062. RTW_PRINT("RecvOnePkt Result: %d\n", res);
  3063. }
  3064. #endif /* CONFIG_SDIO_HCI || CONFIG_GSPI_HCI */
  3065. #ifdef CONFIG_USB_HCI
  3066. else {
  3067. /* to avoid interface start repeatedly */
  3068. if (_FALSE == hal->usb_intf_start)
  3069. rtw_intf_start(adapter);
  3070. }
  3071. #endif /* CONFIG_USB_HCI */
  3072. } while (trycnt--);
  3073. if (trycnt < 0) {
  3074. tmp = rtw_read16(adapter, REG_RXPKT_NUM + 3);
  3075. RTW_PRINT("Stop RX DMA failed......\n");
  3076. RTW_PRINT("%s, RXPKT_NUM: 0x%04x\n",
  3077. __func__, tmp);
  3078. tmp = rtw_read16(adapter, REG_RXPKT_NUM + 2);
  3079. if (tmp & BIT(3))
  3080. RTW_PRINT("%s, RX DMA has req\n",
  3081. __func__);
  3082. else
  3083. RTW_PRINT("%s, RX DMA no req\n",
  3084. __func__);
  3085. ret = _FAIL;
  3086. }
  3087. return ret;
  3088. }
  3089. #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
  3090. #ifndef RTW_HALMAC
  3091. static u8 rtw_hal_enable_cpwm2(_adapter *adapter)
  3092. {
  3093. u8 ret = 0;
  3094. int res = 0;
  3095. u32 tmp = 0;
  3096. #ifdef CONFIG_GPIO_WAKEUP
  3097. return _SUCCESS;
  3098. #else
  3099. RTW_PRINT("%s\n", __func__);
  3100. res = sdio_local_read(adapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
  3101. if (!res)
  3102. RTW_INFO("read SDIO_REG_HIMR: 0x%08x\n", tmp);
  3103. else
  3104. RTW_INFO("sdio_local_read fail\n");
  3105. tmp = SDIO_HIMR_CPWM2_MSK;
  3106. res = sdio_local_write(adapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
  3107. if (!res) {
  3108. res = sdio_local_read(adapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
  3109. RTW_INFO("read again SDIO_REG_HIMR: 0x%08x\n", tmp);
  3110. ret = _SUCCESS;
  3111. } else {
  3112. RTW_INFO("sdio_local_write fail\n");
  3113. ret = _FAIL;
  3114. }
  3115. return ret;
  3116. #endif /* CONFIG_CPIO_WAKEUP */
  3117. }
  3118. #endif
  3119. #endif /* CONFIG_SDIO_HCI, CONFIG_GSPI_HCI */
  3120. #endif /* CONFIG_WOWLAN || CONFIG_AP_WOWLAN */
  3121. #ifdef CONFIG_WOWLAN
  3122. /*
  3123. * rtw_hal_check_wow_ctrl
  3124. * chk_type: _TRUE means to check enable, if 0x690 & bit1 (for 8051), WOW enable successful.
  3125. * If 0x1C7 == 0 (for 3081), WOW enable successful.
  3126. * _FALSE means to check disable, if 0x690 & bit1 (for 8051), WOW disable fail.
  3127. * If 0x120 & bit16 || 0x284 & bit18 (for 3081), WOW disable fail.
  3128. */
  3129. static u8 rtw_hal_check_wow_ctrl(_adapter *adapter, u8 chk_type)
  3130. {
  3131. u32 fe1_imr = 0xFF, rxpkt_num = 0xFF;
  3132. u8 mstatus = 0;
  3133. u8 reason = 0xFF;
  3134. u8 trycnt = 25;
  3135. u8 res = _FALSE;
  3136. if (IS_HARDWARE_TYPE_JAGUAR2(adapter)) {
  3137. if (chk_type) {
  3138. reason = rtw_read8(adapter, REG_WOWLAN_WAKE_REASON);
  3139. RTW_INFO("%s reason:0x%02x\n", __func__, reason);
  3140. while (reason && trycnt > 1) {
  3141. reason = rtw_read8(adapter, REG_WOWLAN_WAKE_REASON);
  3142. RTW_PRINT("Loop index: %d :0x%02x\n",
  3143. trycnt, reason);
  3144. trycnt--;
  3145. rtw_msleep_os(20);
  3146. }
  3147. if (!reason)
  3148. res = _TRUE;
  3149. else
  3150. res = _FALSE;
  3151. } else {
  3152. /* Wait FW to cleare 0x120 bit16, 0x284 bit18 to 0 */
  3153. fe1_imr = rtw_read32(adapter, REG_FE1IMR); /* RxDone IMR for 3081 */
  3154. rxpkt_num = rtw_read32(adapter, REG_RXPKT_NUM); /* Release RXDMA */
  3155. RTW_PRINT("%s REG_FE1IMR (reg120): 0x%x, REG_RXPKT_NUM(reg284): 0x%x\n", __func__, fe1_imr, rxpkt_num);
  3156. while (((fe1_imr & BIT_FS_RXDONE_INT_EN) || (rxpkt_num & BIT_RW_RELEASE_EN)) && trycnt > 1) {
  3157. fe1_imr = rtw_read32(adapter, REG_FE1IMR);
  3158. rxpkt_num = rtw_read32(adapter, REG_RXPKT_NUM);
  3159. RTW_PRINT("Loop index: %d :0x%x, 0x%x\n",
  3160. trycnt, fe1_imr, rxpkt_num);
  3161. trycnt--;
  3162. rtw_msleep_os(20);
  3163. }
  3164. if ((fe1_imr & BIT_FS_RXDONE_INT_EN) || (rxpkt_num & BIT_RW_RELEASE_EN))
  3165. res = _FALSE;
  3166. else
  3167. res = _TRUE;
  3168. }
  3169. } else {
  3170. mstatus = rtw_read8(adapter, REG_WOW_CTRL);
  3171. RTW_INFO("%s mstatus:0x%02x\n", __func__, mstatus);
  3172. if (chk_type) {
  3173. while (!(mstatus & BIT1) && trycnt > 1) {
  3174. mstatus = rtw_read8(adapter, REG_WOW_CTRL);
  3175. RTW_PRINT("Loop index: %d :0x%02x\n",
  3176. trycnt, mstatus);
  3177. trycnt--;
  3178. rtw_msleep_os(20);
  3179. }
  3180. if (mstatus & BIT1)
  3181. res = _TRUE;
  3182. else
  3183. res = _FALSE;
  3184. } else {
  3185. while (mstatus & BIT1 && trycnt > 1) {
  3186. mstatus = rtw_read8(adapter, REG_WOW_CTRL);
  3187. RTW_PRINT("Loop index: %d :0x%02x\n",
  3188. trycnt, mstatus);
  3189. trycnt--;
  3190. rtw_msleep_os(20);
  3191. }
  3192. if (mstatus & BIT1)
  3193. res = _FALSE;
  3194. else
  3195. res = _TRUE;
  3196. }
  3197. }
  3198. RTW_PRINT("%s check_type: %d res: %d trycnt: %d\n",
  3199. __func__, chk_type, res, (25 - trycnt));
  3200. return res;
  3201. }
  3202. #ifdef CONFIG_PNO_SUPPORT
  3203. static u8 rtw_hal_check_pno_enabled(_adapter *adapter)
  3204. {
  3205. struct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(adapter);
  3206. u8 res = 0, count = 0;
  3207. u8 ret = _FALSE;
  3208. if (ppwrpriv->wowlan_pno_enable && ppwrpriv->wowlan_in_resume == _FALSE) {
  3209. res = rtw_read8(adapter, REG_PNO_STATUS);
  3210. while (!(res & BIT(7)) && count < 25) {
  3211. RTW_INFO("[%d] cmd: 0x81 REG_PNO_STATUS: 0x%02x\n",
  3212. count, res);
  3213. res = rtw_read8(adapter, REG_PNO_STATUS);
  3214. count++;
  3215. rtw_msleep_os(2);
  3216. }
  3217. if (res & BIT(7))
  3218. ret = _TRUE;
  3219. else
  3220. ret = _FALSE;
  3221. RTW_INFO("cmd: 0x81 REG_PNO_STATUS: ret(%d)\n", ret);
  3222. }
  3223. return ret;
  3224. }
  3225. #endif
  3226. static void rtw_hal_backup_rate(_adapter *adapter)
  3227. {
  3228. RTW_INFO("%s\n", __func__);
  3229. /* backup data rate to register 0x8b for wowlan FW */
  3230. rtw_write8(adapter, 0x8d, 1);
  3231. rtw_write8(adapter, 0x8c, 0);
  3232. rtw_write8(adapter, 0x8f, 0x40);
  3233. rtw_write8(adapter, 0x8b, rtw_read8(adapter, 0x2f0));
  3234. }
  3235. #ifdef CONFIG_GTK_OL
  3236. static void rtw_hal_fw_sync_cam_id(_adapter *adapter)
  3237. {
  3238. struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
  3239. int cam_id, index = 0;
  3240. u8 *addr = NULL;
  3241. if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
  3242. return;
  3243. addr = get_bssid(pmlmepriv);
  3244. if (addr == NULL) {
  3245. RTW_INFO("%s: get bssid MAC addr fail!!\n", __func__);
  3246. return;
  3247. }
  3248. rtw_clean_dk_section(adapter);
  3249. do {
  3250. cam_id = rtw_camid_search(adapter, addr, index, 1);
  3251. if (cam_id == -1)
  3252. RTW_INFO("%s: cam_id: %d, key_id:%d\n", __func__, cam_id, index);
  3253. else
  3254. rtw_sec_cam_swap(adapter, cam_id, index);
  3255. index++;
  3256. } while (index < 4);
  3257. rtw_write8(adapter, REG_SECCFG, 0xcc);
  3258. }
  3259. static void rtw_dump_aoac_rpt(_adapter *adapter)
  3260. {
  3261. struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
  3262. struct aoac_report *paoac_rpt = &pwrctl->wowlan_aoac_rpt;
  3263. RTW_INFO_DUMP("[AOAC-RPT] IV -", paoac_rpt->iv, 8);
  3264. RTW_INFO_DUMP("[AOAC-RPT] Replay counter of EAPOL key - ",
  3265. paoac_rpt->replay_counter_eapol_key, 8);
  3266. RTW_INFO_DUMP("[AOAC-RPT] Group key - ", paoac_rpt->group_key, 32);
  3267. RTW_INFO("[AOAC-RPT] Key Index - %d\n", paoac_rpt->key_index);
  3268. RTW_INFO("[AOAC-RPT] Security Type - %d\n", paoac_rpt->security_type);
  3269. }
  3270. static void rtw_hal_get_aoac_rpt(_adapter *adapter)
  3271. {
  3272. struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
  3273. struct aoac_report *paoac_rpt = &pwrctl->wowlan_aoac_rpt;
  3274. u32 page_offset = 0, page_number = 0;
  3275. u32 page_size = 0, buf_size = 0;
  3276. u8 *buffer = NULL;
  3277. u8 i = 0, tmp = 0;
  3278. int ret = -1;
  3279. /* read aoac report from rsvd page */
  3280. page_offset = pwrctl->wowlan_aoac_rpt_loc;
  3281. page_number = 1;
  3282. rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, &page_size);
  3283. buf_size = page_size * page_number;
  3284. buffer = rtw_zvmalloc(buf_size);
  3285. if (NULL == buffer) {
  3286. RTW_ERR("%s buffer allocate failed size(%d)\n",
  3287. __func__, buf_size);
  3288. return;
  3289. }
  3290. RTW_INFO("Get AOAC Report from rsvd page_offset:%d\n", page_offset);
  3291. ret = rtw_hal_get_rsvd_page(adapter, page_offset,
  3292. page_number, buffer, buf_size);
  3293. if (ret == _FALSE) {
  3294. RTW_ERR("%s get aoac report failed\n", __func__);
  3295. rtw_warn_on(1);
  3296. goto _exit;
  3297. }
  3298. _rtw_memset(paoac_rpt, 0, sizeof(struct aoac_report));
  3299. _rtw_memcpy(paoac_rpt, buffer, sizeof(struct aoac_report));
  3300. for (i = 0 ; i < 4 ; i++) {
  3301. tmp = paoac_rpt->replay_counter_eapol_key[i];
  3302. paoac_rpt->replay_counter_eapol_key[i] =
  3303. paoac_rpt->replay_counter_eapol_key[7 - i];
  3304. paoac_rpt->replay_counter_eapol_key[7 - i] = tmp;
  3305. }
  3306. /* rtw_dump_aoac_rpt(adapter); */
  3307. _exit:
  3308. if (buffer)
  3309. rtw_vmfree(buffer, buf_size);
  3310. }
  3311. static void rtw_hal_update_gtk_offload_info(_adapter *adapter)
  3312. {
  3313. struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
  3314. struct aoac_report *paoac_rpt = &pwrctl->wowlan_aoac_rpt;
  3315. struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
  3316. struct security_priv *psecuritypriv = &adapter->securitypriv;
  3317. struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
  3318. struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
  3319. _irqL irqL;
  3320. u8 get_key[16];
  3321. u8 gtk_id = 0, offset = 0;
  3322. u64 replay_count = 0;
  3323. if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
  3324. return;
  3325. _rtw_memset(get_key, 0, sizeof(get_key));
  3326. _rtw_memcpy(&replay_count,
  3327. paoac_rpt->replay_counter_eapol_key, 8);
  3328. /*read gtk key index*/
  3329. gtk_id = paoac_rpt->key_index;
  3330. if (gtk_id == 5 || gtk_id == 0) {
  3331. RTW_INFO("%s no rekey event happened.\n", __func__);
  3332. } else if (gtk_id > 0 && gtk_id < 4) {
  3333. RTW_INFO("%s update security key.\n", __func__);
  3334. /*read key from sec-cam,for DK ,keyindex is equal to cam-id*/
  3335. rtw_sec_read_cam_ent(adapter, gtk_id,
  3336. NULL, NULL, get_key);
  3337. rtw_clean_hw_dk_cam(adapter);
  3338. if (_rtw_camid_is_gk(adapter, gtk_id)) {
  3339. _enter_critical_bh(&cam_ctl->lock, &irqL);
  3340. _rtw_memcpy(&dvobj->cam_cache[gtk_id].key,
  3341. get_key, 16);
  3342. _exit_critical_bh(&cam_ctl->lock, &irqL);
  3343. } else {
  3344. struct setkey_parm parm_gtk;
  3345. parm_gtk.algorithm = paoac_rpt->security_type;
  3346. parm_gtk.keyid = gtk_id;
  3347. _rtw_memcpy(parm_gtk.key, get_key, 16);
  3348. setkey_hdl(adapter, (u8 *)&parm_gtk);
  3349. }
  3350. /*update key into related sw variable and sec-cam cache*/
  3351. psecuritypriv->dot118021XGrpKeyid = gtk_id;
  3352. _rtw_memcpy(&psecuritypriv->dot118021XGrpKey[gtk_id],
  3353. get_key, 16);
  3354. /* update SW TKIP TX/RX MIC value */
  3355. if (psecuritypriv->dot118021XGrpPrivacy == _TKIP_) {
  3356. offset = RTW_KEK_LEN + RTW_TKIP_MIC_LEN;
  3357. _rtw_memcpy(
  3358. &psecuritypriv->dot118021XGrptxmickey[gtk_id],
  3359. &(paoac_rpt->group_key[offset]),
  3360. RTW_TKIP_MIC_LEN);
  3361. offset = RTW_KEK_LEN;
  3362. _rtw_memcpy(
  3363. &psecuritypriv->dot118021XGrprxmickey[gtk_id],
  3364. &(paoac_rpt->group_key[offset]),
  3365. RTW_TKIP_MIC_LEN);
  3366. }
  3367. RTW_PRINT("GTK (%d) "KEY_FMT"\n", gtk_id,
  3368. KEY_ARG(psecuritypriv->dot118021XGrpKey[gtk_id].skey));
  3369. }
  3370. rtw_clean_dk_section(adapter);
  3371. rtw_write8(adapter, REG_SECCFG, 0x0c);
  3372. #ifdef CONFIG_GTK_OL_DBG
  3373. /* if (gtk_keyindex != 5) */
  3374. dump_sec_cam(RTW_DBGDUMP, adapter);
  3375. dump_sec_cam_cache(RTW_DBGDUMP, adapter);
  3376. #endif
  3377. }
  3378. static void rtw_hal_update_tx_iv(_adapter *adapter)
  3379. {
  3380. struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
  3381. struct aoac_report *paoac_rpt = &pwrctl->wowlan_aoac_rpt;
  3382. struct sta_info *psta;
  3383. struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
  3384. struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
  3385. struct security_priv *psecpriv = &adapter->securitypriv;
  3386. u16 val16 = 0;
  3387. u32 val32 = 0;
  3388. u64 txiv = 0;
  3389. u8 *pval = NULL;
  3390. psta = rtw_get_stainfo(&adapter->stapriv,
  3391. get_my_bssid(&pmlmeinfo->network));
  3392. /* Update TX iv data. */
  3393. pval = (u8 *)&paoac_rpt->iv;
  3394. if (psecpriv->dot11PrivacyAlgrthm == _TKIP_) {
  3395. val16 = ((u16)(paoac_rpt->iv[2]) << 0) +
  3396. ((u16)(paoac_rpt->iv[0]) << 8);
  3397. val32 = ((u32)(paoac_rpt->iv[4]) << 0) +
  3398. ((u32)(paoac_rpt->iv[5]) << 8) +
  3399. ((u32)(paoac_rpt->iv[6]) << 16) +
  3400. ((u32)(paoac_rpt->iv[7]) << 24);
  3401. } else if (psecpriv->dot11PrivacyAlgrthm == _AES_) {
  3402. val16 = ((u16)(paoac_rpt->iv[0]) << 0) +
  3403. ((u16)(paoac_rpt->iv[1]) << 8);
  3404. val32 = ((u32)(paoac_rpt->iv[4]) << 0) +
  3405. ((u32)(paoac_rpt->iv[5]) << 8) +
  3406. ((u32)(paoac_rpt->iv[6]) << 16) +
  3407. ((u32)(paoac_rpt->iv[7]) << 24);
  3408. }
  3409. if (psta) {
  3410. txiv = val16 + ((u64)val32 << 16);
  3411. if (txiv != 0)
  3412. psta->dot11txpn.val = txiv;
  3413. }
  3414. }
  3415. static void rtw_hal_update_sw_security_info(_adapter *adapter)
  3416. {
  3417. rtw_hal_update_tx_iv(adapter);
  3418. rtw_hal_update_gtk_offload_info(adapter);
  3419. }
  3420. #endif /*CONFIG_GTK_OL*/
  3421. static u8 rtw_hal_set_keep_alive_cmd(_adapter *adapter, u8 enable, u8 pkt_type)
  3422. {
  3423. struct hal_ops *pHalFunc = &adapter->hal_func;
  3424. u8 u1H2CKeepAliveParm[H2C_KEEP_ALIVE_CTRL_LEN] = {0};
  3425. u8 adopt = 1, check_period = 5;
  3426. u8 ret = _FAIL;
  3427. SET_H2CCMD_KEEPALIVE_PARM_ENABLE(u1H2CKeepAliveParm, enable);
  3428. SET_H2CCMD_KEEPALIVE_PARM_ADOPT(u1H2CKeepAliveParm, adopt);
  3429. SET_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(u1H2CKeepAliveParm, pkt_type);
  3430. SET_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(u1H2CKeepAliveParm, check_period);
  3431. #ifdef CONFIG_FW_MULTI_PORT_SUPPORT
  3432. SET_H2CCMD_KEEPALIVE_PARM_PORT_NUM(u1H2CKeepAliveParm, adapter->hw_port);
  3433. RTW_INFO("%s(): enable = %d, port = %d\n", __func__, enable, adapter->hw_port);
  3434. #else
  3435. RTW_INFO("%s(): enable = %d\n", __func__, enable);
  3436. #endif
  3437. ret = rtw_hal_fill_h2c_cmd(adapter,
  3438. H2C_KEEP_ALIVE,
  3439. H2C_KEEP_ALIVE_CTRL_LEN,
  3440. u1H2CKeepAliveParm);
  3441. return ret;
  3442. }
  3443. static u8 rtw_hal_set_disconnect_decision_cmd(_adapter *adapter, u8 enable)
  3444. {
  3445. struct hal_ops *pHalFunc = &adapter->hal_func;
  3446. u8 u1H2CDisconDecisionParm[H2C_DISCON_DECISION_LEN] = {0};
  3447. u8 adopt = 1, check_period = 10, trypkt_num = 0;
  3448. u8 ret = _FAIL;
  3449. SET_H2CCMD_DISCONDECISION_PARM_ENABLE(u1H2CDisconDecisionParm, enable);
  3450. SET_H2CCMD_DISCONDECISION_PARM_ADOPT(u1H2CDisconDecisionParm, adopt);
  3451. SET_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(u1H2CDisconDecisionParm, check_period);
  3452. SET_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(u1H2CDisconDecisionParm, trypkt_num);
  3453. #ifdef CONFIG_FW_MULTI_PORT_SUPPORT
  3454. SET_H2CCMD_DISCONDECISION_PORT_NUM(u1H2CDisconDecisionParm, adapter->hw_port);
  3455. RTW_INFO("%s(): enable = %d, port = %d\n", __func__, enable, adapter->hw_port);
  3456. #else
  3457. RTW_INFO("%s(): enable = %d\n", __func__, enable);
  3458. #endif
  3459. ret = rtw_hal_fill_h2c_cmd(adapter,
  3460. H2C_DISCON_DECISION,
  3461. H2C_DISCON_DECISION_LEN,
  3462. u1H2CDisconDecisionParm);
  3463. return ret;
  3464. }
  3465. static u8 rtw_hal_set_wowlan_ctrl_cmd(_adapter *adapter, u8 enable, u8 change_unit)
  3466. {
  3467. struct security_priv *psecpriv = &adapter->securitypriv;
  3468. struct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(adapter);
  3469. struct hal_ops *pHalFunc = &adapter->hal_func;
  3470. u8 u1H2CWoWlanCtrlParm[H2C_WOWLAN_LEN] = {0};
  3471. u8 discont_wake = 1, gpionum = 0, gpio_dur = 0;
  3472. u8 hw_unicast = 0, gpio_pulse_cnt = 0, gpio_pulse_en = 0;
  3473. u8 sdio_wakeup_enable = 1;
  3474. u8 gpio_high_active = 0;
  3475. u8 magic_pkt = 0;
  3476. u8 gpio_unit = 0; /*0: 64ns, 1: 8ms*/
  3477. u8 ret = _FAIL;
  3478. #ifdef CONFIG_GPIO_WAKEUP
  3479. gpio_high_active = ppwrpriv->is_high_active;
  3480. gpionum = WAKEUP_GPIO_IDX;
  3481. sdio_wakeup_enable = 0;
  3482. #endif /* CONFIG_GPIO_WAKEUP */
  3483. if (!ppwrpriv->wowlan_pno_enable)
  3484. magic_pkt = enable;
  3485. #ifndef CONFIG_DEFAULT_PATTERNS_EN
  3486. if (psecpriv->dot11PrivacyAlgrthm == _WEP40_ || psecpriv->dot11PrivacyAlgrthm == _WEP104_)
  3487. hw_unicast = 1;
  3488. else
  3489. hw_unicast = 0;
  3490. #endif
  3491. RTW_INFO("%s(): enable=%d change_unit=%d\n", __func__,
  3492. enable, change_unit);
  3493. /* time = (gpio_dur/2) * gpio_unit, default:256 ms */
  3494. if (enable && change_unit) {
  3495. gpio_dur = 0x40;
  3496. gpio_unit = 1;
  3497. gpio_pulse_en = 1;
  3498. }
  3499. #ifdef CONFIG_PLATFORM_ARM_RK3188
  3500. if (enable) {
  3501. gpio_pulse_en = 1;
  3502. gpio_pulse_cnt = 0x04;
  3503. }
  3504. #endif
  3505. SET_H2CCMD_WOWLAN_FUNC_ENABLE(u1H2CWoWlanCtrlParm, enable);
  3506. SET_H2CCMD_WOWLAN_PATTERN_MATCH_ENABLE(u1H2CWoWlanCtrlParm, enable);
  3507. SET_H2CCMD_WOWLAN_MAGIC_PKT_ENABLE(u1H2CWoWlanCtrlParm, magic_pkt);
  3508. SET_H2CCMD_WOWLAN_UNICAST_PKT_ENABLE(u1H2CWoWlanCtrlParm, hw_unicast);
  3509. SET_H2CCMD_WOWLAN_ALL_PKT_DROP(u1H2CWoWlanCtrlParm, 0);
  3510. SET_H2CCMD_WOWLAN_GPIO_ACTIVE(u1H2CWoWlanCtrlParm, gpio_high_active);
  3511. #ifdef CONFIG_GTK_OL
  3512. /* GTK rekey only for AES, if GTK rekey is TKIP, then wake up*/
  3513. if (psecpriv->binstallKCK_KEK == _TRUE)
  3514. SET_H2CCMD_WOWLAN_REKEY_WAKE_UP(u1H2CWoWlanCtrlParm, 0);
  3515. else
  3516. SET_H2CCMD_WOWLAN_REKEY_WAKE_UP(u1H2CWoWlanCtrlParm, 1);
  3517. #else
  3518. SET_H2CCMD_WOWLAN_REKEY_WAKE_UP(u1H2CWoWlanCtrlParm, enable);
  3519. #endif
  3520. SET_H2CCMD_WOWLAN_DISCONNECT_WAKE_UP(u1H2CWoWlanCtrlParm, discont_wake);
  3521. SET_H2CCMD_WOWLAN_GPIONUM(u1H2CWoWlanCtrlParm, gpionum);
  3522. SET_H2CCMD_WOWLAN_DATAPIN_WAKE_UP(u1H2CWoWlanCtrlParm, sdio_wakeup_enable);
  3523. SET_H2CCMD_WOWLAN_GPIO_DURATION(u1H2CWoWlanCtrlParm, gpio_dur);
  3524. SET_H2CCMD_WOWLAN_CHANGE_UNIT(u1H2CWoWlanCtrlParm, gpio_unit);
  3525. SET_H2CCMD_WOWLAN_GPIO_PULSE_EN(u1H2CWoWlanCtrlParm, gpio_pulse_en);
  3526. SET_H2CCMD_WOWLAN_GPIO_PULSE_COUNT(u1H2CWoWlanCtrlParm, gpio_pulse_cnt);
  3527. #ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE
  3528. if (enable)
  3529. SET_H2CCMD_WOWLAN_GPIO_INPUT_EN(u1H2CWoWlanCtrlParm, 1);
  3530. #endif
  3531. ret = rtw_hal_fill_h2c_cmd(adapter,
  3532. H2C_WOWLAN,
  3533. H2C_WOWLAN_LEN,
  3534. u1H2CWoWlanCtrlParm);
  3535. return ret;
  3536. }
  3537. static u8 rtw_hal_set_remote_wake_ctrl_cmd(_adapter *adapter, u8 enable)
  3538. {
  3539. struct hal_ops *pHalFunc = &adapter->hal_func;
  3540. struct security_priv *psecuritypriv = &(adapter->securitypriv);
  3541. struct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(adapter);
  3542. struct registry_priv *pregistrypriv = &adapter->registrypriv;
  3543. u8 u1H2CRemoteWakeCtrlParm[H2C_REMOTE_WAKE_CTRL_LEN] = {0};
  3544. u8 ret = _FAIL, count = 0;
  3545. RTW_INFO("%s(): enable=%d\n", __func__, enable);
  3546. if (!ppwrpriv->wowlan_pno_enable) {
  3547. SET_H2CCMD_REMOTE_WAKECTRL_ENABLE(
  3548. u1H2CRemoteWakeCtrlParm, enable);
  3549. SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_OFFLOAD_EN(
  3550. u1H2CRemoteWakeCtrlParm, 1);
  3551. #ifdef CONFIG_GTK_OL
  3552. if (psecuritypriv->binstallKCK_KEK == _TRUE) {
  3553. SET_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(
  3554. u1H2CRemoteWakeCtrlParm, 1);
  3555. } else {
  3556. RTW_INFO("no kck kek\n");
  3557. SET_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(
  3558. u1H2CRemoteWakeCtrlParm, 0);
  3559. }
  3560. #endif /* CONFIG_GTK_OL */
  3561. if (pregistrypriv->default_patterns_en == _FALSE) {
  3562. SET_H2CCMD_REMOTE_WAKE_CTRL_FW_UNICAST_EN(
  3563. u1H2CRemoteWakeCtrlParm, enable);
  3564. /*
  3565. * filter NetBios name service pkt to avoid being waked-up
  3566. * by this kind of unicast pkt this exceptional modification
  3567. * is used for match competitor's behavior
  3568. */
  3569. SET_H2CCMD_REMOTE_WAKE_CTRL_NBNS_FILTER_EN(
  3570. u1H2CRemoteWakeCtrlParm, enable);
  3571. }
  3572. if ((psecuritypriv->dot11PrivacyAlgrthm == _AES_) ||
  3573. (psecuritypriv->dot11PrivacyAlgrthm == _TKIP_) ||
  3574. (psecuritypriv->dot11PrivacyAlgrthm == _NO_PRIVACY_)) {
  3575. SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_ACTION(
  3576. u1H2CRemoteWakeCtrlParm, 0);
  3577. } else {
  3578. SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_ACTION(
  3579. u1H2CRemoteWakeCtrlParm, 1);
  3580. }
  3581. if (psecuritypriv->dot11PrivacyAlgrthm == _TKIP_) {
  3582. SET_H2CCMD_REMOTE_WAKE_CTRL_TKIP_OFFLOAD_EN(
  3583. u1H2CRemoteWakeCtrlParm, enable);
  3584. if (IS_HARDWARE_TYPE_8188E(adapter) ||
  3585. IS_HARDWARE_TYPE_8812(adapter)) {
  3586. SET_H2CCMD_REMOTE_WAKE_CTRL_TKIP_OFFLOAD_EN(
  3587. u1H2CRemoteWakeCtrlParm, 0);
  3588. SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_ACTION(
  3589. u1H2CRemoteWakeCtrlParm, 1);
  3590. }
  3591. }
  3592. SET_H2CCMD_REMOTE_WAKE_CTRL_FW_PARSING_UNTIL_WAKEUP(
  3593. u1H2CRemoteWakeCtrlParm, 1);
  3594. }
  3595. #ifdef CONFIG_PNO_SUPPORT
  3596. else {
  3597. SET_H2CCMD_REMOTE_WAKECTRL_ENABLE(
  3598. u1H2CRemoteWakeCtrlParm, enable);
  3599. SET_H2CCMD_REMOTE_WAKE_CTRL_NLO_OFFLOAD_EN(
  3600. u1H2CRemoteWakeCtrlParm, enable);
  3601. }
  3602. #endif
  3603. #ifdef CONFIG_P2P_WOWLAN
  3604. if (_TRUE == ppwrpriv->wowlan_p2p_mode) {
  3605. RTW_INFO("P2P OFFLOAD ENABLE\n");
  3606. SET_H2CCMD_REMOTE_WAKE_CTRL_P2P_OFFLAD_EN(u1H2CRemoteWakeCtrlParm, 1);
  3607. } else {
  3608. RTW_INFO("P2P OFFLOAD DISABLE\n");
  3609. SET_H2CCMD_REMOTE_WAKE_CTRL_P2P_OFFLAD_EN(u1H2CRemoteWakeCtrlParm, 0);
  3610. }
  3611. #endif /* CONFIG_P2P_WOWLAN */
  3612. ret = rtw_hal_fill_h2c_cmd(adapter,
  3613. H2C_REMOTE_WAKE_CTRL,
  3614. H2C_REMOTE_WAKE_CTRL_LEN,
  3615. u1H2CRemoteWakeCtrlParm);
  3616. return ret;
  3617. }
  3618. static u8 rtw_hal_set_global_info_cmd(_adapter *adapter, u8 group_alg, u8 pairwise_alg)
  3619. {
  3620. struct hal_ops *pHalFunc = &adapter->hal_func;
  3621. u8 ret = _FAIL;
  3622. u8 u1H2CAOACGlobalInfoParm[H2C_AOAC_GLOBAL_INFO_LEN] = {0};
  3623. RTW_INFO("%s(): group_alg=%d pairwise_alg=%d\n",
  3624. __func__, group_alg, pairwise_alg);
  3625. SET_H2CCMD_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(u1H2CAOACGlobalInfoParm,
  3626. pairwise_alg);
  3627. SET_H2CCMD_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(u1H2CAOACGlobalInfoParm,
  3628. group_alg);
  3629. ret = rtw_hal_fill_h2c_cmd(adapter,
  3630. H2C_AOAC_GLOBAL_INFO,
  3631. H2C_AOAC_GLOBAL_INFO_LEN,
  3632. u1H2CAOACGlobalInfoParm);
  3633. return ret;
  3634. }
  3635. #ifdef CONFIG_PNO_SUPPORT
  3636. static u8 rtw_hal_set_scan_offload_info_cmd(_adapter *adapter,
  3637. PRSVDPAGE_LOC rsvdpageloc, u8 enable)
  3638. {
  3639. struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
  3640. struct hal_ops *pHalFunc = &adapter->hal_func;
  3641. u8 u1H2CScanOffloadInfoParm[H2C_SCAN_OFFLOAD_CTRL_LEN] = {0};
  3642. u8 res = 0, count = 0, ret = _FAIL;
  3643. RTW_INFO("%s: loc_probe_packet:%d, loc_scan_info: %d loc_ssid_info:%d\n",
  3644. __func__, rsvdpageloc->LocProbePacket,
  3645. rsvdpageloc->LocScanInfo, rsvdpageloc->LocSSIDInfo);
  3646. SET_H2CCMD_AOAC_NLO_FUN_EN(u1H2CScanOffloadInfoParm, enable);
  3647. SET_H2CCMD_AOAC_NLO_IPS_EN(u1H2CScanOffloadInfoParm, enable);
  3648. SET_H2CCMD_AOAC_RSVDPAGE_LOC_SCAN_INFO(u1H2CScanOffloadInfoParm,
  3649. rsvdpageloc->LocScanInfo);
  3650. SET_H2CCMD_AOAC_RSVDPAGE_LOC_PROBE_PACKET(u1H2CScanOffloadInfoParm,
  3651. rsvdpageloc->LocProbePacket);
  3652. /*
  3653. SET_H2CCMD_AOAC_RSVDPAGE_LOC_SSID_INFO(u1H2CScanOffloadInfoParm,
  3654. rsvdpageloc->LocSSIDInfo);
  3655. */
  3656. ret = rtw_hal_fill_h2c_cmd(adapter,
  3657. H2C_D0_SCAN_OFFLOAD_INFO,
  3658. H2C_SCAN_OFFLOAD_CTRL_LEN,
  3659. u1H2CScanOffloadInfoParm);
  3660. return ret;
  3661. }
  3662. #endif /* CONFIG_PNO_SUPPORT */
  3663. void rtw_hal_set_fw_wow_related_cmd(_adapter *padapter, u8 enable)
  3664. {
  3665. struct security_priv *psecpriv = &padapter->securitypriv;
  3666. struct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(padapter);
  3667. struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
  3668. struct sta_info *psta = NULL;
  3669. u16 media_status_rpt;
  3670. u8 pkt_type = 0;
  3671. u8 ret = _SUCCESS;
  3672. RTW_PRINT("+%s()+: enable=%d\n", __func__, enable);
  3673. rtw_hal_set_wowlan_ctrl_cmd(padapter, enable, _FALSE);
  3674. if (enable) {
  3675. rtw_hal_set_global_info_cmd(padapter,
  3676. psecpriv->dot118021XGrpPrivacy,
  3677. psecpriv->dot11PrivacyAlgrthm);
  3678. if (!(ppwrpriv->wowlan_pno_enable)) {
  3679. rtw_hal_set_disconnect_decision_cmd(padapter, enable);
  3680. #ifdef CONFIG_ARP_KEEP_ALIVE
  3681. if ((psecpriv->dot11PrivacyAlgrthm == _WEP40_) ||
  3682. (psecpriv->dot11PrivacyAlgrthm == _WEP104_))
  3683. pkt_type = 0;
  3684. else
  3685. pkt_type = 1;
  3686. #else
  3687. pkt_type = 0;
  3688. #endif /* CONFIG_ARP_KEEP_ALIVE */
  3689. rtw_hal_set_keep_alive_cmd(padapter, enable, pkt_type);
  3690. }
  3691. rtw_hal_set_remote_wake_ctrl_cmd(padapter, enable);
  3692. #ifdef CONFIG_PNO_SUPPORT
  3693. rtw_hal_check_pno_enabled(padapter);
  3694. #endif /* CONFIG_PNO_SUPPORT */
  3695. } else {
  3696. #if 0
  3697. {
  3698. u32 PageSize = 0;
  3699. rtw_hal_get_def_var(padapter, HAL_DEF_TX_PAGE_SIZE, (u8 *)&PageSize);
  3700. dump_TX_FIFO(padapter, 4, PageSize);
  3701. }
  3702. #endif
  3703. rtw_hal_set_remote_wake_ctrl_cmd(padapter, enable);
  3704. }
  3705. RTW_PRINT("-%s()-\n", __func__);
  3706. }
  3707. #endif /* CONFIG_WOWLAN */
  3708. #ifdef CONFIG_AP_WOWLAN
  3709. static u8 rtw_hal_set_ap_wowlan_ctrl_cmd(_adapter *adapter, u8 enable)
  3710. {
  3711. struct security_priv *psecpriv = &adapter->securitypriv;
  3712. struct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(adapter);
  3713. struct hal_ops *pHalFunc = &adapter->hal_func;
  3714. u8 u1H2CAPWoWlanCtrlParm[H2C_AP_WOW_GPIO_CTRL_LEN] = {0};
  3715. u8 gpionum = 0, gpio_dur = 0;
  3716. u8 gpio_pulse = enable;
  3717. u8 sdio_wakeup_enable = 1;
  3718. u8 gpio_high_active = 0;
  3719. u8 ret = _FAIL;
  3720. #ifdef CONFIG_GPIO_WAKEUP
  3721. gpio_high_active = ppwrpriv->is_high_active;
  3722. gpionum = WAKEUP_GPIO_IDX;
  3723. sdio_wakeup_enable = 0;
  3724. #endif /*CONFIG_GPIO_WAKEUP*/
  3725. RTW_INFO("%s(): enable=%d\n", __func__, enable);
  3726. SET_H2CCMD_AP_WOW_GPIO_CTRL_INDEX(u1H2CAPWoWlanCtrlParm,
  3727. gpionum);
  3728. SET_H2CCMD_AP_WOW_GPIO_CTRL_PLUS(u1H2CAPWoWlanCtrlParm,
  3729. gpio_pulse);
  3730. SET_H2CCMD_AP_WOW_GPIO_CTRL_HIGH_ACTIVE(u1H2CAPWoWlanCtrlParm,
  3731. gpio_high_active);
  3732. SET_H2CCMD_AP_WOW_GPIO_CTRL_EN(u1H2CAPWoWlanCtrlParm,
  3733. enable);
  3734. SET_H2CCMD_AP_WOW_GPIO_CTRL_DURATION(u1H2CAPWoWlanCtrlParm,
  3735. gpio_dur);
  3736. ret = rtw_hal_fill_h2c_cmd(adapter,
  3737. H2C_AP_WOW_GPIO_CTRL,
  3738. H2C_AP_WOW_GPIO_CTRL_LEN,
  3739. u1H2CAPWoWlanCtrlParm);
  3740. return ret;
  3741. }
  3742. static u8 rtw_hal_set_ap_offload_ctrl_cmd(_adapter *adapter, u8 enable)
  3743. {
  3744. struct hal_ops *pHalFunc = &adapter->hal_func;
  3745. u8 u1H2CAPOffloadCtrlParm[H2C_WOWLAN_LEN] = {0};
  3746. u8 ret = _FAIL;
  3747. RTW_INFO("%s(): bFuncEn=%d\n", __func__, enable);
  3748. SET_H2CCMD_AP_WOWLAN_EN(u1H2CAPOffloadCtrlParm, enable);
  3749. ret = rtw_hal_fill_h2c_cmd(adapter,
  3750. H2C_AP_OFFLOAD,
  3751. H2C_AP_OFFLOAD_LEN,
  3752. u1H2CAPOffloadCtrlParm);
  3753. return ret;
  3754. }
  3755. static u8 rtw_hal_set_ap_ps_cmd(_adapter *adapter, u8 enable)
  3756. {
  3757. struct hal_ops *pHalFunc = &adapter->hal_func;
  3758. u8 ap_ps_parm[H2C_AP_PS_LEN] = {0};
  3759. u8 ret = _FAIL;
  3760. RTW_INFO("%s(): enable=%d\n" , __func__ , enable);
  3761. SET_H2CCMD_AP_WOW_PS_EN(ap_ps_parm, enable);
  3762. #ifndef CONFIG_USB_HCI
  3763. SET_H2CCMD_AP_WOW_PS_32K_EN(ap_ps_parm, enable);
  3764. #endif /*CONFIG_USB_HCI*/
  3765. SET_H2CCMD_AP_WOW_PS_RF(ap_ps_parm, enable);
  3766. if (enable)
  3767. SET_H2CCMD_AP_WOW_PS_DURATION(ap_ps_parm, 0x32);
  3768. else
  3769. SET_H2CCMD_AP_WOW_PS_DURATION(ap_ps_parm, 0x0);
  3770. ret = rtw_hal_fill_h2c_cmd(adapter, H2C_SAP_PS_,
  3771. H2C_AP_PS_LEN, ap_ps_parm);
  3772. return ret;
  3773. }
  3774. static void rtw_hal_set_ap_rsvdpage_loc_cmd(PADAPTER padapter,
  3775. PRSVDPAGE_LOC rsvdpageloc)
  3776. {
  3777. struct hal_ops *pHalFunc = &padapter->hal_func;
  3778. u8 rsvdparm[H2C_AOAC_RSVDPAGE_LOC_LEN] = {0};
  3779. u8 ret = _FAIL, header = 0;
  3780. if (pHalFunc->fill_h2c_cmd == NULL) {
  3781. RTW_INFO("%s: Please hook fill_h2c_cmd first!\n", __func__);
  3782. return;
  3783. }
  3784. header = rtw_read8(padapter, REG_BCNQ_BDNY);
  3785. RTW_INFO("%s: beacon: %d, probeRsp: %d, header:0x%02x\n", __func__,
  3786. rsvdpageloc->LocApOffloadBCN,
  3787. rsvdpageloc->LocProbeRsp,
  3788. header);
  3789. SET_H2CCMD_AP_WOWLAN_RSVDPAGE_LOC_BCN(rsvdparm,
  3790. rsvdpageloc->LocApOffloadBCN + header);
  3791. ret = rtw_hal_fill_h2c_cmd(padapter, H2C_BCN_RSVDPAGE,
  3792. H2C_BCN_RSVDPAGE_LEN, rsvdparm);
  3793. if (ret == _FAIL)
  3794. RTW_INFO("%s: H2C_BCN_RSVDPAGE cmd fail\n", __func__);
  3795. rtw_msleep_os(10);
  3796. _rtw_memset(&rsvdparm, 0, sizeof(rsvdparm));
  3797. SET_H2CCMD_AP_WOWLAN_RSVDPAGE_LOC_ProbeRsp(rsvdparm,
  3798. rsvdpageloc->LocProbeRsp + header);
  3799. ret = rtw_hal_fill_h2c_cmd(padapter, H2C_PROBERSP_RSVDPAGE,
  3800. H2C_PROBERSP_RSVDPAGE_LEN, rsvdparm);
  3801. if (ret == _FAIL)
  3802. RTW_INFO("%s: H2C_PROBERSP_RSVDPAGE cmd fail\n", __func__);
  3803. rtw_msleep_os(10);
  3804. }
  3805. static void rtw_hal_set_fw_ap_wow_related_cmd(_adapter *padapter, u8 enable)
  3806. {
  3807. rtw_hal_set_ap_offload_ctrl_cmd(padapter, enable);
  3808. rtw_hal_set_ap_wowlan_ctrl_cmd(padapter, enable);
  3809. rtw_hal_set_ap_ps_cmd(padapter, enable);
  3810. }
  3811. static void rtw_hal_ap_wow_enable(_adapter *padapter)
  3812. {
  3813. struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
  3814. struct security_priv *psecuritypriv = &padapter->securitypriv;
  3815. struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
  3816. struct hal_ops *pHalFunc = &padapter->hal_func;
  3817. struct sta_info *psta = NULL;
  3818. PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
  3819. #ifdef DBG_CHECK_FW_PS_STATE
  3820. struct dvobj_priv *psdpriv = padapter->dvobj;
  3821. struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
  3822. #endif /*DBG_CHECK_FW_PS_STATE*/
  3823. int res;
  3824. u16 media_status_rpt;
  3825. RTW_INFO("%s, WOWLAN_AP_ENABLE\n", __func__);
  3826. #ifdef DBG_CHECK_FW_PS_STATE
  3827. if (rtw_fw_ps_state(padapter) == _FAIL) {
  3828. pdbgpriv->dbg_enwow_dload_fw_fail_cnt++;
  3829. RTW_PRINT("wowlan enable no leave 32k\n");
  3830. }
  3831. #endif /*DBG_CHECK_FW_PS_STATE*/
  3832. /* 1. Download WOWLAN FW*/
  3833. rtw_hal_fw_dl(padapter, _TRUE);
  3834. media_status_rpt = RT_MEDIA_CONNECT;
  3835. rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_JOINBSSRPT,
  3836. (u8 *)&media_status_rpt);
  3837. issue_beacon(padapter, 0);
  3838. rtw_msleep_os(2);
  3839. #if defined(CONFIG_RTL8188E)
  3840. if (IS_HARDWARE_TYPE_8188E(padapter))
  3841. rtw_hal_disable_tx_report(padapter);
  3842. #endif
  3843. /* RX DMA stop */
  3844. res = rtw_hal_pause_rx_dma(padapter);
  3845. if (res == _FAIL)
  3846. RTW_PRINT("[WARNING] pause RX DMA fail\n");
  3847. #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
  3848. /* Enable CPWM2 only. */
  3849. res = rtw_hal_enable_cpwm2(padapter);
  3850. if (res == _FAIL)
  3851. RTW_PRINT("[WARNING] enable cpwm2 fail\n");
  3852. #endif
  3853. #ifdef CONFIG_GPIO_WAKEUP
  3854. rtw_hal_switch_gpio_wl_ctrl(padapter, WAKEUP_GPIO_IDX, _TRUE);
  3855. #endif
  3856. /* 5. Set Enable WOWLAN H2C command. */
  3857. RTW_PRINT("Set Enable AP WOWLan cmd\n");
  3858. rtw_hal_set_fw_ap_wow_related_cmd(padapter, 1);
  3859. rtw_write8(padapter, REG_MCUTST_WOWLAN, 0);
  3860. #ifdef CONFIG_USB_HCI
  3861. rtw_mi_intf_stop(padapter);
  3862. #endif
  3863. #if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
  3864. /* Invoid SE0 reset signal during suspending*/
  3865. rtw_write8(padapter, REG_RSV_CTRL, 0x20);
  3866. if (IS_8188F(pHalData->version_id) == FALSE)
  3867. rtw_write8(padapter, REG_RSV_CTRL, 0x60);
  3868. #endif
  3869. }
  3870. static void rtw_hal_ap_wow_disable(_adapter *padapter)
  3871. {
  3872. struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
  3873. struct hal_ops *pHalFunc = &padapter->hal_func;
  3874. #ifdef DBG_CHECK_FW_PS_STATE
  3875. struct dvobj_priv *psdpriv = padapter->dvobj;
  3876. struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
  3877. #endif /*DBG_CHECK_FW_PS_STATE*/
  3878. u16 media_status_rpt;
  3879. u8 val8;
  3880. RTW_INFO("%s, WOWLAN_AP_DISABLE\n", __func__);
  3881. /* 1. Read wakeup reason*/
  3882. pwrctl->wowlan_wake_reason = rtw_read8(padapter, REG_MCUTST_WOWLAN);
  3883. RTW_PRINT("wakeup_reason: 0x%02x\n",
  3884. pwrctl->wowlan_wake_reason);
  3885. rtw_hal_set_fw_ap_wow_related_cmd(padapter, 0);
  3886. rtw_msleep_os(2);
  3887. #ifdef DBG_CHECK_FW_PS_STATE
  3888. if (rtw_fw_ps_state(padapter) == _FAIL) {
  3889. pdbgpriv->dbg_diswow_dload_fw_fail_cnt++;
  3890. RTW_PRINT("wowlan enable no leave 32k\n");
  3891. }
  3892. #endif /*DBG_CHECK_FW_PS_STATE*/
  3893. #if defined(CONFIG_RTL8188E)
  3894. if (IS_HARDWARE_TYPE_8188E(padapter))
  3895. rtw_hal_enable_tx_report(padapter);
  3896. #endif
  3897. rtw_hal_force_enable_rxdma(padapter);
  3898. rtw_hal_fw_dl(padapter, _FALSE);
  3899. #ifdef CONFIG_GPIO_WAKEUP
  3900. #ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE
  3901. if (pwrctl->is_high_active == 0)
  3902. rtw_hal_set_input_gpio(padapter, WAKEUP_GPIO_IDX);
  3903. else
  3904. rtw_hal_set_output_gpio(padapter, WAKEUP_GPIO_IDX, 0);
  3905. #else
  3906. val8 = (pwrctl->is_high_active == 0) ? 1 : 0;
  3907. RTW_PRINT("Set Wake GPIO to default(%d).\n", val8);
  3908. rtw_hal_set_output_gpio(padapter, WAKEUP_GPIO_IDX, val8);
  3909. rtw_hal_switch_gpio_wl_ctrl(padapter, WAKEUP_GPIO_IDX, _FALSE);
  3910. #endif/*CONFIG_WAKEUP_GPIO_INPUT_MODE*/
  3911. #endif
  3912. media_status_rpt = RT_MEDIA_CONNECT;
  3913. rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_JOINBSSRPT,
  3914. (u8 *)&media_status_rpt);
  3915. issue_beacon(padapter, 0);
  3916. }
  3917. #endif /*CONFIG_AP_WOWLAN*/
  3918. #ifdef CONFIG_P2P_WOWLAN
  3919. static int update_hidden_ssid(u8 *ies, u32 ies_len, u8 hidden_ssid_mode)
  3920. {
  3921. u8 *ssid_ie;
  3922. sint ssid_len_ori;
  3923. int len_diff = 0;
  3924. ssid_ie = rtw_get_ie(ies, WLAN_EID_SSID, &ssid_len_ori, ies_len);
  3925. /* RTW_INFO("%s hidden_ssid_mode:%u, ssid_ie:%p, ssid_len_ori:%d\n", __FUNCTION__, hidden_ssid_mode, ssid_ie, ssid_len_ori); */
  3926. if (ssid_ie && ssid_len_ori > 0) {
  3927. switch (hidden_ssid_mode) {
  3928. case 1: {
  3929. u8 *next_ie = ssid_ie + 2 + ssid_len_ori;
  3930. u32 remain_len = 0;
  3931. remain_len = ies_len - (next_ie - ies);
  3932. ssid_ie[1] = 0;
  3933. _rtw_memcpy(ssid_ie + 2, next_ie, remain_len);
  3934. len_diff -= ssid_len_ori;
  3935. break;
  3936. }
  3937. case 2:
  3938. _rtw_memset(&ssid_ie[2], 0, ssid_len_ori);
  3939. break;
  3940. default:
  3941. break;
  3942. }
  3943. }
  3944. return len_diff;
  3945. }
  3946. static void rtw_hal_construct_P2PBeacon(_adapter *padapter, u8 *pframe, u32 *pLength)
  3947. {
  3948. /* struct xmit_frame *pmgntframe; */
  3949. /* struct pkt_attrib *pattrib; */
  3950. /* unsigned char *pframe; */
  3951. struct rtw_ieee80211_hdr *pwlanhdr;
  3952. unsigned short *fctrl;
  3953. unsigned int rate_len;
  3954. struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
  3955. u32 pktlen;
  3956. /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
  3957. /* _irqL irqL;
  3958. * struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
  3959. * #endif */ /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
  3960. struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
  3961. struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
  3962. struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
  3963. WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
  3964. u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
  3965. #ifdef CONFIG_P2P
  3966. struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
  3967. #endif /* CONFIG_P2P */
  3968. /* for debug */
  3969. u8 *dbgbuf = pframe;
  3970. u8 dbgbufLen = 0, index = 0;
  3971. RTW_INFO("%s\n", __FUNCTION__);
  3972. /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
  3973. /* _enter_critical_bh(&pmlmepriv->bcn_update_lock, &irqL);
  3974. * #endif */ /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
  3975. pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
  3976. fctrl = &(pwlanhdr->frame_ctl);
  3977. *(fctrl) = 0;
  3978. _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
  3979. _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
  3980. _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN);
  3981. SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/);
  3982. /* pmlmeext->mgnt_seq++; */
  3983. set_frame_sub_type(pframe, WIFI_BEACON);
  3984. pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
  3985. pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
  3986. if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {
  3987. /* RTW_INFO("ie len=%d\n", cur_network->IELength); */
  3988. #ifdef CONFIG_P2P
  3989. /* for P2P : Primary Device Type & Device Name */
  3990. u32 wpsielen = 0, insert_len = 0;
  3991. u8 *wpsie = NULL;
  3992. wpsie = rtw_get_wps_ie(cur_network->IEs + _FIXED_IE_LENGTH_, cur_network->IELength - _FIXED_IE_LENGTH_, NULL, &wpsielen);
  3993. if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) && wpsie && wpsielen > 0) {
  3994. uint wps_offset, remainder_ielen;
  3995. u8 *premainder_ie, *pframe_wscie;
  3996. wps_offset = (uint)(wpsie - cur_network->IEs);
  3997. premainder_ie = wpsie + wpsielen;
  3998. remainder_ielen = cur_network->IELength - wps_offset - wpsielen;
  3999. #ifdef CONFIG_IOCTL_CFG80211
  4000. if (pwdinfo->driver_interface == DRIVER_CFG80211) {
  4001. if (pmlmepriv->wps_beacon_ie && pmlmepriv->wps_beacon_ie_len > 0) {
  4002. _rtw_memcpy(pframe, cur_network->IEs, wps_offset);
  4003. pframe += wps_offset;
  4004. pktlen += wps_offset;
  4005. _rtw_memcpy(pframe, pmlmepriv->wps_beacon_ie, pmlmepriv->wps_beacon_ie_len);
  4006. pframe += pmlmepriv->wps_beacon_ie_len;
  4007. pktlen += pmlmepriv->wps_beacon_ie_len;
  4008. /* copy remainder_ie to pframe */
  4009. _rtw_memcpy(pframe, premainder_ie, remainder_ielen);
  4010. pframe += remainder_ielen;
  4011. pktlen += remainder_ielen;
  4012. } else {
  4013. _rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength);
  4014. pframe += cur_network->IELength;
  4015. pktlen += cur_network->IELength;
  4016. }
  4017. } else
  4018. #endif /* CONFIG_IOCTL_CFG80211 */
  4019. {
  4020. pframe_wscie = pframe + wps_offset;
  4021. _rtw_memcpy(pframe, cur_network->IEs, wps_offset + wpsielen);
  4022. pframe += (wps_offset + wpsielen);
  4023. pktlen += (wps_offset + wpsielen);
  4024. /* now pframe is end of wsc ie, insert Primary Device Type & Device Name */
  4025. /* Primary Device Type */
  4026. /* Type: */
  4027. *(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_ATTR_PRIMARY_DEV_TYPE);
  4028. insert_len += 2;
  4029. /* Length: */
  4030. *(u16 *)(pframe + insert_len) = cpu_to_be16(0x0008);
  4031. insert_len += 2;
  4032. /* Value: */
  4033. /* Category ID */
  4034. *(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);
  4035. insert_len += 2;
  4036. /* OUI */
  4037. *(u32 *)(pframe + insert_len) = cpu_to_be32(WPSOUI);
  4038. insert_len += 4;
  4039. /* Sub Category ID */
  4040. *(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);
  4041. insert_len += 2;
  4042. /* Device Name */
  4043. /* Type: */
  4044. *(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);
  4045. insert_len += 2;
  4046. /* Length: */
  4047. *(u16 *)(pframe + insert_len) = cpu_to_be16(pwdinfo->device_name_len);
  4048. insert_len += 2;
  4049. /* Value: */
  4050. _rtw_memcpy(pframe + insert_len, pwdinfo->device_name, pwdinfo->device_name_len);
  4051. insert_len += pwdinfo->device_name_len;
  4052. /* update wsc ie length */
  4053. *(pframe_wscie + 1) = (wpsielen - 2) + insert_len;
  4054. /* pframe move to end */
  4055. pframe += insert_len;
  4056. pktlen += insert_len;
  4057. /* copy remainder_ie to pframe */
  4058. _rtw_memcpy(pframe, premainder_ie, remainder_ielen);
  4059. pframe += remainder_ielen;
  4060. pktlen += remainder_ielen;
  4061. }
  4062. } else
  4063. #endif /* CONFIG_P2P */
  4064. {
  4065. int len_diff;
  4066. _rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength);
  4067. len_diff = update_hidden_ssid(
  4068. pframe + _BEACON_IE_OFFSET_
  4069. , cur_network->IELength - _BEACON_IE_OFFSET_
  4070. , pmlmeinfo->hidden_ssid_mode
  4071. );
  4072. pframe += (cur_network->IELength + len_diff);
  4073. pktlen += (cur_network->IELength + len_diff);
  4074. }
  4075. #if 0
  4076. {
  4077. u8 *wps_ie;
  4078. uint wps_ielen;
  4079. u8 sr = 0;
  4080. wps_ie = rtw_get_wps_ie(pmgntframe->buf_addr + TXDESC_OFFSET + sizeof(struct rtw_ieee80211_hdr_3addr) + _BEACON_IE_OFFSET_,
  4081. pattrib->pktlen - sizeof(struct rtw_ieee80211_hdr_3addr) - _BEACON_IE_OFFSET_, NULL, &wps_ielen);
  4082. if (wps_ie && wps_ielen > 0)
  4083. rtw_get_wps_attr_content(wps_ie, wps_ielen, WPS_ATTR_SELECTED_REGISTRAR, (u8 *)(&sr), NULL);
  4084. if (sr != 0)
  4085. set_fwstate(pmlmepriv, WIFI_UNDER_WPS);
  4086. else
  4087. _clr_fwstate_(pmlmepriv, WIFI_UNDER_WPS);
  4088. }
  4089. #endif
  4090. #ifdef CONFIG_P2P
  4091. if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
  4092. u32 len;
  4093. #ifdef CONFIG_IOCTL_CFG80211
  4094. if (pwdinfo->driver_interface == DRIVER_CFG80211) {
  4095. len = pmlmepriv->p2p_beacon_ie_len;
  4096. if (pmlmepriv->p2p_beacon_ie && len > 0)
  4097. _rtw_memcpy(pframe, pmlmepriv->p2p_beacon_ie, len);
  4098. } else
  4099. #endif /* CONFIG_IOCTL_CFG80211 */
  4100. {
  4101. len = build_beacon_p2p_ie(pwdinfo, pframe);
  4102. }
  4103. pframe += len;
  4104. pktlen += len;
  4105. #ifdef CONFIG_WFD
  4106. len = rtw_append_beacon_wfd_ie(padapter, pframe);
  4107. pframe += len;
  4108. pktlen += len;
  4109. #endif
  4110. }
  4111. #endif /* CONFIG_P2P */
  4112. goto _issue_bcn;
  4113. }
  4114. /* below for ad-hoc mode */
  4115. /* timestamp will be inserted by hardware */
  4116. pframe += 8;
  4117. pktlen += 8;
  4118. /* beacon interval: 2 bytes */
  4119. _rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2);
  4120. pframe += 2;
  4121. pktlen += 2;
  4122. /* capability info: 2 bytes */
  4123. _rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2);
  4124. pframe += 2;
  4125. pktlen += 2;
  4126. /* SSID */
  4127. pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pktlen);
  4128. /* supported rates... */
  4129. rate_len = rtw_get_rateset_len(cur_network->SupportedRates);
  4130. pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ? 8 : rate_len), cur_network->SupportedRates, &pktlen);
  4131. /* DS parameter set */
  4132. pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pktlen);
  4133. /* if( (pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) */
  4134. {
  4135. u8 erpinfo = 0;
  4136. u32 ATIMWindow;
  4137. /* IBSS Parameter Set... */
  4138. /* ATIMWindow = cur->Configuration.ATIMWindow; */
  4139. ATIMWindow = 0;
  4140. pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pktlen);
  4141. /* ERP IE */
  4142. pframe = rtw_set_ie(pframe, _ERPINFO_IE_, 1, &erpinfo, &pktlen);
  4143. }
  4144. /* EXTERNDED SUPPORTED RATE */
  4145. if (rate_len > 8)
  4146. pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pktlen);
  4147. /* todo:HT for adhoc */
  4148. _issue_bcn:
  4149. /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
  4150. /* pmlmepriv->update_bcn = _FALSE;
  4151. *
  4152. * _exit_critical_bh(&pmlmepriv->bcn_update_lock, &irqL);
  4153. * #endif */ /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
  4154. *pLength = pktlen;
  4155. #if 0
  4156. /* printf dbg msg */
  4157. dbgbufLen = pktlen;
  4158. RTW_INFO("======> DBG MSG FOR CONSTRAUCT P2P BEACON\n");
  4159. for (index = 0; index < dbgbufLen; index++)
  4160. printk("%x ", *(dbgbuf + index));
  4161. printk("\n");
  4162. RTW_INFO("<====== DBG MSG FOR CONSTRAUCT P2P BEACON\n");
  4163. #endif
  4164. }
  4165. static int get_reg_classes_full_count(struct p2p_channels channel_list)
  4166. {
  4167. int cnt = 0;
  4168. int i;
  4169. for (i = 0; i < channel_list.reg_classes; i++)
  4170. cnt += channel_list.reg_class[i].channels;
  4171. return cnt;
  4172. }
  4173. static void rtw_hal_construct_P2PProbeRsp(_adapter *padapter, u8 *pframe, u32 *pLength)
  4174. {
  4175. /* struct xmit_frame *pmgntframe; */
  4176. /* struct pkt_attrib *pattrib; */
  4177. /* unsigned char *pframe; */
  4178. struct rtw_ieee80211_hdr *pwlanhdr;
  4179. unsigned short *fctrl;
  4180. unsigned char *mac;
  4181. struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
  4182. struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
  4183. struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
  4184. struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
  4185. /* WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); */
  4186. u16 beacon_interval = 100;
  4187. u16 capInfo = 0;
  4188. struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
  4189. u8 wpsie[255] = { 0x00 };
  4190. u32 wpsielen = 0, p2pielen = 0;
  4191. u32 pktlen;
  4192. #ifdef CONFIG_WFD
  4193. u32 wfdielen = 0;
  4194. #endif
  4195. #ifdef CONFIG_INTEL_WIDI
  4196. u8 zero_array_check[L2SDTA_SERVICE_VE_LEN] = { 0x00 };
  4197. #endif /* CONFIG_INTEL_WIDI */
  4198. /* for debug */
  4199. u8 *dbgbuf = pframe;
  4200. u8 dbgbufLen = 0, index = 0;
  4201. RTW_INFO("%s\n", __FUNCTION__);
  4202. pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
  4203. mac = adapter_mac_addr(padapter);
  4204. fctrl = &(pwlanhdr->frame_ctl);
  4205. *(fctrl) = 0;
  4206. /* DA filled by FW */
  4207. _rtw_memset(pwlanhdr->addr1, 0, ETH_ALEN);
  4208. _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);
  4209. /* Use the device address for BSSID field. */
  4210. _rtw_memcpy(pwlanhdr->addr3, mac, ETH_ALEN);
  4211. SetSeqNum(pwlanhdr, 0);
  4212. set_frame_sub_type(fctrl, WIFI_PROBERSP);
  4213. pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
  4214. pframe += pktlen;
  4215. /* timestamp will be inserted by hardware */
  4216. pframe += 8;
  4217. pktlen += 8;
  4218. /* beacon interval: 2 bytes */
  4219. _rtw_memcpy(pframe, (unsigned char *) &beacon_interval, 2);
  4220. pframe += 2;
  4221. pktlen += 2;
  4222. /* capability info: 2 bytes */
  4223. /* ESS and IBSS bits must be 0 (defined in the 3.1.2.1.1 of WiFi Direct Spec) */
  4224. capInfo |= cap_ShortPremble;
  4225. capInfo |= cap_ShortSlot;
  4226. _rtw_memcpy(pframe, (unsigned char *) &capInfo, 2);
  4227. pframe += 2;
  4228. pktlen += 2;
  4229. /* SSID */
  4230. pframe = rtw_set_ie(pframe, _SSID_IE_, 7, pwdinfo->p2p_wildcard_ssid, &pktlen);
  4231. /* supported rates... */
  4232. /* Use the OFDM rate in the P2P probe response frame. ( 6(B), 9(B), 12, 18, 24, 36, 48, 54 ) */
  4233. pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, 8, pwdinfo->support_rate, &pktlen);
  4234. /* DS parameter set */
  4235. pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&pwdinfo->listen_channel, &pktlen);
  4236. #ifdef CONFIG_IOCTL_CFG80211
  4237. if (pwdinfo->driver_interface == DRIVER_CFG80211) {
  4238. if (pmlmepriv->wps_probe_resp_ie != NULL && pmlmepriv->p2p_probe_resp_ie != NULL) {
  4239. /* WPS IE */
  4240. _rtw_memcpy(pframe, pmlmepriv->wps_probe_resp_ie, pmlmepriv->wps_probe_resp_ie_len);
  4241. pktlen += pmlmepriv->wps_probe_resp_ie_len;
  4242. pframe += pmlmepriv->wps_probe_resp_ie_len;
  4243. /* P2P IE */
  4244. _rtw_memcpy(pframe, pmlmepriv->p2p_probe_resp_ie, pmlmepriv->p2p_probe_resp_ie_len);
  4245. pktlen += pmlmepriv->p2p_probe_resp_ie_len;
  4246. pframe += pmlmepriv->p2p_probe_resp_ie_len;
  4247. }
  4248. } else
  4249. #endif /* CONFIG_IOCTL_CFG80211 */
  4250. {
  4251. /* Todo: WPS IE */
  4252. /* Noted by Albert 20100907 */
  4253. /* According to the WPS specification, all the WPS attribute is presented by Big Endian. */
  4254. wpsielen = 0;
  4255. /* WPS OUI */
  4256. *(u32 *)(wpsie) = cpu_to_be32(WPSOUI);
  4257. wpsielen += 4;
  4258. /* WPS version */
  4259. /* Type: */
  4260. *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);
  4261. wpsielen += 2;
  4262. /* Length: */
  4263. *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
  4264. wpsielen += 2;
  4265. /* Value: */
  4266. wpsie[wpsielen++] = WPS_VERSION_1; /* Version 1.0 */
  4267. #ifdef CONFIG_INTEL_WIDI
  4268. /* Commented by Kurt */
  4269. /* Appended WiDi info. only if we did issued_probereq_widi(), and then we saved ven. ext. in pmlmepriv->sa_ext. */
  4270. if (_rtw_memcmp(pmlmepriv->sa_ext, zero_array_check, L2SDTA_SERVICE_VE_LEN) == _FALSE
  4271. || pmlmepriv->num_p2p_sdt != 0) {
  4272. /* Sec dev type */
  4273. *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_SEC_DEV_TYPE_LIST);
  4274. wpsielen += 2;
  4275. /* Length: */
  4276. *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0008);
  4277. wpsielen += 2;
  4278. /* Value: */
  4279. /* Category ID */
  4280. *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_CID_DISPLAYS);
  4281. wpsielen += 2;
  4282. /* OUI */
  4283. *(u32 *)(wpsie + wpsielen) = cpu_to_be32(INTEL_DEV_TYPE_OUI);
  4284. wpsielen += 4;
  4285. *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_SCID_WIDI_CONSUMER_SINK);
  4286. wpsielen += 2;
  4287. if (_rtw_memcmp(pmlmepriv->sa_ext, zero_array_check, L2SDTA_SERVICE_VE_LEN) == _FALSE) {
  4288. /* Vendor Extension */
  4289. _rtw_memcpy(wpsie + wpsielen, pmlmepriv->sa_ext, L2SDTA_SERVICE_VE_LEN);
  4290. wpsielen += L2SDTA_SERVICE_VE_LEN;
  4291. }
  4292. }
  4293. #endif /* CONFIG_INTEL_WIDI */
  4294. /* WiFi Simple Config State */
  4295. /* Type: */
  4296. *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_SIMPLE_CONF_STATE);
  4297. wpsielen += 2;
  4298. /* Length: */
  4299. *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
  4300. wpsielen += 2;
  4301. /* Value: */
  4302. wpsie[wpsielen++] = WPS_WSC_STATE_NOT_CONFIG; /* Not Configured. */
  4303. /* Response Type */
  4304. /* Type: */
  4305. *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_RESP_TYPE);
  4306. wpsielen += 2;
  4307. /* Length: */
  4308. *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
  4309. wpsielen += 2;
  4310. /* Value: */
  4311. wpsie[wpsielen++] = WPS_RESPONSE_TYPE_8021X;
  4312. /* UUID-E */
  4313. /* Type: */
  4314. *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_UUID_E);
  4315. wpsielen += 2;
  4316. /* Length: */
  4317. *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0010);
  4318. wpsielen += 2;
  4319. /* Value: */
  4320. if (pwdinfo->external_uuid == 0) {
  4321. _rtw_memset(wpsie + wpsielen, 0x0, 16);
  4322. _rtw_memcpy(wpsie + wpsielen, mac, ETH_ALEN);
  4323. } else
  4324. _rtw_memcpy(wpsie + wpsielen, pwdinfo->uuid, 0x10);
  4325. wpsielen += 0x10;
  4326. /* Manufacturer */
  4327. /* Type: */
  4328. *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_MANUFACTURER);
  4329. wpsielen += 2;
  4330. /* Length: */
  4331. *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0007);
  4332. wpsielen += 2;
  4333. /* Value: */
  4334. _rtw_memcpy(wpsie + wpsielen, "Realtek", 7);
  4335. wpsielen += 7;
  4336. /* Model Name */
  4337. /* Type: */
  4338. *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_MODEL_NAME);
  4339. wpsielen += 2;
  4340. /* Length: */
  4341. *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0006);
  4342. wpsielen += 2;
  4343. /* Value: */
  4344. _rtw_memcpy(wpsie + wpsielen, "8192CU", 6);
  4345. wpsielen += 6;
  4346. /* Model Number */
  4347. /* Type: */
  4348. *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_MODEL_NUMBER);
  4349. wpsielen += 2;
  4350. /* Length: */
  4351. *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
  4352. wpsielen += 2;
  4353. /* Value: */
  4354. wpsie[wpsielen++] = 0x31; /* character 1 */
  4355. /* Serial Number */
  4356. /* Type: */
  4357. *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_SERIAL_NUMBER);
  4358. wpsielen += 2;
  4359. /* Length: */
  4360. *(u16 *)(wpsie + wpsielen) = cpu_to_be16(ETH_ALEN);
  4361. wpsielen += 2;
  4362. /* Value: */
  4363. _rtw_memcpy(wpsie + wpsielen, "123456" , ETH_ALEN);
  4364. wpsielen += ETH_ALEN;
  4365. /* Primary Device Type */
  4366. /* Type: */
  4367. *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_PRIMARY_DEV_TYPE);
  4368. wpsielen += 2;
  4369. /* Length: */
  4370. *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0008);
  4371. wpsielen += 2;
  4372. /* Value: */
  4373. /* Category ID */
  4374. *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);
  4375. wpsielen += 2;
  4376. /* OUI */
  4377. *(u32 *)(wpsie + wpsielen) = cpu_to_be32(WPSOUI);
  4378. wpsielen += 4;
  4379. /* Sub Category ID */
  4380. *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);
  4381. wpsielen += 2;
  4382. /* Device Name */
  4383. /* Type: */
  4384. *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);
  4385. wpsielen += 2;
  4386. /* Length: */
  4387. *(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->device_name_len);
  4388. wpsielen += 2;
  4389. /* Value: */
  4390. _rtw_memcpy(wpsie + wpsielen, pwdinfo->device_name, pwdinfo->device_name_len);
  4391. wpsielen += pwdinfo->device_name_len;
  4392. /* Config Method */
  4393. /* Type: */
  4394. *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_CONF_METHOD);
  4395. wpsielen += 2;
  4396. /* Length: */
  4397. *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);
  4398. wpsielen += 2;
  4399. /* Value: */
  4400. *(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->supported_wps_cm);
  4401. wpsielen += 2;
  4402. pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pktlen);
  4403. p2pielen = build_probe_resp_p2p_ie(pwdinfo, pframe);
  4404. pframe += p2pielen;
  4405. pktlen += p2pielen;
  4406. }
  4407. #ifdef CONFIG_WFD
  4408. wfdielen = rtw_append_probe_resp_wfd_ie(padapter, pframe);
  4409. pframe += wfdielen;
  4410. pktlen += wfdielen;
  4411. #endif
  4412. *pLength = pktlen;
  4413. #if 0
  4414. /* printf dbg msg */
  4415. dbgbufLen = pktlen;
  4416. RTW_INFO("======> DBG MSG FOR CONSTRAUCT P2P Probe Rsp\n");
  4417. for (index = 0; index < dbgbufLen; index++)
  4418. printk("%x ", *(dbgbuf + index));
  4419. printk("\n");
  4420. RTW_INFO("<====== DBG MSG FOR CONSTRAUCT P2P Probe Rsp\n");
  4421. #endif
  4422. }
  4423. static void rtw_hal_construct_P2PNegoRsp(_adapter *padapter, u8 *pframe, u32 *pLength)
  4424. {
  4425. unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
  4426. u8 action = P2P_PUB_ACTION_ACTION;
  4427. u32 p2poui = cpu_to_be32(P2POUI);
  4428. u8 oui_subtype = P2P_GO_NEGO_RESP;
  4429. u8 wpsie[255] = { 0x00 }, p2pie[255] = { 0x00 };
  4430. u8 p2pielen = 0, i;
  4431. uint wpsielen = 0;
  4432. u16 wps_devicepassword_id = 0x0000;
  4433. uint wps_devicepassword_id_len = 0;
  4434. u8 channel_cnt_24g = 0, channel_cnt_5gl = 0, channel_cnt_5gh;
  4435. u16 len_channellist_attr = 0;
  4436. u32 pktlen;
  4437. u8 dialogToken = 0;
  4438. /* struct xmit_frame *pmgntframe; */
  4439. /* struct pkt_attrib *pattrib; */
  4440. /* unsigned char *pframe; */
  4441. struct rtw_ieee80211_hdr *pwlanhdr;
  4442. unsigned short *fctrl;
  4443. struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
  4444. struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
  4445. struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
  4446. struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
  4447. /* WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); */
  4448. #ifdef CONFIG_WFD
  4449. u32 wfdielen = 0;
  4450. #endif
  4451. /* for debug */
  4452. u8 *dbgbuf = pframe;
  4453. u8 dbgbufLen = 0, index = 0;
  4454. RTW_INFO("%s\n", __FUNCTION__);
  4455. pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
  4456. fctrl = &(pwlanhdr->frame_ctl);
  4457. *(fctrl) = 0;
  4458. /* RA, filled by FW */
  4459. _rtw_memset(pwlanhdr->addr1, 0, ETH_ALEN);
  4460. _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
  4461. _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN);
  4462. SetSeqNum(pwlanhdr, 0);
  4463. set_frame_sub_type(pframe, WIFI_ACTION);
  4464. pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
  4465. pframe += pktlen;
  4466. pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pktlen));
  4467. pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pktlen));
  4468. pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pktlen));
  4469. pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pktlen));
  4470. /* dialog token, filled by FW */
  4471. pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pktlen));
  4472. _rtw_memset(wpsie, 0x00, 255);
  4473. wpsielen = 0;
  4474. /* WPS Section */
  4475. wpsielen = 0;
  4476. /* WPS OUI */
  4477. *(u32 *)(wpsie) = cpu_to_be32(WPSOUI);
  4478. wpsielen += 4;
  4479. /* WPS version */
  4480. /* Type: */
  4481. *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);
  4482. wpsielen += 2;
  4483. /* Length: */
  4484. *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
  4485. wpsielen += 2;
  4486. /* Value: */
  4487. wpsie[wpsielen++] = WPS_VERSION_1; /* Version 1.0 */
  4488. /* Device Password ID */
  4489. /* Type: */
  4490. *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_PWID);
  4491. wpsielen += 2;
  4492. /* Length: */
  4493. *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);
  4494. wpsielen += 2;
  4495. /* Value: */
  4496. if (wps_devicepassword_id == WPS_DPID_USER_SPEC)
  4497. *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_REGISTRAR_SPEC);
  4498. else if (wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC)
  4499. *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_USER_SPEC);
  4500. else
  4501. *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_PBC);
  4502. wpsielen += 2;
  4503. pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pktlen);
  4504. /* P2P IE Section. */
  4505. /* P2P OUI */
  4506. p2pielen = 0;
  4507. p2pie[p2pielen++] = 0x50;
  4508. p2pie[p2pielen++] = 0x6F;
  4509. p2pie[p2pielen++] = 0x9A;
  4510. p2pie[p2pielen++] = 0x09; /* WFA P2P v1.0 */
  4511. /* Commented by Albert 20100908 */
  4512. /* According to the P2P Specification, the group negoitation response frame should contain 9 P2P attributes */
  4513. /* 1. Status */
  4514. /* 2. P2P Capability */
  4515. /* 3. Group Owner Intent */
  4516. /* 4. Configuration Timeout */
  4517. /* 5. Operating Channel */
  4518. /* 6. Intended P2P Interface Address */
  4519. /* 7. Channel List */
  4520. /* 8. Device Info */
  4521. /* 9. Group ID ( Only GO ) */
  4522. /* ToDo: */
  4523. /* P2P Status */
  4524. /* Type: */
  4525. p2pie[p2pielen++] = P2P_ATTR_STATUS;
  4526. /* Length: */
  4527. *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);
  4528. p2pielen += 2;
  4529. /* Value, filled by FW */
  4530. p2pie[p2pielen++] = 1;
  4531. /* P2P Capability */
  4532. /* Type: */
  4533. p2pie[p2pielen++] = P2P_ATTR_CAPABILITY;
  4534. /* Length: */
  4535. *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
  4536. p2pielen += 2;
  4537. /* Value: */
  4538. /* Device Capability Bitmap, 1 byte */
  4539. if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) {
  4540. /* Commented by Albert 2011/03/08 */
  4541. /* According to the P2P specification */
  4542. /* if the sending device will be client, the P2P Capability should be reserved of group negotation response frame */
  4543. p2pie[p2pielen++] = 0;
  4544. } else {
  4545. /* Be group owner or meet the error case */
  4546. p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT;
  4547. }
  4548. /* Group Capability Bitmap, 1 byte */
  4549. if (pwdinfo->persistent_supported)
  4550. p2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN | P2P_GRPCAP_PERSISTENT_GROUP;
  4551. else
  4552. p2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN;
  4553. /* Group Owner Intent */
  4554. /* Type: */
  4555. p2pie[p2pielen++] = P2P_ATTR_GO_INTENT;
  4556. /* Length: */
  4557. *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);
  4558. p2pielen += 2;
  4559. /* Value: */
  4560. if (pwdinfo->peer_intent & 0x01) {
  4561. /* Peer's tie breaker bit is 1, our tie breaker bit should be 0 */
  4562. p2pie[p2pielen++] = (pwdinfo->intent << 1);
  4563. } else {
  4564. /* Peer's tie breaker bit is 0, our tie breaker bit should be 1 */
  4565. p2pie[p2pielen++] = ((pwdinfo->intent << 1) | BIT(0));
  4566. }
  4567. /* Configuration Timeout */
  4568. /* Type: */
  4569. p2pie[p2pielen++] = P2P_ATTR_CONF_TIMEOUT;
  4570. /* Length: */
  4571. *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
  4572. p2pielen += 2;
  4573. /* Value: */
  4574. p2pie[p2pielen++] = 200; /* 2 seconds needed to be the P2P GO */
  4575. p2pie[p2pielen++] = 200; /* 2 seconds needed to be the P2P Client */
  4576. /* Operating Channel */
  4577. /* Type: */
  4578. p2pie[p2pielen++] = P2P_ATTR_OPERATING_CH;
  4579. /* Length: */
  4580. *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);
  4581. p2pielen += 2;
  4582. /* Value: */
  4583. /* Country String */
  4584. p2pie[p2pielen++] = 'X';
  4585. p2pie[p2pielen++] = 'X';
  4586. /* The third byte should be set to 0x04. */
  4587. /* Described in the "Operating Channel Attribute" section. */
  4588. p2pie[p2pielen++] = 0x04;
  4589. /* Operating Class */
  4590. if (pwdinfo->operating_channel <= 14) {
  4591. /* Operating Class */
  4592. p2pie[p2pielen++] = 0x51;
  4593. } else if ((pwdinfo->operating_channel >= 36) && (pwdinfo->operating_channel <= 48)) {
  4594. /* Operating Class */
  4595. p2pie[p2pielen++] = 0x73;
  4596. } else {
  4597. /* Operating Class */
  4598. p2pie[p2pielen++] = 0x7c;
  4599. }
  4600. /* Channel Number */
  4601. p2pie[p2pielen++] = pwdinfo->operating_channel; /* operating channel number */
  4602. /* Intended P2P Interface Address */
  4603. /* Type: */
  4604. p2pie[p2pielen++] = P2P_ATTR_INTENDED_IF_ADDR;
  4605. /* Length: */
  4606. *(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN);
  4607. p2pielen += 2;
  4608. /* Value: */
  4609. _rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);
  4610. p2pielen += ETH_ALEN;
  4611. /* Channel List */
  4612. /* Type: */
  4613. p2pie[p2pielen++] = P2P_ATTR_CH_LIST;
  4614. /* Country String(3) */
  4615. /* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */
  4616. /* + number of channels in all classes */
  4617. len_channellist_attr = 3
  4618. + (1 + 1) * (u16)pmlmeext->channel_list.reg_classes
  4619. + get_reg_classes_full_count(pmlmeext->channel_list);
  4620. #ifdef CONFIG_CONCURRENT_MODE
  4621. if (rtw_mi_buddy_check_fwstate(padapter, _FW_LINKED))
  4622. *(u16 *)(p2pie + p2pielen) = cpu_to_le16(5 + 1);
  4623. else
  4624. *(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
  4625. #else
  4626. *(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
  4627. #endif
  4628. p2pielen += 2;
  4629. /* Value: */
  4630. /* Country String */
  4631. p2pie[p2pielen++] = 'X';
  4632. p2pie[p2pielen++] = 'X';
  4633. /* The third byte should be set to 0x04. */
  4634. /* Described in the "Operating Channel Attribute" section. */
  4635. p2pie[p2pielen++] = 0x04;
  4636. /* Channel Entry List */
  4637. #ifdef CONFIG_CONCURRENT_MODE
  4638. if (rtw_mi_check_status(padapter, MI_LINKED)) {
  4639. u8 union_ch = rtw_mi_get_union_chan(padapter);
  4640. /* Operating Class */
  4641. if (union_ch > 14) {
  4642. if (union_ch >= 149)
  4643. p2pie[p2pielen++] = 0x7c;
  4644. else
  4645. p2pie[p2pielen++] = 0x73;
  4646. } else
  4647. p2pie[p2pielen++] = 0x51;
  4648. /* Number of Channels */
  4649. /* Just support 1 channel and this channel is AP's channel */
  4650. p2pie[p2pielen++] = 1;
  4651. /* Channel List */
  4652. p2pie[p2pielen++] = union_ch;
  4653. } else {
  4654. int i, j;
  4655. for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) {
  4656. /* Operating Class */
  4657. p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class;
  4658. /* Number of Channels */
  4659. p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels;
  4660. /* Channel List */
  4661. for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++)
  4662. p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i];
  4663. }
  4664. }
  4665. #else /* CONFIG_CONCURRENT_MODE */
  4666. {
  4667. int i, j;
  4668. for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) {
  4669. /* Operating Class */
  4670. p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class;
  4671. /* Number of Channels */
  4672. p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels;
  4673. /* Channel List */
  4674. for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++)
  4675. p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i];
  4676. }
  4677. }
  4678. #endif /* CONFIG_CONCURRENT_MODE */
  4679. /* Device Info */
  4680. /* Type: */
  4681. p2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO;
  4682. /* Length: */
  4683. /* 21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes) */
  4684. /* + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */
  4685. *(u16 *)(p2pie + p2pielen) = cpu_to_le16(21 + pwdinfo->device_name_len);
  4686. p2pielen += 2;
  4687. /* Value: */
  4688. /* P2P Device Address */
  4689. _rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);
  4690. p2pielen += ETH_ALEN;
  4691. /* Config Method */
  4692. /* This field should be big endian. Noted by P2P specification. */
  4693. *(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->supported_wps_cm);
  4694. p2pielen += 2;
  4695. /* Primary Device Type */
  4696. /* Category ID */
  4697. *(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);
  4698. p2pielen += 2;
  4699. /* OUI */
  4700. *(u32 *)(p2pie + p2pielen) = cpu_to_be32(WPSOUI);
  4701. p2pielen += 4;
  4702. /* Sub Category ID */
  4703. *(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);
  4704. p2pielen += 2;
  4705. /* Number of Secondary Device Types */
  4706. p2pie[p2pielen++] = 0x00; /* No Secondary Device Type List */
  4707. /* Device Name */
  4708. /* Type: */
  4709. *(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);
  4710. p2pielen += 2;
  4711. /* Length: */
  4712. *(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->device_name_len);
  4713. p2pielen += 2;
  4714. /* Value: */
  4715. _rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name , pwdinfo->device_name_len);
  4716. p2pielen += pwdinfo->device_name_len;
  4717. if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
  4718. /* Group ID Attribute */
  4719. /* Type: */
  4720. p2pie[p2pielen++] = P2P_ATTR_GROUP_ID;
  4721. /* Length: */
  4722. *(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN + pwdinfo->nego_ssidlen);
  4723. p2pielen += 2;
  4724. /* Value: */
  4725. /* p2P Device Address */
  4726. _rtw_memcpy(p2pie + p2pielen , pwdinfo->device_addr, ETH_ALEN);
  4727. p2pielen += ETH_ALEN;
  4728. /* SSID */
  4729. _rtw_memcpy(p2pie + p2pielen, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen);
  4730. p2pielen += pwdinfo->nego_ssidlen;
  4731. }
  4732. pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pktlen);
  4733. #ifdef CONFIG_WFD
  4734. wfdielen = build_nego_resp_wfd_ie(pwdinfo, pframe);
  4735. pframe += wfdielen;
  4736. pktlen += wfdielen;
  4737. #endif
  4738. *pLength = pktlen;
  4739. #if 0
  4740. /* printf dbg msg */
  4741. dbgbufLen = pktlen;
  4742. RTW_INFO("======> DBG MSG FOR CONSTRAUCT Nego Rsp\n");
  4743. for (index = 0; index < dbgbufLen; index++)
  4744. printk("%x ", *(dbgbuf + index));
  4745. printk("\n");
  4746. RTW_INFO("<====== DBG MSG FOR CONSTRAUCT Nego Rsp\n");
  4747. #endif
  4748. }
  4749. static void rtw_hal_construct_P2PInviteRsp(_adapter *padapter, u8 *pframe, u32 *pLength)
  4750. {
  4751. unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
  4752. u8 action = P2P_PUB_ACTION_ACTION;
  4753. u32 p2poui = cpu_to_be32(P2POUI);
  4754. u8 oui_subtype = P2P_INVIT_RESP;
  4755. u8 p2pie[255] = { 0x00 };
  4756. u8 p2pielen = 0, i;
  4757. u8 channel_cnt_24g = 0, channel_cnt_5gl = 0, channel_cnt_5gh = 0;
  4758. u16 len_channellist_attr = 0;
  4759. u32 pktlen;
  4760. u8 dialogToken = 0;
  4761. #ifdef CONFIG_WFD
  4762. u32 wfdielen = 0;
  4763. #endif
  4764. /* struct xmit_frame *pmgntframe; */
  4765. /* struct pkt_attrib *pattrib; */
  4766. /* unsigned char *pframe; */
  4767. struct rtw_ieee80211_hdr *pwlanhdr;
  4768. unsigned short *fctrl;
  4769. struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
  4770. struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
  4771. struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
  4772. struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
  4773. /* for debug */
  4774. u8 *dbgbuf = pframe;
  4775. u8 dbgbufLen = 0, index = 0;
  4776. RTW_INFO("%s\n", __FUNCTION__);
  4777. pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
  4778. fctrl = &(pwlanhdr->frame_ctl);
  4779. *(fctrl) = 0;
  4780. /* RA fill by FW */
  4781. _rtw_memset(pwlanhdr->addr1, 0, ETH_ALEN);
  4782. _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
  4783. /* BSSID fill by FW */
  4784. _rtw_memset(pwlanhdr->addr3, 0, ETH_ALEN);
  4785. SetSeqNum(pwlanhdr, 0);
  4786. set_frame_sub_type(pframe, WIFI_ACTION);
  4787. pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
  4788. pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
  4789. pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pktlen));
  4790. pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pktlen));
  4791. pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pktlen));
  4792. pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pktlen));
  4793. /* dialog token, filled by FW */
  4794. pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pktlen));
  4795. /* P2P IE Section. */
  4796. /* P2P OUI */
  4797. p2pielen = 0;
  4798. p2pie[p2pielen++] = 0x50;
  4799. p2pie[p2pielen++] = 0x6F;
  4800. p2pie[p2pielen++] = 0x9A;
  4801. p2pie[p2pielen++] = 0x09; /* WFA P2P v1.0 */
  4802. /* Commented by Albert 20101005 */
  4803. /* According to the P2P Specification, the P2P Invitation response frame should contain 5 P2P attributes */
  4804. /* 1. Status */
  4805. /* 2. Configuration Timeout */
  4806. /* 3. Operating Channel ( Only GO ) */
  4807. /* 4. P2P Group BSSID ( Only GO ) */
  4808. /* 5. Channel List */
  4809. /* P2P Status */
  4810. /* Type: */
  4811. p2pie[p2pielen++] = P2P_ATTR_STATUS;
  4812. /* Length: */
  4813. *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);
  4814. p2pielen += 2;
  4815. /* Value: filled by FW, defult value is FAIL INFO UNAVAILABLE */
  4816. p2pie[p2pielen++] = P2P_STATUS_FAIL_INFO_UNAVAILABLE;
  4817. /* Configuration Timeout */
  4818. /* Type: */
  4819. p2pie[p2pielen++] = P2P_ATTR_CONF_TIMEOUT;
  4820. /* Length: */
  4821. *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
  4822. p2pielen += 2;
  4823. /* Value: */
  4824. p2pie[p2pielen++] = 200; /* 2 seconds needed to be the P2P GO */
  4825. p2pie[p2pielen++] = 200; /* 2 seconds needed to be the P2P Client */
  4826. /* due to defult value is FAIL INFO UNAVAILABLE, so the following IE is not needed */
  4827. #if 0
  4828. if (status_code == P2P_STATUS_SUCCESS) {
  4829. if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
  4830. /* The P2P Invitation request frame asks this Wi-Fi device to be the P2P GO */
  4831. /* In this case, the P2P Invitation response frame should carry the two more P2P attributes. */
  4832. /* First one is operating channel attribute. */
  4833. /* Second one is P2P Group BSSID attribute. */
  4834. /* Operating Channel */
  4835. /* Type: */
  4836. p2pie[p2pielen++] = P2P_ATTR_OPERATING_CH;
  4837. /* Length: */
  4838. *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);
  4839. p2pielen += 2;
  4840. /* Value: */
  4841. /* Country String */
  4842. p2pie[p2pielen++] = 'X';
  4843. p2pie[p2pielen++] = 'X';
  4844. /* The third byte should be set to 0x04. */
  4845. /* Described in the "Operating Channel Attribute" section. */
  4846. p2pie[p2pielen++] = 0x04;
  4847. /* Operating Class */
  4848. p2pie[p2pielen++] = 0x51; /* Copy from SD7 */
  4849. /* Channel Number */
  4850. p2pie[p2pielen++] = pwdinfo->operating_channel; /* operating channel number */
  4851. /* P2P Group BSSID */
  4852. /* Type: */
  4853. p2pie[p2pielen++] = P2P_ATTR_GROUP_BSSID;
  4854. /* Length: */
  4855. *(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN);
  4856. p2pielen += 2;
  4857. /* Value: */
  4858. /* P2P Device Address for GO */
  4859. _rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);
  4860. p2pielen += ETH_ALEN;
  4861. }
  4862. /* Channel List */
  4863. /* Type: */
  4864. p2pie[p2pielen++] = P2P_ATTR_CH_LIST;
  4865. /* Length: */
  4866. /* Country String(3) */
  4867. /* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */
  4868. /* + number of channels in all classes */
  4869. len_channellist_attr = 3
  4870. + (1 + 1) * (u16)pmlmeext->channel_list.reg_classes
  4871. + get_reg_classes_full_count(pmlmeext->channel_list);
  4872. #ifdef CONFIG_CONCURRENT_MODE
  4873. if (rtw_mi_check_status(padapter, MI_LINKED))
  4874. *(u16 *)(p2pie + p2pielen) = cpu_to_le16(5 + 1);
  4875. else
  4876. *(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
  4877. #else
  4878. *(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
  4879. #endif
  4880. p2pielen += 2;
  4881. /* Value: */
  4882. /* Country String */
  4883. p2pie[p2pielen++] = 'X';
  4884. p2pie[p2pielen++] = 'X';
  4885. /* The third byte should be set to 0x04. */
  4886. /* Described in the "Operating Channel Attribute" section. */
  4887. p2pie[p2pielen++] = 0x04;
  4888. /* Channel Entry List */
  4889. #ifdef CONFIG_CONCURRENT_MODE
  4890. if (rtw_mi_check_status(padapter, MI_LINKED)) {
  4891. u8 union_ch = rtw_mi_get_union_chan(padapter);
  4892. /* Operating Class */
  4893. if (union_ch > 14) {
  4894. if (union_ch >= 149)
  4895. p2pie[p2pielen++] = 0x7c;
  4896. else
  4897. p2pie[p2pielen++] = 0x73;
  4898. } else
  4899. p2pie[p2pielen++] = 0x51;
  4900. /* Number of Channels */
  4901. /* Just support 1 channel and this channel is AP's channel */
  4902. p2pie[p2pielen++] = 1;
  4903. /* Channel List */
  4904. p2pie[p2pielen++] = union_ch;
  4905. } else {
  4906. int i, j;
  4907. for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) {
  4908. /* Operating Class */
  4909. p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class;
  4910. /* Number of Channels */
  4911. p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels;
  4912. /* Channel List */
  4913. for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++)
  4914. p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i];
  4915. }
  4916. }
  4917. #else /* CONFIG_CONCURRENT_MODE */
  4918. {
  4919. int i, j;
  4920. for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) {
  4921. /* Operating Class */
  4922. p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class;
  4923. /* Number of Channels */
  4924. p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels;
  4925. /* Channel List */
  4926. for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++)
  4927. p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i];
  4928. }
  4929. }
  4930. #endif /* CONFIG_CONCURRENT_MODE */
  4931. }
  4932. #endif
  4933. pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pktlen);
  4934. #ifdef CONFIG_WFD
  4935. wfdielen = build_invitation_resp_wfd_ie(pwdinfo, pframe);
  4936. pframe += wfdielen;
  4937. pktlen += wfdielen;
  4938. #endif
  4939. *pLength = pktlen;
  4940. #if 0
  4941. /* printf dbg msg */
  4942. dbgbufLen = pktlen;
  4943. RTW_INFO("======> DBG MSG FOR CONSTRAUCT Invite Rsp\n");
  4944. for (index = 0; index < dbgbufLen; index++)
  4945. printk("%x ", *(dbgbuf + index));
  4946. printk("\n");
  4947. RTW_INFO("<====== DBG MSG FOR CONSTRAUCT Invite Rsp\n");
  4948. #endif
  4949. }
  4950. static void rtw_hal_construct_P2PProvisionDisRsp(_adapter *padapter, u8 *pframe, u32 *pLength)
  4951. {
  4952. unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
  4953. u8 action = P2P_PUB_ACTION_ACTION;
  4954. u8 dialogToken = 0;
  4955. u32 p2poui = cpu_to_be32(P2POUI);
  4956. u8 oui_subtype = P2P_PROVISION_DISC_RESP;
  4957. u8 wpsie[100] = { 0x00 };
  4958. u8 wpsielen = 0;
  4959. u32 pktlen;
  4960. #ifdef CONFIG_WFD
  4961. u32 wfdielen = 0;
  4962. #endif
  4963. /* struct xmit_frame *pmgntframe; */
  4964. /* struct pkt_attrib *pattrib; */
  4965. /* unsigned char *pframe; */
  4966. struct rtw_ieee80211_hdr *pwlanhdr;
  4967. unsigned short *fctrl;
  4968. struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
  4969. struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
  4970. struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
  4971. struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
  4972. /* for debug */
  4973. u8 *dbgbuf = pframe;
  4974. u8 dbgbufLen = 0, index = 0;
  4975. RTW_INFO("%s\n", __FUNCTION__);
  4976. pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
  4977. fctrl = &(pwlanhdr->frame_ctl);
  4978. *(fctrl) = 0;
  4979. /* RA filled by FW */
  4980. _rtw_memset(pwlanhdr->addr1, 0, ETH_ALEN);
  4981. _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
  4982. _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN);
  4983. SetSeqNum(pwlanhdr, 0);
  4984. set_frame_sub_type(pframe, WIFI_ACTION);
  4985. pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
  4986. pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
  4987. pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pktlen));
  4988. pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pktlen));
  4989. pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pktlen));
  4990. pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pktlen));
  4991. /* dialog token, filled by FW */
  4992. pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pktlen));
  4993. wpsielen = 0;
  4994. /* WPS OUI */
  4995. /* *(u32*) ( wpsie ) = cpu_to_be32( WPSOUI ); */
  4996. RTW_PUT_BE32(wpsie, WPSOUI);
  4997. wpsielen += 4;
  4998. #if 0
  4999. /* WPS version */
  5000. /* Type: */
  5001. *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);
  5002. wpsielen += 2;
  5003. /* Length: */
  5004. *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
  5005. wpsielen += 2;
  5006. /* Value: */
  5007. wpsie[wpsielen++] = WPS_VERSION_1; /* Version 1.0 */
  5008. #endif
  5009. /* Config Method */
  5010. /* Type: */
  5011. /* *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_CONF_METHOD ); */
  5012. RTW_PUT_BE16(wpsie + wpsielen, WPS_ATTR_CONF_METHOD);
  5013. wpsielen += 2;
  5014. /* Length: */
  5015. /* *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 ); */
  5016. RTW_PUT_BE16(wpsie + wpsielen, 0x0002);
  5017. wpsielen += 2;
  5018. /* Value: filled by FW, default value is PBC */
  5019. /* *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( config_method ); */
  5020. RTW_PUT_BE16(wpsie + wpsielen, WPS_CM_PUSH_BUTTON);
  5021. wpsielen += 2;
  5022. pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pktlen);
  5023. #ifdef CONFIG_WFD
  5024. wfdielen = build_provdisc_resp_wfd_ie(pwdinfo, pframe);
  5025. pframe += wfdielen;
  5026. pktlen += wfdielen;
  5027. #endif
  5028. *pLength = pktlen;
  5029. /* printf dbg msg */
  5030. #if 0
  5031. dbgbufLen = pktlen;
  5032. RTW_INFO("======> DBG MSG FOR CONSTRAUCT ProvisionDis Rsp\n");
  5033. for (index = 0; index < dbgbufLen; index++)
  5034. printk("%x ", *(dbgbuf + index));
  5035. printk("\n");
  5036. RTW_INFO("<====== DBG MSG FOR CONSTRAUCT ProvisionDis Rsp\n");
  5037. #endif
  5038. }
  5039. u8 rtw_hal_set_FwP2PRsvdPage_cmd(_adapter *adapter, PRSVDPAGE_LOC rsvdpageloc)
  5040. {
  5041. u8 u1H2CP2PRsvdPageParm[H2C_P2PRSVDPAGE_LOC_LEN] = {0};
  5042. struct hal_ops *pHalFunc = &adapter->hal_func;
  5043. u8 ret = _FAIL;
  5044. RTW_INFO("P2PRsvdPageLoc: P2PBeacon=%d P2PProbeRsp=%d NegoRsp=%d InviteRsp=%d PDRsp=%d\n",
  5045. rsvdpageloc->LocP2PBeacon, rsvdpageloc->LocP2PProbeRsp,
  5046. rsvdpageloc->LocNegoRsp, rsvdpageloc->LocInviteRsp,
  5047. rsvdpageloc->LocPDRsp);
  5048. SET_H2CCMD_RSVDPAGE_LOC_P2P_BCN(u1H2CP2PRsvdPageParm, rsvdpageloc->LocProbeRsp);
  5049. SET_H2CCMD_RSVDPAGE_LOC_P2P_PROBE_RSP(u1H2CP2PRsvdPageParm, rsvdpageloc->LocPsPoll);
  5050. SET_H2CCMD_RSVDPAGE_LOC_P2P_NEGO_RSP(u1H2CP2PRsvdPageParm, rsvdpageloc->LocNullData);
  5051. SET_H2CCMD_RSVDPAGE_LOC_P2P_INVITE_RSP(u1H2CP2PRsvdPageParm, rsvdpageloc->LocQosNull);
  5052. SET_H2CCMD_RSVDPAGE_LOC_P2P_PD_RSP(u1H2CP2PRsvdPageParm, rsvdpageloc->LocBTQosNull);
  5053. /* FillH2CCmd8723B(padapter, H2C_8723B_P2P_OFFLOAD_RSVD_PAGE, H2C_P2PRSVDPAGE_LOC_LEN, u1H2CP2PRsvdPageParm); */
  5054. ret = rtw_hal_fill_h2c_cmd(adapter,
  5055. H2C_P2P_OFFLOAD_RSVD_PAGE,
  5056. H2C_P2PRSVDPAGE_LOC_LEN,
  5057. u1H2CP2PRsvdPageParm);
  5058. return ret;
  5059. }
  5060. u8 rtw_hal_set_p2p_wowlan_offload_cmd(_adapter *adapter)
  5061. {
  5062. u8 offload_cmd[H2C_P2P_OFFLOAD_LEN] = {0};
  5063. struct wifidirect_info *pwdinfo = &(adapter->wdinfo);
  5064. struct P2P_WoWlan_Offload_t *p2p_wowlan_offload = (struct P2P_WoWlan_Offload_t *)offload_cmd;
  5065. struct hal_ops *pHalFunc = &adapter->hal_func;
  5066. u8 ret = _FAIL;
  5067. _rtw_memset(p2p_wowlan_offload, 0 , sizeof(struct P2P_WoWlan_Offload_t));
  5068. RTW_INFO("%s\n", __func__);
  5069. switch (pwdinfo->role) {
  5070. case P2P_ROLE_DEVICE:
  5071. RTW_INFO("P2P_ROLE_DEVICE\n");
  5072. p2p_wowlan_offload->role = 0;
  5073. break;
  5074. case P2P_ROLE_CLIENT:
  5075. RTW_INFO("P2P_ROLE_CLIENT\n");
  5076. p2p_wowlan_offload->role = 1;
  5077. break;
  5078. case P2P_ROLE_GO:
  5079. RTW_INFO("P2P_ROLE_GO\n");
  5080. p2p_wowlan_offload->role = 2;
  5081. break;
  5082. default:
  5083. RTW_INFO("P2P_ROLE_DISABLE\n");
  5084. break;
  5085. }
  5086. p2p_wowlan_offload->Wps_Config[0] = pwdinfo->supported_wps_cm >> 8;
  5087. p2p_wowlan_offload->Wps_Config[1] = pwdinfo->supported_wps_cm;
  5088. offload_cmd = (u8 *)p2p_wowlan_offload;
  5089. RTW_INFO("p2p_wowlan_offload: %x:%x:%x\n", offload_cmd[0], offload_cmd[1], offload_cmd[2]);
  5090. ret = rtw_hal_fill_h2c_cmd(adapter,
  5091. H2C_P2P_OFFLOAD,
  5092. H2C_P2P_OFFLOAD_LEN,
  5093. offload_cmd);
  5094. return ret;
  5095. /* FillH2CCmd8723B(adapter, H2C_8723B_P2P_OFFLOAD, sizeof(struct P2P_WoWlan_Offload_t), (u8 *)p2p_wowlan_offload); */
  5096. }
  5097. #endif /* CONFIG_P2P_WOWLAN */
  5098. static void rtw_hal_construct_beacon(_adapter *padapter,
  5099. u8 *pframe, u32 *pLength)
  5100. {
  5101. struct rtw_ieee80211_hdr *pwlanhdr;
  5102. u16 *fctrl;
  5103. u32 rate_len, pktlen;
  5104. struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
  5105. struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
  5106. WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
  5107. u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
  5108. /* RTW_INFO("%s\n", __FUNCTION__); */
  5109. pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
  5110. fctrl = &(pwlanhdr->frame_ctl);
  5111. *(fctrl) = 0;
  5112. _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
  5113. _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
  5114. _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN);
  5115. SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/);
  5116. /* pmlmeext->mgnt_seq++; */
  5117. set_frame_sub_type(pframe, WIFI_BEACON);
  5118. pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
  5119. pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
  5120. /* timestamp will be inserted by hardware */
  5121. pframe += 8;
  5122. pktlen += 8;
  5123. /* beacon interval: 2 bytes */
  5124. _rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2);
  5125. pframe += 2;
  5126. pktlen += 2;
  5127. /* capability info: 2 bytes */
  5128. _rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2);
  5129. pframe += 2;
  5130. pktlen += 2;
  5131. if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {
  5132. /* RTW_INFO("ie len=%d\n", cur_network->IELength); */
  5133. pktlen += cur_network->IELength - sizeof(NDIS_802_11_FIXED_IEs);
  5134. _rtw_memcpy(pframe, cur_network->IEs + sizeof(NDIS_802_11_FIXED_IEs), pktlen);
  5135. goto _ConstructBeacon;
  5136. }
  5137. /* below for ad-hoc mode */
  5138. /* SSID */
  5139. pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pktlen);
  5140. /* supported rates... */
  5141. rate_len = rtw_get_rateset_len(cur_network->SupportedRates);
  5142. pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ? 8 : rate_len), cur_network->SupportedRates, &pktlen);
  5143. /* DS parameter set */
  5144. pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pktlen);
  5145. if ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) {
  5146. u32 ATIMWindow;
  5147. /* IBSS Parameter Set... */
  5148. /* ATIMWindow = cur->Configuration.ATIMWindow; */
  5149. ATIMWindow = 0;
  5150. pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pktlen);
  5151. }
  5152. /* todo: ERP IE */
  5153. /* EXTERNDED SUPPORTED RATE */
  5154. if (rate_len > 8)
  5155. pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pktlen);
  5156. /* todo:HT for adhoc */
  5157. _ConstructBeacon:
  5158. if ((pktlen + TXDESC_SIZE) > 512) {
  5159. RTW_INFO("beacon frame too large\n");
  5160. return;
  5161. }
  5162. *pLength = pktlen;
  5163. /* RTW_INFO("%s bcn_sz=%d\n", __FUNCTION__, pktlen); */
  5164. }
  5165. static void rtw_hal_construct_PSPoll(_adapter *padapter,
  5166. u8 *pframe, u32 *pLength)
  5167. {
  5168. struct rtw_ieee80211_hdr *pwlanhdr;
  5169. u16 *fctrl;
  5170. u32 pktlen;
  5171. struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
  5172. struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
  5173. /* RTW_INFO("%s\n", __FUNCTION__); */
  5174. pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
  5175. /* Frame control. */
  5176. fctrl = &(pwlanhdr->frame_ctl);
  5177. *(fctrl) = 0;
  5178. SetPwrMgt(fctrl);
  5179. set_frame_sub_type(pframe, WIFI_PSPOLL);
  5180. /* AID. */
  5181. set_duration(pframe, (pmlmeinfo->aid | 0xc000));
  5182. /* BSSID. */
  5183. _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
  5184. /* TA. */
  5185. _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
  5186. *pLength = 16;
  5187. }
  5188. void rtw_hal_construct_NullFunctionData(
  5189. PADAPTER padapter,
  5190. u8 *pframe,
  5191. u32 *pLength,
  5192. u8 *StaAddr,
  5193. u8 bQoS,
  5194. u8 AC,
  5195. u8 bEosp,
  5196. u8 bForcePowerSave)
  5197. {
  5198. struct rtw_ieee80211_hdr *pwlanhdr;
  5199. u16 *fctrl;
  5200. u32 pktlen;
  5201. struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
  5202. struct wlan_network *cur_network = &pmlmepriv->cur_network;
  5203. struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
  5204. struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
  5205. /* RTW_INFO("%s:%d\n", __FUNCTION__, bForcePowerSave); */
  5206. pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
  5207. fctrl = &pwlanhdr->frame_ctl;
  5208. *(fctrl) = 0;
  5209. if (bForcePowerSave)
  5210. SetPwrMgt(fctrl);
  5211. switch (cur_network->network.InfrastructureMode) {
  5212. case Ndis802_11Infrastructure:
  5213. SetToDs(fctrl);
  5214. _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
  5215. _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
  5216. _rtw_memcpy(pwlanhdr->addr3, StaAddr, ETH_ALEN);
  5217. break;
  5218. case Ndis802_11APMode:
  5219. SetFrDs(fctrl);
  5220. _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN);
  5221. _rtw_memcpy(pwlanhdr->addr2, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
  5222. _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN);
  5223. break;
  5224. case Ndis802_11IBSS:
  5225. default:
  5226. _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN);
  5227. _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
  5228. _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
  5229. break;
  5230. }
  5231. SetSeqNum(pwlanhdr, 0);
  5232. if (bQoS == _TRUE) {
  5233. struct rtw_ieee80211_hdr_3addr_qos *pwlanqoshdr;
  5234. set_frame_sub_type(pframe, WIFI_QOS_DATA_NULL);
  5235. pwlanqoshdr = (struct rtw_ieee80211_hdr_3addr_qos *)pframe;
  5236. SetPriority(&pwlanqoshdr->qc, AC);
  5237. SetEOSP(&pwlanqoshdr->qc, bEosp);
  5238. pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos);
  5239. } else {
  5240. set_frame_sub_type(pframe, WIFI_DATA_NULL);
  5241. pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
  5242. }
  5243. *pLength = pktlen;
  5244. }
  5245. void rtw_hal_construct_ProbeRsp(_adapter *padapter, u8 *pframe, u32 *pLength,
  5246. u8 *StaAddr, BOOLEAN bHideSSID)
  5247. {
  5248. struct rtw_ieee80211_hdr *pwlanhdr;
  5249. u16 *fctrl;
  5250. u8 *mac, *bssid;
  5251. u32 pktlen;
  5252. struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
  5253. struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
  5254. WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
  5255. /*RTW_INFO("%s\n", __FUNCTION__);*/
  5256. pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
  5257. mac = adapter_mac_addr(padapter);
  5258. bssid = cur_network->MacAddress;
  5259. fctrl = &(pwlanhdr->frame_ctl);
  5260. *(fctrl) = 0;
  5261. _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN);
  5262. _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);
  5263. _rtw_memcpy(pwlanhdr->addr3, bssid, ETH_ALEN);
  5264. SetSeqNum(pwlanhdr, 0);
  5265. set_frame_sub_type(fctrl, WIFI_PROBERSP);
  5266. pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
  5267. pframe += pktlen;
  5268. if (cur_network->IELength > MAX_IE_SZ)
  5269. return;
  5270. _rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength);
  5271. pframe += cur_network->IELength;
  5272. pktlen += cur_network->IELength;
  5273. *pLength = pktlen;
  5274. }
  5275. #ifdef CONFIG_WOWLAN
  5276. static void rtw_hal_append_tkip_mic(PADAPTER padapter,
  5277. u8 *pframe, u32 offset)
  5278. {
  5279. struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
  5280. struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
  5281. struct rtw_ieee80211_hdr *pwlanhdr;
  5282. struct mic_data micdata;
  5283. struct sta_info *psta = NULL;
  5284. int res = 0;
  5285. u8 *payload = (u8 *)(pframe + offset);
  5286. u8 mic[8];
  5287. u8 priority[4] = {0x0};
  5288. u8 null_key[16] = {0x0};
  5289. RTW_INFO("%s(): Add MIC, offset: %d\n", __func__, offset);
  5290. pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
  5291. psta = rtw_get_stainfo(&padapter->stapriv,
  5292. get_my_bssid(&(pmlmeinfo->network)));
  5293. if (psta != NULL) {
  5294. res = _rtw_memcmp(&psta->dot11tkiptxmickey.skey[0],
  5295. null_key, 16);
  5296. if (res == _TRUE)
  5297. RTW_INFO("%s(): STA dot11tkiptxmickey==0\n", __func__);
  5298. rtw_secmicsetkey(&micdata, &psta->dot11tkiptxmickey.skey[0]);
  5299. }
  5300. rtw_secmicappend(&micdata, pwlanhdr->addr3, 6); /* DA */
  5301. rtw_secmicappend(&micdata, pwlanhdr->addr2, 6); /* SA */
  5302. priority[0] = 0;
  5303. rtw_secmicappend(&micdata, &priority[0], 4);
  5304. rtw_secmicappend(&micdata, payload, 36); /* payload length = 8 + 28 */
  5305. rtw_secgetmic(&micdata, &(mic[0]));
  5306. payload += 36;
  5307. _rtw_memcpy(payload, &(mic[0]), 8);
  5308. }
  5309. /*
  5310. * Description:
  5311. * Construct the ARP response packet to support ARP offload.
  5312. * */
  5313. static void rtw_hal_construct_ARPRsp(
  5314. PADAPTER padapter,
  5315. u8 *pframe,
  5316. u32 *pLength,
  5317. u8 *pIPAddress
  5318. )
  5319. {
  5320. struct rtw_ieee80211_hdr *pwlanhdr;
  5321. u16 *fctrl;
  5322. u32 pktlen;
  5323. struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
  5324. struct wlan_network *cur_network = &pmlmepriv->cur_network;
  5325. struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
  5326. struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
  5327. struct security_priv *psecuritypriv = &padapter->securitypriv;
  5328. static u8 ARPLLCHeader[8] = {0xAA, 0xAA, 0x03, 0x00, 0x00, 0x00, 0x08, 0x06};
  5329. u8 *pARPRspPkt = pframe;
  5330. /* for TKIP Cal MIC */
  5331. u8 *payload = pframe;
  5332. u8 EncryptionHeadOverhead = 0, arp_offset = 0;
  5333. /* RTW_INFO("%s:%d\n", __FUNCTION__, bForcePowerSave); */
  5334. pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
  5335. fctrl = &pwlanhdr->frame_ctl;
  5336. *(fctrl) = 0;
  5337. /* ------------------------------------------------------------------------- */
  5338. /* MAC Header. */
  5339. /* ------------------------------------------------------------------------- */
  5340. SetFrameType(fctrl, WIFI_DATA);
  5341. /* set_frame_sub_type(fctrl, 0); */
  5342. SetToDs(fctrl);
  5343. _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
  5344. _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
  5345. _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
  5346. SetSeqNum(pwlanhdr, 0);
  5347. set_duration(pwlanhdr, 0);
  5348. /* SET_80211_HDR_FRAME_CONTROL(pARPRspPkt, 0); */
  5349. /* SET_80211_HDR_TYPE_AND_SUBTYPE(pARPRspPkt, Type_Data); */
  5350. /* SET_80211_HDR_TO_DS(pARPRspPkt, 1); */
  5351. /* SET_80211_HDR_ADDRESS1(pARPRspPkt, pMgntInfo->Bssid); */
  5352. /* SET_80211_HDR_ADDRESS2(pARPRspPkt, Adapter->CurrentAddress); */
  5353. /* SET_80211_HDR_ADDRESS3(pARPRspPkt, pMgntInfo->Bssid); */
  5354. /* SET_80211_HDR_DURATION(pARPRspPkt, 0); */
  5355. /* SET_80211_HDR_FRAGMENT_SEQUENCE(pARPRspPkt, 0); */
  5356. #ifdef CONFIG_WAPI_SUPPORT
  5357. *pLength = sMacHdrLng;
  5358. #else
  5359. *pLength = 24;
  5360. #endif
  5361. switch (psecuritypriv->dot11PrivacyAlgrthm) {
  5362. case _WEP40_:
  5363. case _WEP104_:
  5364. EncryptionHeadOverhead = 4;
  5365. break;
  5366. case _TKIP_:
  5367. EncryptionHeadOverhead = 8;
  5368. break;
  5369. case _AES_:
  5370. EncryptionHeadOverhead = 8;
  5371. break;
  5372. #ifdef CONFIG_WAPI_SUPPORT
  5373. case _SMS4_:
  5374. EncryptionHeadOverhead = 18;
  5375. break;
  5376. #endif
  5377. default:
  5378. EncryptionHeadOverhead = 0;
  5379. }
  5380. if (EncryptionHeadOverhead > 0) {
  5381. _rtw_memset(&(pframe[*pLength]), 0, EncryptionHeadOverhead);
  5382. *pLength += EncryptionHeadOverhead;
  5383. /* SET_80211_HDR_WEP(pARPRspPkt, 1); */ /* Suggested by CCW. */
  5384. SetPrivacy(fctrl);
  5385. }
  5386. /* ------------------------------------------------------------------------- */
  5387. /* Frame Body. */
  5388. /* ------------------------------------------------------------------------- */
  5389. arp_offset = *pLength;
  5390. pARPRspPkt = (u8 *)(pframe + arp_offset);
  5391. payload = pARPRspPkt; /* Get Payload pointer */
  5392. /* LLC header */
  5393. _rtw_memcpy(pARPRspPkt, ARPLLCHeader, 8);
  5394. *pLength += 8;
  5395. /* ARP element */
  5396. pARPRspPkt += 8;
  5397. SET_ARP_PKT_HW(pARPRspPkt, 0x0100);
  5398. SET_ARP_PKT_PROTOCOL(pARPRspPkt, 0x0008); /* IP protocol */
  5399. SET_ARP_PKT_HW_ADDR_LEN(pARPRspPkt, 6);
  5400. SET_ARP_PKT_PROTOCOL_ADDR_LEN(pARPRspPkt, 4);
  5401. SET_ARP_PKT_OPERATION(pARPRspPkt, 0x0200); /* ARP response */
  5402. SET_ARP_PKT_SENDER_MAC_ADDR(pARPRspPkt, adapter_mac_addr(padapter));
  5403. SET_ARP_PKT_SENDER_IP_ADDR(pARPRspPkt, pIPAddress);
  5404. #ifdef CONFIG_ARP_KEEP_ALIVE
  5405. if (!is_zero_mac_addr(pmlmepriv->gw_mac_addr)) {
  5406. SET_ARP_PKT_TARGET_MAC_ADDR(pARPRspPkt, pmlmepriv->gw_mac_addr);
  5407. SET_ARP_PKT_TARGET_IP_ADDR(pARPRspPkt, pmlmepriv->gw_ip);
  5408. } else
  5409. #endif
  5410. {
  5411. SET_ARP_PKT_TARGET_MAC_ADDR(pARPRspPkt,
  5412. get_my_bssid(&(pmlmeinfo->network)));
  5413. SET_ARP_PKT_TARGET_IP_ADDR(pARPRspPkt,
  5414. pIPAddress);
  5415. RTW_INFO("%s Target Mac Addr:" MAC_FMT "\n", __FUNCTION__,
  5416. MAC_ARG(get_my_bssid(&(pmlmeinfo->network))));
  5417. RTW_INFO("%s Target IP Addr" IP_FMT "\n", __FUNCTION__,
  5418. IP_ARG(pIPAddress));
  5419. }
  5420. *pLength += 28;
  5421. if (psecuritypriv->dot11PrivacyAlgrthm == _TKIP_) {
  5422. if (IS_HARDWARE_TYPE_8188E(padapter) ||
  5423. IS_HARDWARE_TYPE_8812(padapter)) {
  5424. rtw_hal_append_tkip_mic(padapter, pframe, arp_offset);
  5425. }
  5426. *pLength += 8;
  5427. }
  5428. }
  5429. #ifdef CONFIG_PNO_SUPPORT
  5430. static void rtw_hal_construct_ProbeReq(_adapter *padapter, u8 *pframe,
  5431. u32 *pLength, pno_ssid_t *ssid)
  5432. {
  5433. struct rtw_ieee80211_hdr *pwlanhdr;
  5434. u16 *fctrl;
  5435. u32 pktlen;
  5436. unsigned char *mac;
  5437. unsigned char bssrate[NumRates];
  5438. struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
  5439. struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
  5440. struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
  5441. struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
  5442. int bssrate_len = 0;
  5443. u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
  5444. pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
  5445. mac = adapter_mac_addr(padapter);
  5446. fctrl = &(pwlanhdr->frame_ctl);
  5447. *(fctrl) = 0;
  5448. _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
  5449. _rtw_memcpy(pwlanhdr->addr3, bc_addr, ETH_ALEN);
  5450. _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);
  5451. SetSeqNum(pwlanhdr, 0);
  5452. set_frame_sub_type(pframe, WIFI_PROBEREQ);
  5453. pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
  5454. pframe += pktlen;
  5455. if (ssid == NULL)
  5456. pframe = rtw_set_ie(pframe, _SSID_IE_, 0, NULL, &pktlen);
  5457. else {
  5458. /* RTW_INFO("%s len:%d\n", ssid->SSID, ssid->SSID_len); */
  5459. pframe = rtw_set_ie(pframe, _SSID_IE_, ssid->SSID_len, ssid->SSID, &pktlen);
  5460. }
  5461. get_rate_set(padapter, bssrate, &bssrate_len);
  5462. if (bssrate_len > 8) {
  5463. pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &pktlen);
  5464. pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &pktlen);
  5465. } else
  5466. pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &pktlen);
  5467. *pLength = pktlen;
  5468. }
  5469. static void rtw_hal_construct_PNO_info(_adapter *padapter,
  5470. u8 *pframe, u32 *pLength)
  5471. {
  5472. struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
  5473. int i;
  5474. u8 *pPnoInfoPkt = pframe;
  5475. pPnoInfoPkt = (u8 *)(pframe + *pLength);
  5476. _rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->ssid_num, 1);
  5477. pPnoInfoPkt += 1;
  5478. _rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->hidden_ssid_num, 1);
  5479. pPnoInfoPkt += 3;
  5480. _rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->fast_scan_period, 1);
  5481. pPnoInfoPkt += 4;
  5482. _rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->fast_scan_iterations, 4);
  5483. pPnoInfoPkt += 4;
  5484. _rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->slow_scan_period, 4);
  5485. pPnoInfoPkt += 4;
  5486. _rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->ssid_length, MAX_PNO_LIST_COUNT);
  5487. pPnoInfoPkt += MAX_PNO_LIST_COUNT;
  5488. _rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->ssid_cipher_info, MAX_PNO_LIST_COUNT);
  5489. pPnoInfoPkt += MAX_PNO_LIST_COUNT;
  5490. _rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->ssid_channel_info, MAX_PNO_LIST_COUNT);
  5491. pPnoInfoPkt += MAX_PNO_LIST_COUNT;
  5492. _rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->loc_probe_req, MAX_HIDDEN_AP);
  5493. pPnoInfoPkt += MAX_HIDDEN_AP;
  5494. /*
  5495. SSID is located at 128th Byte in NLO info Page
  5496. */
  5497. *pLength += 128;
  5498. pPnoInfoPkt = pframe + 128;
  5499. for (i = 0; i < pwrctl->pnlo_info->ssid_num ; i++) {
  5500. _rtw_memcpy(pPnoInfoPkt, &pwrctl->pno_ssid_list->node[i].SSID,
  5501. pwrctl->pnlo_info->ssid_length[i]);
  5502. *pLength += WLAN_SSID_MAXLEN;
  5503. pPnoInfoPkt += WLAN_SSID_MAXLEN;
  5504. }
  5505. }
  5506. static void rtw_hal_construct_ssid_list(_adapter *padapter,
  5507. u8 *pframe, u32 *pLength)
  5508. {
  5509. struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
  5510. u8 *pSSIDListPkt = pframe;
  5511. int i;
  5512. pSSIDListPkt = (u8 *)(pframe + *pLength);
  5513. for (i = 0; i < pwrctl->pnlo_info->ssid_num ; i++) {
  5514. _rtw_memcpy(pSSIDListPkt, &pwrctl->pno_ssid_list->node[i].SSID,
  5515. pwrctl->pnlo_info->ssid_length[i]);
  5516. *pLength += WLAN_SSID_MAXLEN;
  5517. pSSIDListPkt += WLAN_SSID_MAXLEN;
  5518. }
  5519. }
  5520. static void rtw_hal_construct_scan_info(_adapter *padapter,
  5521. u8 *pframe, u32 *pLength)
  5522. {
  5523. struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
  5524. u8 *pScanInfoPkt = pframe;
  5525. int i;
  5526. pScanInfoPkt = (u8 *)(pframe + *pLength);
  5527. _rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->channel_num, 1);
  5528. *pLength += 1;
  5529. pScanInfoPkt += 1;
  5530. _rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->orig_ch, 1);
  5531. *pLength += 1;
  5532. pScanInfoPkt += 1;
  5533. _rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->orig_bw, 1);
  5534. *pLength += 1;
  5535. pScanInfoPkt += 1;
  5536. _rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->orig_40_offset, 1);
  5537. *pLength += 1;
  5538. pScanInfoPkt += 1;
  5539. _rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->orig_80_offset, 1);
  5540. *pLength += 1;
  5541. pScanInfoPkt += 1;
  5542. _rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->periodScan, 1);
  5543. *pLength += 1;
  5544. pScanInfoPkt += 1;
  5545. _rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->period_scan_time, 1);
  5546. *pLength += 1;
  5547. pScanInfoPkt += 1;
  5548. _rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->enableRFE, 1);
  5549. *pLength += 1;
  5550. pScanInfoPkt += 1;
  5551. _rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->rfe_type, 8);
  5552. *pLength += 8;
  5553. pScanInfoPkt += 8;
  5554. for (i = 0 ; i < MAX_SCAN_LIST_COUNT ; i++) {
  5555. _rtw_memcpy(pScanInfoPkt,
  5556. &pwrctl->pscan_info->ssid_channel_info[i], 4);
  5557. *pLength += 4;
  5558. pScanInfoPkt += 4;
  5559. }
  5560. }
  5561. #endif /* CONFIG_PNO_SUPPORT */
  5562. #ifdef CONFIG_GTK_OL
  5563. static void rtw_hal_construct_GTKRsp(
  5564. PADAPTER padapter,
  5565. u8 *pframe,
  5566. u32 *pLength
  5567. )
  5568. {
  5569. struct rtw_ieee80211_hdr *pwlanhdr;
  5570. u16 *fctrl;
  5571. u32 pktlen;
  5572. struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
  5573. struct wlan_network *cur_network = &pmlmepriv->cur_network;
  5574. struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
  5575. struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
  5576. struct security_priv *psecuritypriv = &padapter->securitypriv;
  5577. static u8 LLCHeader[8] = {0xAA, 0xAA, 0x03, 0x00, 0x00, 0x00, 0x88, 0x8E};
  5578. static u8 GTKbody_a[11] = {0x01, 0x03, 0x00, 0x5F, 0x02, 0x03, 0x12, 0x00, 0x10, 0x42, 0x0B};
  5579. u8 *pGTKRspPkt = pframe;
  5580. u8 EncryptionHeadOverhead = 0;
  5581. /* RTW_INFO("%s:%d\n", __FUNCTION__, bForcePowerSave); */
  5582. pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
  5583. fctrl = &pwlanhdr->frame_ctl;
  5584. *(fctrl) = 0;
  5585. /* ------------------------------------------------------------------------- */
  5586. /* MAC Header. */
  5587. /* ------------------------------------------------------------------------- */
  5588. SetFrameType(fctrl, WIFI_DATA);
  5589. /* set_frame_sub_type(fctrl, 0); */
  5590. SetToDs(fctrl);
  5591. _rtw_memcpy(pwlanhdr->addr1,
  5592. get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
  5593. _rtw_memcpy(pwlanhdr->addr2,
  5594. adapter_mac_addr(padapter), ETH_ALEN);
  5595. _rtw_memcpy(pwlanhdr->addr3,
  5596. get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
  5597. SetSeqNum(pwlanhdr, 0);
  5598. set_duration(pwlanhdr, 0);
  5599. #ifdef CONFIG_WAPI_SUPPORT
  5600. *pLength = sMacHdrLng;
  5601. #else
  5602. *pLength = 24;
  5603. #endif /* CONFIG_WAPI_SUPPORT */
  5604. /* ------------------------------------------------------------------------- */
  5605. /* Security Header: leave space for it if necessary. */
  5606. /* ------------------------------------------------------------------------- */
  5607. switch (psecuritypriv->dot11PrivacyAlgrthm) {
  5608. case _WEP40_:
  5609. case _WEP104_:
  5610. EncryptionHeadOverhead = 4;
  5611. break;
  5612. case _TKIP_:
  5613. EncryptionHeadOverhead = 8;
  5614. break;
  5615. case _AES_:
  5616. EncryptionHeadOverhead = 8;
  5617. break;
  5618. #ifdef CONFIG_WAPI_SUPPORT
  5619. case _SMS4_:
  5620. EncryptionHeadOverhead = 18;
  5621. break;
  5622. #endif /* CONFIG_WAPI_SUPPORT */
  5623. default:
  5624. EncryptionHeadOverhead = 0;
  5625. }
  5626. if (EncryptionHeadOverhead > 0) {
  5627. _rtw_memset(&(pframe[*pLength]), 0, EncryptionHeadOverhead);
  5628. *pLength += EncryptionHeadOverhead;
  5629. /* SET_80211_HDR_WEP(pGTKRspPkt, 1); */ /* Suggested by CCW. */
  5630. /* GTK's privacy bit is done by FW */
  5631. /* SetPrivacy(fctrl); */
  5632. }
  5633. /* ------------------------------------------------------------------------- */
  5634. /* Frame Body. */
  5635. /* ------------------------------------------------------------------------- */
  5636. pGTKRspPkt = (u8 *)(pframe + *pLength);
  5637. /* LLC header */
  5638. _rtw_memcpy(pGTKRspPkt, LLCHeader, 8);
  5639. *pLength += 8;
  5640. /* GTK element */
  5641. pGTKRspPkt += 8;
  5642. /* GTK frame body after LLC, part 1 */
  5643. /* TKIP key_length = 32, AES key_length = 16 */
  5644. if (psecuritypriv->dot118021XGrpPrivacy == _TKIP_)
  5645. GTKbody_a[8] = 0x20;
  5646. /* GTK frame body after LLC, part 1 */
  5647. _rtw_memcpy(pGTKRspPkt, GTKbody_a, 11);
  5648. *pLength += 11;
  5649. pGTKRspPkt += 11;
  5650. /* GTK frame body after LLC, part 2 */
  5651. _rtw_memset(&(pframe[*pLength]), 0, 88);
  5652. *pLength += 88;
  5653. pGTKRspPkt += 88;
  5654. if (psecuritypriv->dot118021XGrpPrivacy == _TKIP_)
  5655. *pLength += 8;
  5656. }
  5657. #endif /* CONFIG_GTK_OL */
  5658. void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index,
  5659. u8 tx_desc, u32 page_size, u8 *page_num, u32 *total_pkt_len,
  5660. RSVDPAGE_LOC *rsvd_page_loc)
  5661. {
  5662. struct security_priv *psecuritypriv = &adapter->securitypriv;
  5663. struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
  5664. struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
  5665. struct mlme_ext_priv *pmlmeext;
  5666. struct mlme_ext_info *pmlmeinfo;
  5667. u32 ARPLength = 0, GTKLength = 0, PNOLength = 0, ScanInfoLength = 0;
  5668. u32 SSIDLegnth = 0, ProbeReqLength = 0;
  5669. u8 CurtPktPageNum = 0;
  5670. u8 currentip[4];
  5671. u8 cur_dot11txpn[8];
  5672. #ifdef CONFIG_GTK_OL
  5673. struct sta_priv *pstapriv = &adapter->stapriv;
  5674. struct sta_info *psta;
  5675. struct security_priv *psecpriv = &adapter->securitypriv;
  5676. u8 kek[RTW_KEK_LEN];
  5677. u8 kck[RTW_KCK_LEN];
  5678. #endif /* CONFIG_GTK_OL */
  5679. #ifdef CONFIG_PNO_SUPPORT
  5680. int pno_index;
  5681. u8 ssid_num;
  5682. #endif /* CONFIG_PNO_SUPPORT */
  5683. pmlmeext = &adapter->mlmeextpriv;
  5684. pmlmeinfo = &pmlmeext->mlmext_info;
  5685. if (pwrctl->wowlan_pno_enable == _FALSE) {
  5686. /* ARP RSP * 1 page */
  5687. rtw_get_current_ip_address(adapter, currentip);
  5688. rsvd_page_loc->LocArpRsp = *page_num;
  5689. RTW_INFO("LocArpRsp: %d\n", rsvd_page_loc->LocArpRsp);
  5690. rtw_hal_construct_ARPRsp(adapter, &pframe[index],
  5691. &ARPLength, currentip);
  5692. rtw_hal_fill_fake_txdesc(adapter,
  5693. &pframe[index - tx_desc],
  5694. ARPLength, _FALSE, _FALSE, _TRUE);
  5695. CurtPktPageNum = (u8)PageNum(tx_desc + ARPLength, page_size);
  5696. *page_num += CurtPktPageNum;
  5697. index += (CurtPktPageNum * page_size);
  5698. /* 3 SEC IV * 1 page */
  5699. rtw_get_sec_iv(adapter, cur_dot11txpn,
  5700. get_my_bssid(&pmlmeinfo->network));
  5701. rsvd_page_loc->LocRemoteCtrlInfo = *page_num;
  5702. RTW_INFO("LocRemoteCtrlInfo: %d\n", rsvd_page_loc->LocRemoteCtrlInfo);
  5703. _rtw_memcpy(pframe + index - tx_desc, cur_dot11txpn, _AES_IV_LEN_);
  5704. CurtPktPageNum = (u8)PageNum(_AES_IV_LEN_, page_size);
  5705. *page_num += CurtPktPageNum;
  5706. *total_pkt_len = index + _AES_IV_LEN_;
  5707. #ifdef CONFIG_GTK_OL
  5708. index += (CurtPktPageNum * page_size);
  5709. /* if the ap staion info. exists, get the kek, kck from staion info. */
  5710. psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
  5711. if (psta == NULL) {
  5712. _rtw_memset(kek, 0, RTW_KEK_LEN);
  5713. _rtw_memset(kck, 0, RTW_KCK_LEN);
  5714. RTW_INFO("%s, KEK, KCK download rsvd page all zero\n",
  5715. __func__);
  5716. } else {
  5717. _rtw_memcpy(kek, psta->kek, RTW_KEK_LEN);
  5718. _rtw_memcpy(kck, psta->kck, RTW_KCK_LEN);
  5719. }
  5720. /* 3 KEK, KCK */
  5721. rsvd_page_loc->LocGTKInfo = *page_num;
  5722. RTW_INFO("LocGTKInfo: %d\n", rsvd_page_loc->LocGTKInfo);
  5723. _rtw_memcpy(pframe + index - tx_desc, kck, RTW_KCK_LEN);
  5724. _rtw_memcpy(pframe + index - tx_desc + RTW_KCK_LEN,
  5725. kek, RTW_KEK_LEN);
  5726. GTKLength = tx_desc + RTW_KCK_LEN + RTW_KEK_LEN;
  5727. if (psta != NULL &&
  5728. psecuritypriv->dot118021XGrpPrivacy == _TKIP_) {
  5729. _rtw_memcpy(pframe + index - tx_desc + 56,
  5730. &psta->dot11tkiptxmickey, RTW_TKIP_MIC_LEN);
  5731. GTKLength += RTW_TKIP_MIC_LEN;
  5732. }
  5733. CurtPktPageNum = (u8)PageNum(GTKLength, page_size);
  5734. #if 0
  5735. {
  5736. int i;
  5737. printk("\ntoFW KCK: ");
  5738. for (i = 0; i < 16; i++)
  5739. printk(" %02x ", kck[i]);
  5740. printk("\ntoFW KEK: ");
  5741. for (i = 0; i < 16; i++)
  5742. printk(" %02x ", kek[i]);
  5743. printk("\n");
  5744. }
  5745. RTW_INFO("%s(): HW_VAR_SET_TX_CMD: KEK KCK %p %d\n",
  5746. __FUNCTION__, &pframe[index - tx_desc],
  5747. (tx_desc + RTW_KCK_LEN + RTW_KEK_LEN));
  5748. #endif
  5749. *page_num += CurtPktPageNum;
  5750. index += (CurtPktPageNum * page_size);
  5751. /* 3 GTK Response */
  5752. rsvd_page_loc->LocGTKRsp = *page_num;
  5753. RTW_INFO("LocGTKRsp: %d\n", rsvd_page_loc->LocGTKRsp);
  5754. rtw_hal_construct_GTKRsp(adapter, &pframe[index], &GTKLength);
  5755. rtw_hal_fill_fake_txdesc(adapter, &pframe[index - tx_desc],
  5756. GTKLength, _FALSE, _FALSE, _TRUE);
  5757. #if 0
  5758. {
  5759. int gj;
  5760. printk("123GTK pkt=>\n");
  5761. for (gj = 0; gj < GTKLength + tx_desc; gj++) {
  5762. printk(" %02x ", pframe[index - tx_desc + gj]);
  5763. if ((gj + 1) % 16 == 0)
  5764. printk("\n");
  5765. }
  5766. printk(" <=end\n");
  5767. }
  5768. RTW_INFO("%s(): HW_VAR_SET_TX_CMD: GTK RSP %p %d\n",
  5769. __FUNCTION__, &pframe[index - tx_desc],
  5770. (tx_desc + GTKLength));
  5771. #endif
  5772. CurtPktPageNum = (u8)PageNum(tx_desc + GTKLength, page_size);
  5773. *page_num += CurtPktPageNum;
  5774. index += (CurtPktPageNum * page_size);
  5775. /* below page is empty for GTK extension memory */
  5776. /* 3(11) GTK EXT MEM */
  5777. rsvd_page_loc->LocGTKEXTMEM = *page_num;
  5778. RTW_INFO("LocGTKEXTMEM: %d\n", rsvd_page_loc->LocGTKEXTMEM);
  5779. CurtPktPageNum = 2;
  5780. if (page_size >= 256)
  5781. CurtPktPageNum = 1;
  5782. *page_num += CurtPktPageNum;
  5783. /* extension memory for FW */
  5784. *total_pkt_len = index + (page_size * CurtPktPageNum);
  5785. #endif /* CONFIG_GTK_OL */
  5786. index += (CurtPktPageNum * page_size);
  5787. /*Reserve 1 page for AOAC report*/
  5788. rsvd_page_loc->LocAOACReport = *page_num;
  5789. RTW_INFO("LocAOACReport: %d\n", rsvd_page_loc->LocAOACReport);
  5790. *page_num += 1;
  5791. *total_pkt_len = index + (page_size * 1);
  5792. } else {
  5793. #ifdef CONFIG_PNO_SUPPORT
  5794. if (pwrctl->wowlan_in_resume == _FALSE &&
  5795. pwrctl->pno_inited == _TRUE) {
  5796. /* Broadcast Probe Request */
  5797. rsvd_page_loc->LocProbePacket = *page_num;
  5798. RTW_INFO("loc_probe_req: %d\n",
  5799. rsvd_page_loc->LocProbePacket);
  5800. rtw_hal_construct_ProbeReq(
  5801. adapter,
  5802. &pframe[index],
  5803. &ProbeReqLength,
  5804. NULL);
  5805. rtw_hal_fill_fake_txdesc(adapter,
  5806. &pframe[index - tx_desc],
  5807. ProbeReqLength, _FALSE, _FALSE, _FALSE);
  5808. CurtPktPageNum =
  5809. (u8)PageNum(tx_desc + ProbeReqLength, page_size);
  5810. *page_num += CurtPktPageNum;
  5811. index += (CurtPktPageNum * page_size);
  5812. /* Hidden SSID Probe Request */
  5813. ssid_num = pwrctl->pnlo_info->hidden_ssid_num;
  5814. for (pno_index = 0 ; pno_index < ssid_num ; pno_index++) {
  5815. pwrctl->pnlo_info->loc_probe_req[pno_index] =
  5816. *page_num;
  5817. rtw_hal_construct_ProbeReq(
  5818. adapter,
  5819. &pframe[index],
  5820. &ProbeReqLength,
  5821. &pwrctl->pno_ssid_list->node[pno_index]);
  5822. rtw_hal_fill_fake_txdesc(adapter,
  5823. &pframe[index - tx_desc],
  5824. ProbeReqLength, _FALSE, _FALSE, _FALSE);
  5825. CurtPktPageNum =
  5826. (u8)PageNum(tx_desc + ProbeReqLength, page_size);
  5827. *page_num += CurtPktPageNum;
  5828. index += (CurtPktPageNum * page_size);
  5829. }
  5830. /* PNO INFO Page */
  5831. rsvd_page_loc->LocPNOInfo = *page_num;
  5832. RTW_INFO("LocPNOInfo: %d\n", rsvd_page_loc->LocPNOInfo);
  5833. rtw_hal_construct_PNO_info(adapter,
  5834. &pframe[index - tx_desc],
  5835. &PNOLength);
  5836. CurtPktPageNum = (u8)PageNum(PNOLength, page_size);
  5837. *page_num += CurtPktPageNum;
  5838. index += (CurtPktPageNum * page_size);
  5839. /* Scan Info Page */
  5840. rsvd_page_loc->LocScanInfo = *page_num;
  5841. RTW_INFO("LocScanInfo: %d\n", rsvd_page_loc->LocScanInfo);
  5842. rtw_hal_construct_scan_info(adapter,
  5843. &pframe[index - tx_desc],
  5844. &ScanInfoLength);
  5845. CurtPktPageNum = (u8)PageNum(ScanInfoLength, page_size);
  5846. *page_num += CurtPktPageNum;
  5847. *total_pkt_len = index + ScanInfoLength;
  5848. index += (CurtPktPageNum * page_size);
  5849. }
  5850. #endif /* CONFIG_PNO_SUPPORT */
  5851. }
  5852. }
  5853. static void rtw_hal_gate_bb(_adapter *adapter, bool stop)
  5854. {
  5855. struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
  5856. u8 val8 = 0;
  5857. u16 val16 = 0;
  5858. if (stop) {
  5859. /* Pause TX*/
  5860. pwrpriv->wowlan_txpause_status = rtw_read8(adapter, REG_TXPAUSE);
  5861. rtw_write8(adapter, REG_TXPAUSE, 0xff);
  5862. val8 = rtw_read8(adapter, REG_SYS_FUNC_EN);
  5863. val8 &= ~BIT(0);
  5864. rtw_write8(adapter, REG_SYS_FUNC_EN, val8);
  5865. RTW_INFO("%s: BB gated: 0x%02x, store TXPAUSE: %02x\n",
  5866. __func__,
  5867. rtw_read8(adapter, REG_SYS_FUNC_EN),
  5868. pwrpriv->wowlan_txpause_status);
  5869. } else {
  5870. val8 = rtw_read8(adapter, REG_SYS_FUNC_EN);
  5871. val8 |= BIT(0);
  5872. rtw_write8(adapter, REG_SYS_FUNC_EN, val8);
  5873. RTW_INFO("%s: BB release: 0x%02x, recover TXPAUSE:%02x\n",
  5874. __func__, rtw_read8(adapter, REG_SYS_FUNC_EN),
  5875. pwrpriv->wowlan_txpause_status);
  5876. /* release TX*/
  5877. rtw_write8(adapter, REG_TXPAUSE, pwrpriv->wowlan_txpause_status);
  5878. }
  5879. }
  5880. static void rtw_hal_reset_mac_rx(_adapter *adapter)
  5881. {
  5882. u8 val8 = 0;
  5883. /* Set REG_CR bit1, bit3, bit7 to 0*/
  5884. val8 = rtw_read8(adapter, REG_CR);
  5885. val8 &= 0x75;
  5886. rtw_write8(adapter, REG_CR, val8);
  5887. val8 = rtw_read8(adapter, REG_CR);
  5888. /* Set REG_CR bit1, bit3, bit7 to 1*/
  5889. val8 |= 0x8a;
  5890. rtw_write8(adapter, REG_CR, val8);
  5891. RTW_INFO("0x%04x: %02x\n", REG_CR, rtw_read8(adapter, REG_CR));
  5892. }
  5893. static u8 rtw_hal_wow_pattern_generate(_adapter *adapter, u8 idx, struct rtl_wow_pattern *pwow_pattern)
  5894. {
  5895. struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
  5896. u8 *pattern;
  5897. u8 len = 0;
  5898. u8 *mask;
  5899. u8 mask_hw[MAX_WKFM_SIZE] = {0};
  5900. u8 content[MAX_WKFM_PATTERN_SIZE] = {0};
  5901. u8 broadcast_addr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
  5902. u8 multicast_addr1[2] = {0x33, 0x33};
  5903. u8 multicast_addr2[3] = {0x01, 0x00, 0x5e};
  5904. u8 mask_len = 0;
  5905. u8 mac_addr[ETH_ALEN] = {0};
  5906. u16 count = 0;
  5907. int i, j;
  5908. if (pwrctl->wowlan_pattern_idx > MAX_WKFM_CAM_NUM) {
  5909. RTW_INFO("%s pattern_idx is more than MAX_FMC_NUM: %d\n",
  5910. __func__, MAX_WKFM_CAM_NUM);
  5911. return _FAIL;
  5912. }
  5913. pattern = pwrctl->patterns[idx].content;
  5914. len = pwrctl->patterns[idx].len;
  5915. mask = pwrctl->patterns[idx].mask;
  5916. _rtw_memcpy(mac_addr, adapter_mac_addr(adapter), ETH_ALEN);
  5917. _rtw_memset(pwow_pattern, 0, sizeof(struct rtl_wow_pattern));
  5918. mask_len = DIV_ROUND_UP(len, 8);
  5919. /* 1. setup A1 table */
  5920. if (memcmp(pattern, broadcast_addr, ETH_ALEN) == 0)
  5921. pwow_pattern->type = PATTERN_BROADCAST;
  5922. else if (memcmp(pattern, multicast_addr1, 2) == 0)
  5923. pwow_pattern->type = PATTERN_MULTICAST;
  5924. else if (memcmp(pattern, multicast_addr2, 3) == 0)
  5925. pwow_pattern->type = PATTERN_MULTICAST;
  5926. else if (memcmp(pattern, mac_addr, ETH_ALEN) == 0)
  5927. pwow_pattern->type = PATTERN_UNICAST;
  5928. else
  5929. pwow_pattern->type = PATTERN_INVALID;
  5930. /* translate mask from os to mask for hw */
  5931. /******************************************************************************
  5932. * pattern from OS uses 'ethenet frame', like this:
  5933. | 6 | 6 | 2 | 20 | Variable | 4 |
  5934. |--------+--------+------+-----------+------------+-----|
  5935. | 802.3 Mac Header | IP Header | TCP Packet | FCS |
  5936. | DA | SA | Type |
  5937. * BUT, packet catched by our HW is in '802.11 frame', begin from LLC,
  5938. | 24 or 30 | 6 | 2 | 20 | Variable | 4 |
  5939. |-------------------+--------+------+-----------+------------+-----|
  5940. | 802.11 MAC Header | LLC | IP Header | TCP Packet | FCS |
  5941. | Others | Tpye |
  5942. * Therefore, we need translate mask_from_OS to mask_to_hw.
  5943. * We should left-shift mask by 6 bits, then set the new bit[0~5] = 0,
  5944. * because new mask[0~5] means 'SA', but our HW packet begins from LLC,
  5945. * bit[0~5] corresponds to first 6 Bytes in LLC, they just don't match.
  5946. ******************************************************************************/
  5947. /* Shift 6 bits */
  5948. for (i = 0; i < mask_len - 1; i++) {
  5949. mask_hw[i] = mask[i] >> 6;
  5950. mask_hw[i] |= (mask[i + 1] & 0x3F) << 2;
  5951. }
  5952. mask_hw[i] = (mask[i] >> 6) & 0x3F;
  5953. /* Set bit 0-5 to zero */
  5954. mask_hw[0] &= 0xC0;
  5955. for (i = 0; i < (MAX_WKFM_SIZE / 4); i++) {
  5956. pwow_pattern->mask[i] = mask_hw[i * 4];
  5957. pwow_pattern->mask[i] |= (mask_hw[i * 4 + 1] << 8);
  5958. pwow_pattern->mask[i] |= (mask_hw[i * 4 + 2] << 16);
  5959. pwow_pattern->mask[i] |= (mask_hw[i * 4 + 3] << 24);
  5960. }
  5961. /* To get the wake up pattern from the mask.
  5962. * We do not count first 12 bits which means
  5963. * DA[6] and SA[6] in the pattern to match HW design. */
  5964. count = 0;
  5965. for (i = 12; i < len; i++) {
  5966. if ((mask[i / 8] >> (i % 8)) & 0x01) {
  5967. content[count] = pattern[i];
  5968. count++;
  5969. }
  5970. }
  5971. pwow_pattern->crc = rtw_calc_crc(content, count);
  5972. if (pwow_pattern->crc != 0) {
  5973. if (pwow_pattern->type == PATTERN_INVALID)
  5974. pwow_pattern->type = PATTERN_VALID;
  5975. }
  5976. return _SUCCESS;
  5977. }
  5978. #ifndef CONFIG_WOW_PATTERN_HW_CAM
  5979. static void rtw_hal_set_wow_rxff_boundary(_adapter *adapter, bool wow_mode)
  5980. {
  5981. u8 val8 = 0;
  5982. u16 rxff_bndy = 0;
  5983. u32 rx_dma_buff_sz = 0;
  5984. val8 = rtw_read8(adapter, REG_FIFOPAGE + 3);
  5985. if (val8 != 0)
  5986. RTW_INFO("%s:[%04x]some PKTs in TXPKTBUF\n",
  5987. __func__, (REG_FIFOPAGE + 3));
  5988. rtw_hal_reset_mac_rx(adapter);
  5989. if (wow_mode) {
  5990. rtw_hal_get_def_var(adapter, HAL_DEF_RX_DMA_SZ_WOW,
  5991. (u8 *)&rx_dma_buff_sz);
  5992. rxff_bndy = rx_dma_buff_sz - 1;
  5993. rtw_write16(adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
  5994. RTW_INFO("%s: wow mode, 0x%04x: 0x%04x\n", __func__,
  5995. REG_TRXFF_BNDY + 2,
  5996. rtw_read16(adapter, (REG_TRXFF_BNDY + 2)));
  5997. } else {
  5998. rtw_hal_get_def_var(adapter, HAL_DEF_RX_DMA_SZ,
  5999. (u8 *)&rx_dma_buff_sz);
  6000. rxff_bndy = rx_dma_buff_sz - 1;
  6001. rtw_write16(adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
  6002. RTW_INFO("%s: normal mode, 0x%04x: 0x%04x\n", __func__,
  6003. REG_TRXFF_BNDY + 2,
  6004. rtw_read16(adapter, (REG_TRXFF_BNDY + 2)));
  6005. }
  6006. }
  6007. bool rtw_read_from_frame_mask(_adapter *adapter, u8 idx)
  6008. {
  6009. u32 data_l = 0, data_h = 0, rx_dma_buff_sz = 0, page_sz = 0;
  6010. u16 offset, rx_buf_ptr = 0;
  6011. u16 cam_start_offset = 0;
  6012. u16 ctrl_l = 0, ctrl_h = 0;
  6013. u8 count = 0, tmp = 0;
  6014. int i = 0;
  6015. bool res = _TRUE;
  6016. if (idx > MAX_WKFM_CAM_NUM) {
  6017. RTW_INFO("[Error]: %s, pattern index is out of range\n",
  6018. __func__);
  6019. return _FALSE;
  6020. }
  6021. rtw_hal_get_def_var(adapter, HAL_DEF_RX_DMA_SZ_WOW,
  6022. (u8 *)&rx_dma_buff_sz);
  6023. if (rx_dma_buff_sz == 0) {
  6024. RTW_INFO("[Error]: %s, rx_dma_buff_sz is 0!!\n", __func__);
  6025. return _FALSE;
  6026. }
  6027. rtw_hal_get_def_var(adapter, HAL_DEF_RX_PAGE_SIZE, (u8 *)&page_sz);
  6028. if (page_sz == 0) {
  6029. RTW_INFO("[Error]: %s, page_sz is 0!!\n", __func__);
  6030. return _FALSE;
  6031. }
  6032. offset = (u16)PageNum(rx_dma_buff_sz, page_sz);
  6033. cam_start_offset = offset * page_sz;
  6034. ctrl_l = 0x0;
  6035. ctrl_h = 0x0;
  6036. /* Enable RX packet buffer access */
  6037. rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT);
  6038. /* Read the WKFM CAM */
  6039. for (i = 0; i < (WKFMCAM_ADDR_NUM / 2); i++) {
  6040. /*
  6041. * Set Rx packet buffer offset.
  6042. * RxBufer pointer increases 1, we can access 8 bytes in Rx packet buffer.
  6043. * CAM start offset (unit: 1 byte) = Index*WKFMCAM_SIZE
  6044. * RxBufer pointer addr = (CAM start offset + per entry offset of a WKFMCAM)/8
  6045. * * Index: The index of the wake up frame mask
  6046. * * WKFMCAM_SIZE: the total size of one WKFM CAM
  6047. * * per entry offset of a WKFM CAM: Addr i * 4 bytes
  6048. */
  6049. rx_buf_ptr =
  6050. (cam_start_offset + idx * WKFMCAM_SIZE + i * 8) >> 3;
  6051. rtw_write16(adapter, REG_PKTBUF_DBG_CTRL, rx_buf_ptr);
  6052. rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_l);
  6053. data_l = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_L);
  6054. data_h = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H);
  6055. RTW_INFO("[%d]: %08x %08x\n", i, data_h, data_l);
  6056. count = 0;
  6057. do {
  6058. tmp = rtw_read8(adapter, REG_RXPKTBUF_CTRL);
  6059. rtw_udelay_os(2);
  6060. count++;
  6061. } while (!tmp && count < 100);
  6062. if (count >= 100) {
  6063. RTW_INFO("%s count:%d\n", __func__, count);
  6064. res = _FALSE;
  6065. }
  6066. }
  6067. /* Disable RX packet buffer access */
  6068. rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL,
  6069. DISABLE_TRXPKT_BUF_ACCESS);
  6070. return res;
  6071. }
  6072. bool rtw_write_to_frame_mask(_adapter *adapter, u8 idx,
  6073. struct rtl_wow_pattern *context)
  6074. {
  6075. u32 data = 0, rx_dma_buff_sz = 0, page_sz = 0;
  6076. u16 offset, rx_buf_ptr = 0;
  6077. u16 cam_start_offset = 0;
  6078. u16 ctrl_l = 0, ctrl_h = 0;
  6079. u8 count = 0, tmp = 0;
  6080. int res = 0, i = 0;
  6081. if (idx > MAX_WKFM_CAM_NUM) {
  6082. RTW_INFO("[Error]: %s, pattern index is out of range\n",
  6083. __func__);
  6084. return _FALSE;
  6085. }
  6086. rtw_hal_get_def_var(adapter, HAL_DEF_RX_DMA_SZ_WOW,
  6087. (u8 *)&rx_dma_buff_sz);
  6088. if (rx_dma_buff_sz == 0) {
  6089. RTW_INFO("[Error]: %s, rx_dma_buff_sz is 0!!\n", __func__);
  6090. return _FALSE;
  6091. }
  6092. rtw_hal_get_def_var(adapter, HAL_DEF_RX_PAGE_SIZE, (u8 *)&page_sz);
  6093. if (page_sz == 0) {
  6094. RTW_INFO("[Error]: %s, page_sz is 0!!\n", __func__);
  6095. return _FALSE;
  6096. }
  6097. offset = (u16)PageNum(rx_dma_buff_sz, page_sz);
  6098. cam_start_offset = offset * page_sz;
  6099. if (IS_HARDWARE_TYPE_8188E(adapter)) {
  6100. ctrl_l = 0x0001;
  6101. ctrl_h = 0x0001;
  6102. } else {
  6103. ctrl_l = 0x0f01;
  6104. ctrl_h = 0xf001;
  6105. }
  6106. /* Enable RX packet buffer access */
  6107. rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT);
  6108. /* Write the WKFM CAM */
  6109. for (i = 0; i < WKFMCAM_ADDR_NUM; i++) {
  6110. /*
  6111. * Set Rx packet buffer offset.
  6112. * RxBufer pointer increases 1, we can access 8 bytes in Rx packet buffer.
  6113. * CAM start offset (unit: 1 byte) = Index*WKFMCAM_SIZE
  6114. * RxBufer pointer addr = (CAM start offset + per entry offset of a WKFMCAM)/8
  6115. * * Index: The index of the wake up frame mask
  6116. * * WKFMCAM_SIZE: the total size of one WKFM CAM
  6117. * * per entry offset of a WKFM CAM: Addr i * 4 bytes
  6118. */
  6119. rx_buf_ptr =
  6120. (cam_start_offset + idx * WKFMCAM_SIZE + i * 4) >> 3;
  6121. rtw_write16(adapter, REG_PKTBUF_DBG_CTRL, rx_buf_ptr);
  6122. if (i == 0) {
  6123. if (context->type == PATTERN_VALID)
  6124. data = BIT(31);
  6125. else if (context->type == PATTERN_BROADCAST)
  6126. data = BIT(31) | BIT(26);
  6127. else if (context->type == PATTERN_MULTICAST)
  6128. data = BIT(31) | BIT(25);
  6129. else if (context->type == PATTERN_UNICAST)
  6130. data = BIT(31) | BIT(24);
  6131. if (context->crc != 0)
  6132. data |= context->crc;
  6133. rtw_write32(adapter, REG_PKTBUF_DBG_DATA_L, data);
  6134. rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_l);
  6135. } else if (i == 1) {
  6136. data = 0;
  6137. rtw_write32(adapter, REG_PKTBUF_DBG_DATA_H, data);
  6138. rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_h);
  6139. } else if (i == 2 || i == 4) {
  6140. data = context->mask[i - 2];
  6141. rtw_write32(adapter, REG_PKTBUF_DBG_DATA_L, data);
  6142. /* write to RX packet buffer*/
  6143. rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_l);
  6144. } else if (i == 3 || i == 5) {
  6145. data = context->mask[i - 2];
  6146. rtw_write32(adapter, REG_PKTBUF_DBG_DATA_H, data);
  6147. /* write to RX packet buffer*/
  6148. rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_h);
  6149. }
  6150. count = 0;
  6151. do {
  6152. tmp = rtw_read8(adapter, REG_RXPKTBUF_CTRL);
  6153. rtw_udelay_os(2);
  6154. count++;
  6155. } while (tmp && count < 100);
  6156. if (count >= 100)
  6157. res = _FALSE;
  6158. else
  6159. res = _TRUE;
  6160. }
  6161. /* Disable RX packet buffer access */
  6162. rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL,
  6163. DISABLE_TRXPKT_BUF_ACCESS);
  6164. return res;
  6165. }
  6166. void rtw_clean_pattern(_adapter *adapter)
  6167. {
  6168. struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
  6169. struct rtl_wow_pattern zero_pattern;
  6170. int i = 0;
  6171. _rtw_memset(&zero_pattern, 0, sizeof(struct rtl_wow_pattern));
  6172. zero_pattern.type = PATTERN_INVALID;
  6173. for (i = 0; i < MAX_WKFM_CAM_NUM; i++)
  6174. rtw_write_to_frame_mask(adapter, i, &zero_pattern);
  6175. rtw_write8(adapter, REG_WKFMCAM_NUM, 0);
  6176. }
  6177. static int rtw_hal_set_pattern(_adapter *adapter, u8 *pattern,
  6178. u8 len, u8 *mask, u8 idx)
  6179. {
  6180. struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
  6181. struct mlme_ext_priv *pmlmeext = NULL;
  6182. struct mlme_ext_info *pmlmeinfo = NULL;
  6183. struct rtl_wow_pattern wow_pattern;
  6184. u8 mask_hw[MAX_WKFM_SIZE] = {0};
  6185. u8 content[MAX_WKFM_PATTERN_SIZE] = {0};
  6186. u8 broadcast_addr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
  6187. u8 multicast_addr1[2] = {0x33, 0x33};
  6188. u8 multicast_addr2[3] = {0x01, 0x00, 0x5e};
  6189. u8 res = _FALSE, index = 0, mask_len = 0;
  6190. u8 mac_addr[ETH_ALEN] = {0};
  6191. u16 count = 0;
  6192. int i, j;
  6193. if (pwrctl->wowlan_pattern_idx > MAX_WKFM_CAM_NUM) {
  6194. RTW_INFO("%s pattern_idx is more than MAX_FMC_NUM: %d\n",
  6195. __func__, MAX_WKFM_CAM_NUM);
  6196. return _FALSE;
  6197. }
  6198. pmlmeext = &adapter->mlmeextpriv;
  6199. pmlmeinfo = &pmlmeext->mlmext_info;
  6200. _rtw_memcpy(mac_addr, adapter_mac_addr(adapter), ETH_ALEN);
  6201. _rtw_memset(&wow_pattern, 0, sizeof(struct rtl_wow_pattern));
  6202. mask_len = DIV_ROUND_UP(len, 8);
  6203. /* 1. setup A1 table */
  6204. if (memcmp(pattern, broadcast_addr, ETH_ALEN) == 0)
  6205. wow_pattern.type = PATTERN_BROADCAST;
  6206. else if (memcmp(pattern, multicast_addr1, 2) == 0)
  6207. wow_pattern.type = PATTERN_MULTICAST;
  6208. else if (memcmp(pattern, multicast_addr2, 3) == 0)
  6209. wow_pattern.type = PATTERN_MULTICAST;
  6210. else if (memcmp(pattern, mac_addr, ETH_ALEN) == 0)
  6211. wow_pattern.type = PATTERN_UNICAST;
  6212. else
  6213. wow_pattern.type = PATTERN_INVALID;
  6214. /* translate mask from os to mask for hw */
  6215. /******************************************************************************
  6216. * pattern from OS uses 'ethenet frame', like this:
  6217. | 6 | 6 | 2 | 20 | Variable | 4 |
  6218. |--------+--------+------+-----------+------------+-----|
  6219. | 802.3 Mac Header | IP Header | TCP Packet | FCS |
  6220. | DA | SA | Type |
  6221. * BUT, packet catched by our HW is in '802.11 frame', begin from LLC,
  6222. | 24 or 30 | 6 | 2 | 20 | Variable | 4 |
  6223. |-------------------+--------+------+-----------+------------+-----|
  6224. | 802.11 MAC Header | LLC | IP Header | TCP Packet | FCS |
  6225. | Others | Tpye |
  6226. * Therefore, we need translate mask_from_OS to mask_to_hw.
  6227. * We should left-shift mask by 6 bits, then set the new bit[0~5] = 0,
  6228. * because new mask[0~5] means 'SA', but our HW packet begins from LLC,
  6229. * bit[0~5] corresponds to first 6 Bytes in LLC, they just don't match.
  6230. ******************************************************************************/
  6231. /* Shift 6 bits */
  6232. for (i = 0; i < mask_len - 1; i++) {
  6233. mask_hw[i] = mask[i] >> 6;
  6234. mask_hw[i] |= (mask[i + 1] & 0x3F) << 2;
  6235. }
  6236. mask_hw[i] = (mask[i] >> 6) & 0x3F;
  6237. /* Set bit 0-5 to zero */
  6238. mask_hw[0] &= 0xC0;
  6239. for (i = 0; i < (MAX_WKFM_SIZE / 4); i++) {
  6240. wow_pattern.mask[i] = mask_hw[i * 4];
  6241. wow_pattern.mask[i] |= (mask_hw[i * 4 + 1] << 8);
  6242. wow_pattern.mask[i] |= (mask_hw[i * 4 + 2] << 16);
  6243. wow_pattern.mask[i] |= (mask_hw[i * 4 + 3] << 24);
  6244. }
  6245. /* To get the wake up pattern from the mask.
  6246. * We do not count first 12 bits which means
  6247. * DA[6] and SA[6] in the pattern to match HW design. */
  6248. count = 0;
  6249. for (i = 12; i < len; i++) {
  6250. if ((mask[i / 8] >> (i % 8)) & 0x01) {
  6251. content[count] = pattern[i];
  6252. count++;
  6253. }
  6254. }
  6255. wow_pattern.crc = rtw_calc_crc(content, count);
  6256. if (wow_pattern.crc != 0) {
  6257. if (wow_pattern.type == PATTERN_INVALID)
  6258. wow_pattern.type = PATTERN_VALID;
  6259. }
  6260. index = idx;
  6261. if (!pwrctl->bInSuspend)
  6262. index += 2;
  6263. /* write pattern */
  6264. res = rtw_write_to_frame_mask(adapter, index, &wow_pattern);
  6265. if (res == _FALSE)
  6266. RTW_INFO("%s: ERROR!! idx: %d write_to_frame_mask_cam fail\n",
  6267. __func__, idx);
  6268. return res;
  6269. }
  6270. void rtw_fill_pattern(_adapter *adapter)
  6271. {
  6272. int i = 0, total = 0, index;
  6273. struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
  6274. struct rtl_wow_pattern wow_pattern;
  6275. total = pwrpriv->wowlan_pattern_idx;
  6276. if (total > MAX_WKFM_CAM_NUM)
  6277. total = MAX_WKFM_CAM_NUM;
  6278. for (i = 0 ; i < total ; i++) {
  6279. if (_SUCCESS == rtw_hal_wow_pattern_generate(adapter, i, &wow_pattern)) {
  6280. index = i;
  6281. if (!pwrpriv->bInSuspend)
  6282. index += 2;
  6283. if (rtw_write_to_frame_mask(adapter, index, &wow_pattern) == _FALSE)
  6284. RTW_INFO("%s: ERROR!! idx: %d write_to_frame_mask_cam fail\n", __func__, i);
  6285. }
  6286. }
  6287. rtw_write8(adapter, REG_WKFMCAM_NUM, total);
  6288. }
  6289. #else /*CONFIG_WOW_PATTERN_HW_CAM*/
  6290. #define WOW_CAM_ACCESS_TIMEOUT_MS 200
  6291. #define WOW_VALID_BIT BIT31
  6292. #define WOW_BC_BIT BIT26
  6293. #define WOW_MC_BIT BIT25
  6294. #define WOW_UC_BIT BIT24
  6295. static u32 _rtw_wow_pattern_read_cam(_adapter *adapter, u8 addr)
  6296. {
  6297. struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
  6298. _mutex *mutex = &pwrpriv->wowlan_pattern_cam_mutex;
  6299. u32 rdata = 0;
  6300. u32 cnt = 0;
  6301. u32 start = 0;
  6302. u8 timeout = 0;
  6303. u8 rst = _FALSE;
  6304. _enter_critical_mutex(mutex, NULL);
  6305. rtw_write32(adapter, REG_WKFMCAM_CMD, BIT_WKFCAM_POLLING_V1 | BIT_WKFCAM_ADDR_V2(addr));
  6306. start = rtw_get_current_time();
  6307. while (1) {
  6308. if (rtw_is_surprise_removed(adapter))
  6309. break;
  6310. cnt++;
  6311. if (0 == (rtw_read32(adapter, REG_WKFMCAM_CMD) & BIT_WKFCAM_POLLING_V1)) {
  6312. rst = _SUCCESS;
  6313. break;
  6314. }
  6315. if (rtw_get_passing_time_ms(start) > WOW_CAM_ACCESS_TIMEOUT_MS) {
  6316. timeout = 1;
  6317. break;
  6318. }
  6319. }
  6320. rdata = rtw_read32(adapter, REG_WKFMCAM_RWD);
  6321. _exit_critical_mutex(mutex, NULL);
  6322. /*RTW_INFO("%s ==> addr:0x%02x , rdata:0x%08x\n", __func__, addr, rdata);*/
  6323. if (timeout)
  6324. RTW_ERR(FUNC_ADPT_FMT" failed due to polling timeout\n", FUNC_ADPT_ARG(adapter));
  6325. return rdata;
  6326. }
  6327. void rtw_wow_pattern_read_cam_ent(_adapter *adapter, u8 id, struct rtl_wow_pattern *context)
  6328. {
  6329. int i;
  6330. u32 rdata;
  6331. _rtw_memset(context, 0, sizeof(struct rtl_wow_pattern));
  6332. for (i = 4; i >= 0; i--) {
  6333. rdata = _rtw_wow_pattern_read_cam(adapter, (id << 3) | i);
  6334. switch (i) {
  6335. case 4:
  6336. if (rdata & WOW_BC_BIT)
  6337. context->type = PATTERN_BROADCAST;
  6338. else if (rdata & WOW_MC_BIT)
  6339. context->type = PATTERN_MULTICAST;
  6340. else if (rdata & WOW_UC_BIT)
  6341. context->type = PATTERN_UNICAST;
  6342. else
  6343. context->type = PATTERN_INVALID;
  6344. context->crc = rdata & 0xFFFF;
  6345. break;
  6346. default:
  6347. _rtw_memcpy(&context->mask[i], (u8 *)(&rdata), 4);
  6348. break;
  6349. }
  6350. }
  6351. }
  6352. static void _rtw_wow_pattern_write_cam(_adapter *adapter, u8 addr, u32 wdata)
  6353. {
  6354. struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
  6355. _mutex *mutex = &pwrpriv->wowlan_pattern_cam_mutex;
  6356. u32 cnt = 0;
  6357. u32 start = 0, end = 0;
  6358. u8 timeout = 0;
  6359. /*RTW_INFO("%s ==> addr:0x%02x , wdata:0x%08x\n", __func__, addr, wdata);*/
  6360. _enter_critical_mutex(mutex, NULL);
  6361. rtw_write32(adapter, REG_WKFMCAM_RWD, wdata);
  6362. rtw_write32(adapter, REG_WKFMCAM_CMD, BIT_WKFCAM_POLLING_V1 | BIT_WKFCAM_WE | BIT_WKFCAM_ADDR_V2(addr));
  6363. start = rtw_get_current_time();
  6364. while (1) {
  6365. if (rtw_is_surprise_removed(adapter))
  6366. break;
  6367. cnt++;
  6368. if (0 == (rtw_read32(adapter, REG_WKFMCAM_CMD) & BIT_WKFCAM_POLLING_V1))
  6369. break;
  6370. if (rtw_get_passing_time_ms(start) > WOW_CAM_ACCESS_TIMEOUT_MS) {
  6371. timeout = 1;
  6372. break;
  6373. }
  6374. }
  6375. end = rtw_get_current_time();
  6376. _exit_critical_mutex(mutex, NULL);
  6377. if (timeout) {
  6378. RTW_ERR(FUNC_ADPT_FMT" addr:0x%02x, wdata:0x%08x, to:%u, polling:%u, %d ms\n"
  6379. , FUNC_ADPT_ARG(adapter), addr, wdata, timeout, cnt, rtw_get_time_interval_ms(start, end));
  6380. }
  6381. }
  6382. void rtw_wow_pattern_write_cam_ent(_adapter *adapter, u8 id, struct rtl_wow_pattern *context)
  6383. {
  6384. int j;
  6385. u8 addr;
  6386. u32 wdata = 0;
  6387. for (j = 4; j >= 0; j--) {
  6388. switch (j) {
  6389. case 4:
  6390. wdata = context->crc;
  6391. if (PATTERN_BROADCAST == context->type)
  6392. wdata |= WOW_BC_BIT;
  6393. if (PATTERN_MULTICAST == context->type)
  6394. wdata |= WOW_MC_BIT;
  6395. if (PATTERN_UNICAST == context->type)
  6396. wdata |= WOW_UC_BIT;
  6397. if (PATTERN_INVALID != context->type)
  6398. wdata |= WOW_VALID_BIT;
  6399. break;
  6400. default:
  6401. wdata = context->mask[j];
  6402. break;
  6403. }
  6404. addr = (id << 3) + j;
  6405. _rtw_wow_pattern_write_cam(adapter, addr, wdata);
  6406. }
  6407. }
  6408. static u8 _rtw_wow_pattern_clean_cam(_adapter *adapter)
  6409. {
  6410. struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
  6411. _mutex *mutex = &pwrpriv->wowlan_pattern_cam_mutex;
  6412. u32 cnt = 0;
  6413. u32 start = 0;
  6414. u8 timeout = 0;
  6415. u8 rst = _FAIL;
  6416. _enter_critical_mutex(mutex, NULL);
  6417. rtw_write32(adapter, REG_WKFMCAM_CMD, BIT_WKFCAM_POLLING_V1 | BIT_WKFCAM_CLR_V1);
  6418. start = rtw_get_current_time();
  6419. while (1) {
  6420. if (rtw_is_surprise_removed(adapter))
  6421. break;
  6422. cnt++;
  6423. if (0 == (rtw_read32(adapter, REG_WKFMCAM_CMD) & BIT_WKFCAM_POLLING_V1)) {
  6424. rst = _SUCCESS;
  6425. break;
  6426. }
  6427. if (rtw_get_passing_time_ms(start) > WOW_CAM_ACCESS_TIMEOUT_MS) {
  6428. timeout = 1;
  6429. break;
  6430. }
  6431. }
  6432. _exit_critical_mutex(mutex, NULL);
  6433. if (timeout)
  6434. RTW_ERR(FUNC_ADPT_FMT" falied ,polling timeout\n", FUNC_ADPT_ARG(adapter));
  6435. return rst;
  6436. }
  6437. void rtw_clean_pattern(_adapter *adapter)
  6438. {
  6439. if (_FAIL == _rtw_wow_pattern_clean_cam(adapter))
  6440. RTW_ERR("rtw_clean_pattern failed\n");
  6441. }
  6442. void rtw_dump_wow_pattern(void *sel, struct rtl_wow_pattern *pwow_pattern, u8 idx)
  6443. {
  6444. int j;
  6445. RTW_PRINT_SEL(sel, "=======WOW CAM-ID[%d]=======\n", idx);
  6446. RTW_PRINT_SEL(sel, "[WOW CAM] type:%d\n", pwow_pattern->type);
  6447. RTW_PRINT_SEL(sel, "[WOW CAM] crc:0x%04x\n", pwow_pattern->crc);
  6448. for (j = 0; j < 4; j++)
  6449. RTW_PRINT_SEL(sel, "[WOW CAM] Mask:0x%08x\n", pwow_pattern->mask[j]);
  6450. }
  6451. void rtw_fill_pattern(_adapter *adapter)
  6452. {
  6453. int i = 0, total = 0;
  6454. struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
  6455. struct rtl_wow_pattern wow_pattern;
  6456. total = pwrpriv->wowlan_pattern_idx;
  6457. if (total > MAX_WKFM_CAM_NUM)
  6458. total = MAX_WKFM_CAM_NUM;
  6459. for (i = 0 ; i < total ; i++) {
  6460. if (_SUCCESS == rtw_hal_wow_pattern_generate(adapter, i, &wow_pattern)) {
  6461. rtw_dump_wow_pattern(RTW_DBGDUMP, &wow_pattern, i);
  6462. rtw_wow_pattern_write_cam_ent(adapter, i, &wow_pattern);
  6463. }
  6464. }
  6465. }
  6466. #endif
  6467. void rtw_wow_pattern_cam_dump(_adapter *adapter)
  6468. {
  6469. #ifndef CONFIG_WOW_PATTERN_HW_CAM
  6470. int i;
  6471. for (i = 0 ; i < MAX_WKFM_CAM_NUM; i++) {
  6472. RTW_INFO("=======[%d]=======\n", i);
  6473. rtw_read_from_frame_mask(adapter, i);
  6474. }
  6475. #else
  6476. struct rtl_wow_pattern context;
  6477. int i;
  6478. for (i = 0 ; i < MAX_WKFM_CAM_NUM; i++) {
  6479. rtw_wow_pattern_read_cam_ent(adapter, i, &context);
  6480. rtw_dump_wow_pattern(RTW_DBGDUMP, &context, i);
  6481. }
  6482. #endif
  6483. }
  6484. static void rtw_hal_dl_pattern(_adapter *adapter, u8 mode)
  6485. {
  6486. struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
  6487. switch (mode) {
  6488. case 0:
  6489. rtw_clean_pattern(adapter);
  6490. RTW_INFO("%s: total patterns: %d\n", __func__, pwrpriv->wowlan_pattern_idx);
  6491. break;
  6492. case 1:
  6493. rtw_set_default_pattern(adapter);
  6494. rtw_fill_pattern(adapter);
  6495. RTW_INFO("%s: pattern total: %d downloaded\n", __func__, pwrpriv->wowlan_pattern_idx);
  6496. break;
  6497. case 2:
  6498. rtw_clean_pattern(adapter);
  6499. rtw_wow_pattern_sw_reset(adapter);
  6500. RTW_INFO("%s: clean patterns\n", __func__);
  6501. break;
  6502. default:
  6503. RTW_INFO("%s: unknown mode\n", __func__);
  6504. break;
  6505. }
  6506. }
  6507. static void rtw_hal_wow_enable(_adapter *adapter)
  6508. {
  6509. struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
  6510. struct security_priv *psecuritypriv = &adapter->securitypriv;
  6511. struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
  6512. struct hal_ops *pHalFunc = &adapter->hal_func;
  6513. struct sta_info *psta = NULL;
  6514. PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
  6515. int res;
  6516. u16 media_status_rpt;
  6517. RTW_PRINT("%s, WOWLAN_ENABLE\n", __func__);
  6518. rtw_hal_gate_bb(adapter, _TRUE);
  6519. #ifdef CONFIG_GTK_OL
  6520. if (psecuritypriv->binstallKCK_KEK == _TRUE)
  6521. rtw_hal_fw_sync_cam_id(adapter);
  6522. #endif
  6523. if (IS_HARDWARE_TYPE_8723B(adapter))
  6524. rtw_hal_backup_rate(adapter);
  6525. /* RX DMA stop */
  6526. #if defined(CONFIG_RTL8188E)
  6527. if (IS_HARDWARE_TYPE_8188E(adapter))
  6528. rtw_hal_disable_tx_report(adapter);
  6529. #endif
  6530. res = rtw_hal_pause_rx_dma(adapter);
  6531. if (res == _FAIL)
  6532. RTW_PRINT("[WARNING] pause RX DMA fail\n");
  6533. #ifndef CONFIG_WOW_PATTERN_HW_CAM
  6534. /* Reconfig RX_FF Boundary */
  6535. rtw_hal_set_wow_rxff_boundary(adapter, _TRUE);
  6536. #endif
  6537. /* redownload wow pattern */
  6538. rtw_hal_dl_pattern(adapter, 1);
  6539. rtw_hal_fw_dl(adapter, _TRUE);
  6540. media_status_rpt = RT_MEDIA_CONNECT;
  6541. rtw_hal_set_hwreg(adapter, HW_VAR_H2C_FW_JOINBSSRPT,
  6542. (u8 *)&media_status_rpt);
  6543. if (!pwrctl->wowlan_pno_enable) {
  6544. psta = rtw_get_stainfo(&adapter->stapriv, get_bssid(pmlmepriv));
  6545. if (psta != NULL) {
  6546. #ifdef CONFIG_FW_MULTI_PORT_SUPPORT
  6547. rtw_hal_set_default_port_id_cmd(adapter, psta->mac_id);
  6548. #endif
  6549. rtw_sta_media_status_rpt(adapter, psta, 1);
  6550. }
  6551. }
  6552. #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
  6553. /* Enable CPWM2 only. */
  6554. res = rtw_hal_enable_cpwm2(adapter);
  6555. if (res == _FAIL)
  6556. RTW_PRINT("[WARNING] enable cpwm2 fail\n");
  6557. #endif
  6558. #ifdef CONFIG_GPIO_WAKEUP
  6559. rtw_hal_switch_gpio_wl_ctrl(adapter, WAKEUP_GPIO_IDX, _TRUE);
  6560. #endif
  6561. /* Set WOWLAN H2C command. */
  6562. RTW_PRINT("Set WOWLan cmd\n");
  6563. rtw_hal_set_fw_wow_related_cmd(adapter, 1);
  6564. res = rtw_hal_check_wow_ctrl(adapter, _TRUE);
  6565. if (res == _FALSE)
  6566. RTW_INFO("[Error]%s: set wowlan CMD fail!!\n", __func__);
  6567. pwrctl->wowlan_wake_reason =
  6568. rtw_read8(adapter, REG_WOWLAN_WAKE_REASON);
  6569. RTW_PRINT("wowlan_wake_reason: 0x%02x\n",
  6570. pwrctl->wowlan_wake_reason);
  6571. #ifdef CONFIG_GTK_OL_DBG
  6572. dump_sec_cam(RTW_DBGDUMP, adapter);
  6573. dump_sec_cam_cache(RTW_DBGDUMP, adapter);
  6574. #endif
  6575. #ifdef CONFIG_USB_HCI
  6576. /* free adapter's resource */
  6577. rtw_mi_intf_stop(adapter);
  6578. #endif
  6579. #if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
  6580. /* Invoid SE0 reset signal during suspending*/
  6581. rtw_write8(adapter, REG_RSV_CTRL, 0x20);
  6582. if (IS_8188F(pHalData->version_id) == FALSE)
  6583. rtw_write8(adapter, REG_RSV_CTRL, 0x60);
  6584. #endif
  6585. rtw_hal_gate_bb(adapter, _FALSE);
  6586. }
  6587. #define DBG_WAKEUP_REASON
  6588. #ifdef DBG_WAKEUP_REASON
  6589. void _dbg_wake_up_reason_string(_adapter *adapter, const char *srt_res)
  6590. {
  6591. RTW_INFO(ADPT_FMT "- wake up reason - %s\n", ADPT_ARG(adapter), srt_res);
  6592. }
  6593. void _dbg_rtw_wake_up_reason(_adapter *adapter, u8 reason)
  6594. {
  6595. if (RX_PAIRWISEKEY == reason)
  6596. _dbg_wake_up_reason_string(adapter, "Rx pairwise key");
  6597. else if (RX_GTK == reason)
  6598. _dbg_wake_up_reason_string(adapter, "Rx GTK");
  6599. else if (RX_FOURWAY_HANDSHAKE == reason)
  6600. _dbg_wake_up_reason_string(adapter, "Rx four way handshake");
  6601. else if (RX_DISASSOC == reason)
  6602. _dbg_wake_up_reason_string(adapter, "Rx disassoc");
  6603. else if (RX_DEAUTH == reason)
  6604. _dbg_wake_up_reason_string(adapter, "Rx deauth");
  6605. else if (RX_ARP_REQUEST == reason)
  6606. _dbg_wake_up_reason_string(adapter, "Rx ARP request");
  6607. else if (FW_DECISION_DISCONNECT == reason)
  6608. _dbg_wake_up_reason_string(adapter, "FW detect disconnect");
  6609. else if (RX_MAGIC_PKT == reason)
  6610. _dbg_wake_up_reason_string(adapter, "Rx magic packet");
  6611. else if (RX_UNICAST_PKT == reason)
  6612. _dbg_wake_up_reason_string(adapter, "Rx unicast packet");
  6613. else if (RX_PATTERN_PKT == reason)
  6614. _dbg_wake_up_reason_string(adapter, "Rx pattern packet");
  6615. else if (RTD3_SSID_MATCH == reason)
  6616. _dbg_wake_up_reason_string(adapter, "RTD3 SSID match");
  6617. else if (RX_REALWOW_V2_WAKEUP_PKT == reason)
  6618. _dbg_wake_up_reason_string(adapter, "Rx real WOW V2 wakeup packet");
  6619. else if (RX_REALWOW_V2_ACK_LOST == reason)
  6620. _dbg_wake_up_reason_string(adapter, "Rx real WOW V2 ack lost");
  6621. else if (ENABLE_FAIL_DMA_IDLE == reason)
  6622. _dbg_wake_up_reason_string(adapter, "enable fail DMA idle");
  6623. else if (ENABLE_FAIL_DMA_PAUSE == reason)
  6624. _dbg_wake_up_reason_string(adapter, "enable fail DMA pause");
  6625. else if (AP_OFFLOAD_WAKEUP == reason)
  6626. _dbg_wake_up_reason_string(adapter, "AP offload wakeup");
  6627. else if (CLK_32K_UNLOCK == reason)
  6628. _dbg_wake_up_reason_string(adapter, "clk 32k unlock");
  6629. else if (RTIME_FAIL_DMA_IDLE == reason)
  6630. _dbg_wake_up_reason_string(adapter, "RTIME fail DMA idle");
  6631. else if (CLK_32K_LOCK == reason)
  6632. _dbg_wake_up_reason_string(adapter, "clk 32k lock");
  6633. else
  6634. _dbg_wake_up_reason_string(adapter, "unknown reasoen");
  6635. }
  6636. #endif
  6637. static void rtw_hal_wow_disable(_adapter *adapter)
  6638. {
  6639. struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
  6640. struct security_priv *psecuritypriv = &adapter->securitypriv;
  6641. struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
  6642. struct hal_ops *pHalFunc = &adapter->hal_func;
  6643. struct sta_info *psta = NULL;
  6644. int res;
  6645. u16 media_status_rpt;
  6646. u8 val8;
  6647. RTW_PRINT("%s, WOWLAN_DISABLE\n", __func__);
  6648. if (!pwrctl->wowlan_pno_enable) {
  6649. psta = rtw_get_stainfo(&adapter->stapriv, get_bssid(pmlmepriv));
  6650. if (psta != NULL)
  6651. rtw_sta_media_status_rpt(adapter, psta, 0);
  6652. else
  6653. RTW_INFO("%s: psta is null\n", __func__);
  6654. }
  6655. if (0) {
  6656. RTW_INFO("0x630:0x%02x\n", rtw_read8(adapter, 0x630));
  6657. RTW_INFO("0x631:0x%02x\n", rtw_read8(adapter, 0x631));
  6658. RTW_INFO("0x634:0x%02x\n", rtw_read8(adapter, 0x634));
  6659. RTW_INFO("0x1c7:0x%02x\n", rtw_read8(adapter, 0x1c7));
  6660. }
  6661. pwrctl->wowlan_wake_reason = rtw_read8(adapter, REG_WOWLAN_WAKE_REASON);
  6662. RTW_PRINT("wakeup_reason: 0x%02x\n",
  6663. pwrctl->wowlan_wake_reason);
  6664. #ifdef DBG_WAKEUP_REASON
  6665. _dbg_rtw_wake_up_reason(adapter, pwrctl->wowlan_wake_reason);
  6666. #endif
  6667. rtw_hal_set_fw_wow_related_cmd(adapter, 0);
  6668. res = rtw_hal_check_wow_ctrl(adapter, _FALSE);
  6669. if (res == _FALSE) {
  6670. RTW_INFO("[Error]%s: disable WOW cmd fail\n!!", __func__);
  6671. rtw_hal_force_enable_rxdma(adapter);
  6672. }
  6673. rtw_hal_gate_bb(adapter, _TRUE);
  6674. res = rtw_hal_pause_rx_dma(adapter);
  6675. if (res == _FAIL)
  6676. RTW_PRINT("[WARNING] pause RX DMA fail\n");
  6677. /* clean HW pattern match */
  6678. rtw_hal_dl_pattern(adapter, 0);
  6679. #ifndef CONFIG_WOW_PATTERN_HW_CAM
  6680. /* config RXFF boundary to original */
  6681. rtw_hal_set_wow_rxff_boundary(adapter, _FALSE);
  6682. #endif
  6683. rtw_hal_release_rx_dma(adapter);
  6684. #if defined(CONFIG_RTL8188E)
  6685. if (IS_HARDWARE_TYPE_8188E(adapter))
  6686. rtw_hal_enable_tx_report(adapter);
  6687. #endif
  6688. #ifdef CONFIG_GTK_OL
  6689. if (((pwrctl->wowlan_wake_reason != RX_DISASSOC) ||
  6690. (pwrctl->wowlan_wake_reason != RX_DEAUTH) ||
  6691. (pwrctl->wowlan_wake_reason != FW_DECISION_DISCONNECT)) &&
  6692. psecuritypriv->binstallKCK_KEK == _TRUE) {
  6693. rtw_hal_get_aoac_rpt(adapter);
  6694. rtw_hal_update_sw_security_info(adapter);
  6695. }
  6696. #endif /*CONFIG_GTK_OL*/
  6697. rtw_hal_fw_dl(adapter, _FALSE);
  6698. #ifdef CONFIG_GPIO_WAKEUP
  6699. #ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE
  6700. if (pwrctl->is_high_active == 0)
  6701. rtw_hal_set_input_gpio(adapter, WAKEUP_GPIO_IDX);
  6702. else
  6703. rtw_hal_set_output_gpio(adapter, WAKEUP_GPIO_IDX, 0);
  6704. #else
  6705. val8 = (pwrctl->is_high_active == 0) ? 1 : 0;
  6706. RTW_PRINT("Set Wake GPIO to default(%d).\n", val8);
  6707. rtw_hal_set_output_gpio(adapter, WAKEUP_GPIO_IDX, val8);
  6708. rtw_hal_switch_gpio_wl_ctrl(adapter, WAKEUP_GPIO_IDX, _FALSE);
  6709. #endif
  6710. #endif
  6711. if ((pwrctl->wowlan_wake_reason != FW_DECISION_DISCONNECT) &&
  6712. (pwrctl->wowlan_wake_reason != RX_PAIRWISEKEY) &&
  6713. (pwrctl->wowlan_wake_reason != RX_DISASSOC) &&
  6714. (pwrctl->wowlan_wake_reason != RX_DEAUTH)) {
  6715. media_status_rpt = RT_MEDIA_CONNECT;
  6716. rtw_hal_set_hwreg(adapter, HW_VAR_H2C_FW_JOINBSSRPT,
  6717. (u8 *)&media_status_rpt);
  6718. if (psta != NULL) {
  6719. #ifdef CONFIG_FW_MULTI_PORT_SUPPORT
  6720. rtw_hal_set_default_port_id_cmd(adapter, psta->mac_id);
  6721. #endif
  6722. rtw_sta_media_status_rpt(adapter, psta, 1);
  6723. }
  6724. }
  6725. rtw_hal_gate_bb(adapter, _FALSE);
  6726. }
  6727. #endif /*CONFIG_WOWLAN*/
  6728. #ifdef CONFIG_P2P_WOWLAN
  6729. void rtw_hal_set_p2p_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index,
  6730. u8 tx_desc, u32 page_size, u8 *page_num, u32 *total_pkt_len,
  6731. RSVDPAGE_LOC *rsvd_page_loc)
  6732. {
  6733. u32 P2PNegoRspLength = 0, P2PInviteRspLength = 0;
  6734. u32 P2PPDRspLength = 0, P2PProbeRspLength = 0, P2PBCNLength = 0;
  6735. u8 CurtPktPageNum = 0;
  6736. /* P2P Beacon */
  6737. rsvd_page_loc->LocP2PBeacon = *page_num;
  6738. rtw_hal_construct_P2PBeacon(adapter, &pframe[index], &P2PBCNLength);
  6739. rtw_hal_fill_fake_txdesc(adapter, &pframe[index - tx_desc],
  6740. P2PBCNLength, _FALSE, _FALSE, _FALSE);
  6741. #if 0
  6742. RTW_INFO("%s(): HW_VAR_SET_TX_CMD: PROBE RSP %p %d\n",
  6743. __FUNCTION__, &pframe[index - tx_desc], (P2PBCNLength + tx_desc));
  6744. #endif
  6745. CurtPktPageNum = (u8)PageNum(tx_desc + P2PBCNLength, page_size);
  6746. *page_num += CurtPktPageNum;
  6747. index += (CurtPktPageNum * page_size);
  6748. /* P2P Probe rsp */
  6749. rsvd_page_loc->LocP2PProbeRsp = *page_num;
  6750. rtw_hal_construct_P2PProbeRsp(adapter, &pframe[index],
  6751. &P2PProbeRspLength);
  6752. rtw_hal_fill_fake_txdesc(adapter, &pframe[index - tx_desc],
  6753. P2PProbeRspLength, _FALSE, _FALSE, _FALSE);
  6754. /* RTW_INFO("%s(): HW_VAR_SET_TX_CMD: PROBE RSP %p %d\n", */
  6755. /* __FUNCTION__, &pframe[index-tx_desc], (P2PProbeRspLength+tx_desc)); */
  6756. CurtPktPageNum = (u8)PageNum(tx_desc + P2PProbeRspLength, page_size);
  6757. *page_num += CurtPktPageNum;
  6758. index += (CurtPktPageNum * page_size);
  6759. /* P2P nego rsp */
  6760. rsvd_page_loc->LocNegoRsp = *page_num;
  6761. rtw_hal_construct_P2PNegoRsp(adapter, &pframe[index],
  6762. &P2PNegoRspLength);
  6763. rtw_hal_fill_fake_txdesc(adapter, &pframe[index - tx_desc],
  6764. P2PNegoRspLength, _FALSE, _FALSE, _FALSE);
  6765. /* RTW_INFO("%s(): HW_VAR_SET_TX_CMD: QOS NULL DATA %p %d\n", */
  6766. /* __FUNCTION__, &pframe[index-tx_desc], (NegoRspLength+tx_desc)); */
  6767. CurtPktPageNum = (u8)PageNum(tx_desc + P2PNegoRspLength, page_size);
  6768. *page_num += CurtPktPageNum;
  6769. index += (CurtPktPageNum * page_size);
  6770. /* P2P invite rsp */
  6771. rsvd_page_loc->LocInviteRsp = *page_num;
  6772. rtw_hal_construct_P2PInviteRsp(adapter, &pframe[index],
  6773. &P2PInviteRspLength);
  6774. rtw_hal_fill_fake_txdesc(adapter, &pframe[index - tx_desc],
  6775. P2PInviteRspLength, _FALSE, _FALSE, _FALSE);
  6776. /* RTW_INFO("%s(): HW_VAR_SET_TX_CMD: QOS NULL DATA %p %d\n", */
  6777. /* __FUNCTION__, &pframe[index-tx_desc], (InviteRspLength+tx_desc)); */
  6778. CurtPktPageNum = (u8)PageNum(tx_desc + P2PInviteRspLength, page_size);
  6779. *page_num += CurtPktPageNum;
  6780. index += (CurtPktPageNum * page_size);
  6781. /* P2P provision discovery rsp */
  6782. rsvd_page_loc->LocPDRsp = *page_num;
  6783. rtw_hal_construct_P2PProvisionDisRsp(adapter,
  6784. &pframe[index], &P2PPDRspLength);
  6785. rtw_hal_fill_fake_txdesc(adapter, &pframe[index - tx_desc],
  6786. P2PPDRspLength, _FALSE, _FALSE, _FALSE);
  6787. /* RTW_INFO("%s(): HW_VAR_SET_TX_CMD: QOS NULL DATA %p %d\n", */
  6788. /* __FUNCTION__, &pframe[index-tx_desc], (PDRspLength+tx_desc)); */
  6789. CurtPktPageNum = (u8)PageNum(tx_desc + P2PPDRspLength, page_size);
  6790. *page_num += CurtPktPageNum;
  6791. *total_pkt_len = index + P2PPDRspLength;
  6792. index += (CurtPktPageNum * page_size);
  6793. }
  6794. #endif /* CONFIG_P2P_WOWLAN */
  6795. #ifdef CONFIG_LPS_PG
  6796. #include "hal_halmac.h"
  6797. #define DBG_LPSPG_SEC_DUMP
  6798. #define LPS_PG_INFO_RSVD_LEN 16
  6799. #define LPS_PG_INFO_RSVD_PAGE_NUM 1
  6800. #define DBG_LPSPG_INFO_DUMP
  6801. static void rtw_hal_set_lps_pg_info_rsvd_page(_adapter *adapter)
  6802. {
  6803. struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
  6804. struct sta_info *psta = rtw_get_stainfo(&adapter->stapriv, get_bssid(&adapter->mlmepriv));
  6805. struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
  6806. PHAL_DATA_TYPE phal_data = GET_HAL_DATA(adapter);
  6807. u8 lps_pg_info[LPS_PG_INFO_RSVD_LEN] = {0};
  6808. #ifdef CONFIG_MBSSID_CAM
  6809. u8 cam_id = INVALID_CAM_ID;
  6810. #endif
  6811. u8 *psec_cam_id = lps_pg_info + 8;
  6812. u8 sec_cam_num = 0;
  6813. if (!psta) {
  6814. RTW_ERR("%s [ERROR] sta is NULL\n", __func__);
  6815. rtw_warn_on(1);
  6816. return;
  6817. }
  6818. /*Byte 0 - used macid*/
  6819. LPSPG_RSVD_PAGE_SET_MACID(lps_pg_info, psta->mac_id);
  6820. RTW_INFO("[LPSPG-INFO] mac_id:%d\n", psta->mac_id);
  6821. #ifdef CONFIG_MBSSID_CAM
  6822. /*Byte 1 - used BSSID CAM entry*/
  6823. cam_id = rtw_mbid_cam_search_by_ifaceid(adapter, adapter->iface_id);
  6824. if (cam_id != INVALID_CAM_ID)
  6825. LPSPG_RSVD_PAGE_SET_MBSSCAMID(lps_pg_info, cam_id);
  6826. RTW_INFO("[LPSPG-INFO] mbss_cam_id:%d\n", cam_id);
  6827. #endif
  6828. #ifdef CONFIG_WOWLAN /*&& pattern match cam used*/
  6829. /*Btye 2 - Max used Pattern Match CAM entry*/
  6830. if (pwrpriv->wowlan_mode == _TRUE &&
  6831. check_fwstate(&adapter->mlmepriv, _FW_LINKED) == _TRUE) {
  6832. LPSPG_RSVD_PAGE_SET_PMC_NUM(lps_pg_info, pwrpriv->wowlan_pattern_idx);
  6833. RTW_INFO("[LPSPG-INFO] Max Pattern Match CAM entry :%d\n", pwrpriv->wowlan_pattern_idx);
  6834. }
  6835. #endif
  6836. #ifdef CONFIG_BEAMFORMING /*&& MU BF*/
  6837. /*Btye 3 - Max MU rate table Group ID*/
  6838. LPSPG_RSVD_PAGE_SET_MU_RAID_GID(lps_pg_info, _value);
  6839. RTW_INFO("[LPSPG-INFO] Max MU rate table Group ID :%d\n", _value);
  6840. #endif
  6841. /*Btye 8 ~15 - used Security CAM entry */
  6842. sec_cam_num = rtw_get_sec_camid(adapter, 8, psec_cam_id);
  6843. /*Btye 4 - used Security CAM entry number*/
  6844. if (sec_cam_num < 8)
  6845. LPSPG_RSVD_PAGE_SET_SEC_CAM_NUM(lps_pg_info, sec_cam_num);
  6846. RTW_INFO("[LPSPG-INFO] Security CAM entry number :%d\n", sec_cam_num);
  6847. /*Btye 5 - Txbuf used page number for fw offload*/
  6848. LPSPG_RSVD_PAGE_SET_DRV_RSVDPAGE_NUM(lps_pg_info, phal_data->drv_rsvd_page_number);
  6849. RTW_INFO("[LPSPG-INFO] DRV's rsvd page numbers :%d\n", phal_data->drv_rsvd_page_number);
  6850. #ifdef DBG_LPSPG_SEC_DUMP
  6851. {
  6852. int i;
  6853. for (i = 0; i < sec_cam_num; i++)
  6854. RTW_INFO("%d = sec_cam_id:%d\n", i, psec_cam_id[i]);
  6855. }
  6856. #endif
  6857. #ifdef DBG_LPSPG_INFO_DUMP
  6858. RTW_INFO("==== DBG_LPSPG_INFO_RSVD_PAGE_DUMP====\n");
  6859. RTW_INFO(" %02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
  6860. *(lps_pg_info), *(lps_pg_info + 1), *(lps_pg_info + 2), *(lps_pg_info + 3),
  6861. *(lps_pg_info + 4), *(lps_pg_info + 5), *(lps_pg_info + 6), *(lps_pg_info + 7));
  6862. RTW_INFO(" %02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
  6863. *(lps_pg_info + 8), *(lps_pg_info + 9), *(lps_pg_info + 10), *(lps_pg_info + 11),
  6864. *(lps_pg_info + 12), *(lps_pg_info + 13), *(lps_pg_info + 14), *(lps_pg_info + 15));
  6865. RTW_INFO("==== DBG_LPSPG_INFO_RSVD_PAGE_DUMP====\n");
  6866. #endif
  6867. rtw_halmac_download_rsvd_page(dvobj, pwrpriv->lpspg_rsvd_page_locate, lps_pg_info, LPS_PG_INFO_RSVD_LEN);
  6868. #ifdef DBG_LPSPG_INFO_DUMP
  6869. RTW_INFO("Get LPS-PG INFO from rsvd page_offset:%d\n", pwrpriv->lpspg_rsvd_page_locate);
  6870. rtw_dump_rsvd_page(RTW_DBGDUMP, adapter, pwrpriv->lpspg_rsvd_page_locate, 1);
  6871. #endif
  6872. }
  6873. static u8 rtw_hal_set_lps_pg_info_cmd(_adapter *adapter)
  6874. {
  6875. struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
  6876. struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
  6877. u8 lpspg_info[H2C_LPS_PG_INFO_LEN] = {0};
  6878. u8 ret = _FAIL;
  6879. RTW_INFO("%s: loc_lpspg_info:%d\n", __func__, pwrpriv->lpspg_rsvd_page_locate);
  6880. if (_NO_PRIVACY_ != adapter->securitypriv.dot11PrivacyAlgrthm)
  6881. SET_H2CCMD_LPSPG_SEC_CAM_EN(lpspg_info, 1); /*SecurityCAM_En*/
  6882. #ifdef CONFIG_MBSSID_CAM
  6883. SET_H2CCMD_LPSPG_MBID_CAM_EN(lpspg_info, 1); /*BSSIDCAM_En*/
  6884. #endif
  6885. #if defined(CONFIG_WOWLAN) && defined(CONFIG_WOW_PATTERN_HW_CAM)
  6886. if (pwrpriv->wowlan_mode == _TRUE &&
  6887. check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {
  6888. SET_H2CCMD_LPSPG_PMC_CAM_EN(lpspg_info, 1); /*PatternMatchCAM_En*/
  6889. }
  6890. #endif
  6891. #ifdef CONFIG_MACID_SEARCH
  6892. SET_H2CCMD_LPSPG_MACID_SEARCH_EN(lpspg_info, 1); /*MACIDSearch_En*/
  6893. #endif
  6894. #ifdef CONFIG_TX_SC
  6895. SET_H2CCMD_LPSPG_TXSC_EN(lpspg_info, 1); /*TXSC_En*/
  6896. #endif
  6897. #ifdef CONFIG_BEAMFORMING /*&& MU BF*/
  6898. SET_H2CCMD_LPSPG_MU_RATE_TB_EN(lpspg_info, 1); /*MURateTable_En*/
  6899. #endif
  6900. SET_H2CCMD_LPSPG_LOC(lpspg_info, pwrpriv->lpspg_rsvd_page_locate);
  6901. #ifdef DBG_LPSPG_INFO_DUMP
  6902. RTW_INFO("==== DBG_LPSPG_INFO_CMD_DUMP====\n");
  6903. RTW_INFO(" H2C_CMD: 0x%02x, H2C_LEN: %d\n", H2C_LPS_PG_INFO, H2C_LPS_PG_INFO_LEN);
  6904. RTW_INFO(" %02X:%02X\n", *(lpspg_info), *(lpspg_info + 1));
  6905. RTW_INFO("==== DBG_LPSPG_INFO_CMD_DUMP====\n");
  6906. #endif
  6907. ret = rtw_hal_fill_h2c_cmd(adapter,
  6908. H2C_LPS_PG_INFO,
  6909. H2C_LPS_PG_INFO_LEN,
  6910. lpspg_info);
  6911. return ret;
  6912. }
  6913. u8 rtw_hal_set_lps_pg_info(_adapter *adapter)
  6914. {
  6915. u8 ret = _FAIL;
  6916. struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
  6917. if (pwrpriv->lpspg_rsvd_page_locate == 0) {
  6918. RTW_ERR("%s [ERROR] lpspg_rsvd_page_locate = 0\n", __func__);
  6919. rtw_warn_on(1);
  6920. return ret;
  6921. }
  6922. rtw_hal_set_lps_pg_info_rsvd_page(adapter);
  6923. ret = rtw_hal_set_lps_pg_info_cmd(adapter);
  6924. if (_SUCCESS == ret)
  6925. pwrpriv->blpspg_info_up = _FALSE;
  6926. return ret;
  6927. }
  6928. void rtw_hal_lps_pg_rssi_lv_decide(_adapter *adapter, struct sta_info *sta)
  6929. {
  6930. #if 0
  6931. if (sta->rssi_level >= 4)
  6932. sta->lps_pg_rssi_lv = 3; /*RSSI High - 1SS_VHT_MCS7*/
  6933. else if (sta->rssi_level >= 2)
  6934. sta->lps_pg_rssi_lv = 2; /*RSSI Middle - 1SS_VHT_MCS3*/
  6935. else
  6936. sta->lps_pg_rssi_lv = 1; /*RSSI Lower - Lowest_rate*/
  6937. #else
  6938. sta->lps_pg_rssi_lv = 0;
  6939. #endif
  6940. RTW_INFO("%s mac-id:%d, rssi:%d, rssi_level:%d, lps_pg_rssi_lv:%d\n",
  6941. __func__, sta->mac_id, sta->rssi_stat.undecorated_smoothed_pwdb, sta->rssi_level, sta->lps_pg_rssi_lv);
  6942. }
  6943. void rtw_hal_lps_pg_handler(_adapter *adapter, enum lps_pg_hdl_id hdl_id)
  6944. {
  6945. switch (hdl_id) {
  6946. case LPS_PG_INFO_CFG:
  6947. rtw_hal_set_lps_pg_info(adapter);
  6948. break;
  6949. case LPS_PG_REDLEMEM:
  6950. {
  6951. /*set xmit_block*/
  6952. rtw_set_xmit_block(adapter, XMIT_BLOCK_REDLMEM);
  6953. if (_FAIL == rtw_hal_fw_mem_dl(adapter, FW_EMEM))
  6954. rtw_warn_on(1);
  6955. /*clearn xmit_block*/
  6956. rtw_clr_xmit_block(adapter, XMIT_BLOCK_REDLMEM);
  6957. }
  6958. break;
  6959. case LPS_PG_RESEND_H2C:
  6960. {
  6961. struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl;
  6962. struct sta_info *sta;
  6963. PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
  6964. int i;
  6965. for (i = 0; i < MACID_NUM_SW_LIMIT; i++) {
  6966. sta = macid_ctl->sta[i];
  6967. if (sta && !is_broadcast_mac_addr(sta->hwaddr)) {
  6968. rtw_hal_lps_pg_rssi_lv_decide(adapter, sta);
  6969. set_sta_rate(adapter, sta);
  6970. sta->lps_pg_rssi_lv = 0;
  6971. }
  6972. }
  6973. }
  6974. break;
  6975. default:
  6976. break;
  6977. }
  6978. }
  6979. #endif /*CONFIG_LPS_PG*/
  6980. /*
  6981. * Description: Fill the reserved packets that FW will use to RSVD page.
  6982. * Now we just send 4 types packet to rsvd page.
  6983. * (1)Beacon, (2)Ps-poll, (3)Null data, (4)ProbeRsp.
  6984. * Input:
  6985. * finished - FALSE:At the first time we will send all the packets as a large packet to Hw,
  6986. * so we need to set the packet length to total lengh.
  6987. * TRUE: At the second time, we should send the first packet (default:beacon)
  6988. * to Hw again and set the lengh in descriptor to the real beacon lengh.
  6989. * 2009.10.15 by tynli.
  6990. *
  6991. * Page Size = 128: 8188e, 8723a/b, 8192c/d,
  6992. * Page Size = 256: 8192e, 8821a
  6993. * Page Size = 512: 8812a
  6994. */
  6995. /*#define DBG_DUMP_SET_RSVD_PAGE*/
  6996. void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished)
  6997. {
  6998. PHAL_DATA_TYPE pHalData;
  6999. struct xmit_frame *pcmdframe;
  7000. struct pkt_attrib *pattrib;
  7001. struct xmit_priv *pxmitpriv;
  7002. struct mlme_ext_priv *pmlmeext;
  7003. struct mlme_ext_info *pmlmeinfo;
  7004. struct pwrctrl_priv *pwrctl;
  7005. struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
  7006. struct hal_ops *pHalFunc = &adapter->hal_func;
  7007. u32 BeaconLength = 0, ProbeRspLength = 0, PSPollLength = 0;
  7008. u32 NullDataLength = 0, QosNullLength = 0, BTQosNullLength = 0;
  7009. u32 ProbeReqLength = 0, NullFunctionDataLength = 0;
  7010. u8 TxDescLen = TXDESC_SIZE, TxDescOffset = TXDESC_OFFSET;
  7011. u8 TotalPageNum = 0 , CurtPktPageNum = 0 , RsvdPageNum = 0;
  7012. u8 *ReservedPagePacket;
  7013. u16 BufIndex = 0;
  7014. u32 TotalPacketLen = 0, MaxRsvdPageBufSize = 0, PageSize = 0;
  7015. RSVDPAGE_LOC RsvdPageLoc;
  7016. #ifdef DBG_CONFIG_ERROR_DETECT
  7017. struct sreset_priv *psrtpriv;
  7018. #endif /* DBG_CONFIG_ERROR_DETECT */
  7019. #ifdef CONFIG_MCC_MODE
  7020. u8 dl_mcc_page = _FAIL;
  7021. #endif /* CONFIG_MCC_MODE */
  7022. pHalData = GET_HAL_DATA(adapter);
  7023. #ifdef DBG_CONFIG_ERROR_DETECT
  7024. psrtpriv = &pHalData->srestpriv;
  7025. #endif
  7026. pxmitpriv = &adapter->xmitpriv;
  7027. pmlmeext = &adapter->mlmeextpriv;
  7028. pmlmeinfo = &pmlmeext->mlmext_info;
  7029. pwrctl = adapter_to_pwrctl(adapter);
  7030. rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, (u8 *)&PageSize);
  7031. if (PageSize == 0) {
  7032. RTW_INFO("[Error]: %s, PageSize is zero!!\n", __func__);
  7033. return;
  7034. }
  7035. if (pwrctl->wowlan_mode == _TRUE || pwrctl->wowlan_ap_mode == _TRUE)
  7036. RsvdPageNum = rtw_hal_get_txbuff_rsvd_page_num(adapter, _TRUE);
  7037. else
  7038. RsvdPageNum = rtw_hal_get_txbuff_rsvd_page_num(adapter, _FALSE);
  7039. RTW_INFO("%s PageSize: %d, RsvdPageNUm: %d\n", __func__, PageSize, RsvdPageNum);
  7040. MaxRsvdPageBufSize = RsvdPageNum * PageSize;
  7041. if (MaxRsvdPageBufSize > MAX_CMDBUF_SZ) {
  7042. RTW_INFO("%s MaxRsvdPageBufSize(%d) is larger than MAX_CMDBUF_SZ(%d)",
  7043. __func__, MaxRsvdPageBufSize, MAX_CMDBUF_SZ);
  7044. rtw_warn_on(1);
  7045. return;
  7046. }
  7047. pcmdframe = rtw_alloc_cmdxmitframe(pxmitpriv);
  7048. if (pcmdframe == NULL) {
  7049. RTW_INFO("%s: alloc ReservedPagePacket fail!\n", __FUNCTION__);
  7050. return;
  7051. }
  7052. ReservedPagePacket = pcmdframe->buf_addr;
  7053. _rtw_memset(&RsvdPageLoc, 0, sizeof(RSVDPAGE_LOC));
  7054. /* beacon * 2 pages */
  7055. BufIndex = TxDescOffset;
  7056. rtw_hal_construct_beacon(adapter,
  7057. &ReservedPagePacket[BufIndex], &BeaconLength);
  7058. /*
  7059. * When we count the first page size, we need to reserve description size for the RSVD
  7060. * packet, it will be filled in front of the packet in TXPKTBUF.
  7061. */
  7062. CurtPktPageNum = (u8)PageNum((TxDescLen + BeaconLength), PageSize);
  7063. /* If we don't add 1 more page, ARP offload function will fail at 8723bs.*/
  7064. if (CurtPktPageNum == 1)
  7065. CurtPktPageNum += 1;
  7066. TotalPageNum += CurtPktPageNum;
  7067. BufIndex += (CurtPktPageNum * PageSize);
  7068. if (pwrctl->wowlan_ap_mode == _TRUE) {
  7069. /* (4) probe response*/
  7070. RsvdPageLoc.LocProbeRsp = TotalPageNum;
  7071. rtw_hal_construct_ProbeRsp(
  7072. adapter, &ReservedPagePacket[BufIndex],
  7073. &ProbeRspLength,
  7074. get_my_bssid(&pmlmeinfo->network), _FALSE);
  7075. rtw_hal_fill_fake_txdesc(adapter,
  7076. &ReservedPagePacket[BufIndex - TxDescLen],
  7077. ProbeRspLength, _FALSE, _FALSE, _FALSE);
  7078. CurtPktPageNum = (u8)PageNum(TxDescLen + ProbeRspLength, PageSize);
  7079. TotalPageNum += CurtPktPageNum;
  7080. TotalPacketLen = BufIndex + ProbeRspLength;
  7081. BufIndex += (CurtPktPageNum * PageSize);
  7082. goto download_page;
  7083. }
  7084. /* ps-poll * 1 page */
  7085. RsvdPageLoc.LocPsPoll = TotalPageNum;
  7086. RTW_INFO("LocPsPoll: %d\n", RsvdPageLoc.LocPsPoll);
  7087. rtw_hal_construct_PSPoll(adapter,
  7088. &ReservedPagePacket[BufIndex], &PSPollLength);
  7089. rtw_hal_fill_fake_txdesc(adapter,
  7090. &ReservedPagePacket[BufIndex - TxDescLen],
  7091. PSPollLength, _TRUE, _FALSE, _FALSE);
  7092. CurtPktPageNum = (u8)PageNum((TxDescLen + PSPollLength), PageSize);
  7093. TotalPageNum += CurtPktPageNum;
  7094. BufIndex += (CurtPktPageNum * PageSize);
  7095. #ifdef CONFIG_BT_COEXIST
  7096. /* BT Qos null data * 1 page */
  7097. RsvdPageLoc.LocBTQosNull = TotalPageNum;
  7098. RTW_INFO("LocBTQosNull: %d\n", RsvdPageLoc.LocBTQosNull);
  7099. rtw_hal_construct_NullFunctionData(
  7100. adapter,
  7101. &ReservedPagePacket[BufIndex],
  7102. &BTQosNullLength,
  7103. get_my_bssid(&pmlmeinfo->network),
  7104. _TRUE, 0, 0, _FALSE);
  7105. rtw_hal_fill_fake_txdesc(adapter,
  7106. &ReservedPagePacket[BufIndex - TxDescLen],
  7107. BTQosNullLength, _FALSE, _TRUE, _FALSE);
  7108. CurtPktPageNum = (u8)PageNum(TxDescLen + BTQosNullLength, PageSize);
  7109. TotalPageNum += CurtPktPageNum;
  7110. BufIndex += (CurtPktPageNum * PageSize);
  7111. #endif /* CONFIG_BT_COEXIT */
  7112. #ifdef CONFIG_MCC_MODE
  7113. if (MCC_EN(adapter)) {
  7114. dl_mcc_page = rtw_hal_dl_mcc_fw_rsvd_page(adapter, ReservedPagePacket,
  7115. &BufIndex, TxDescLen, PageSize,
  7116. &TotalPageNum, &TotalPacketLen, &RsvdPageLoc);
  7117. } else
  7118. dl_mcc_page = _FAIL;
  7119. if (dl_mcc_page == _FAIL) {
  7120. #endif /* CONFIG_MCC_MODE */
  7121. /* null data * 1 page */
  7122. RsvdPageLoc.LocNullData = TotalPageNum;
  7123. RTW_INFO("LocNullData: %d\n", RsvdPageLoc.LocNullData);
  7124. rtw_hal_construct_NullFunctionData(
  7125. adapter,
  7126. &ReservedPagePacket[BufIndex],
  7127. &NullDataLength,
  7128. get_my_bssid(&pmlmeinfo->network),
  7129. _FALSE, 0, 0, _FALSE);
  7130. rtw_hal_fill_fake_txdesc(adapter,
  7131. &ReservedPagePacket[BufIndex - TxDescLen],
  7132. NullDataLength, _FALSE, _FALSE, _FALSE);
  7133. CurtPktPageNum = (u8)PageNum(TxDescLen + NullDataLength, PageSize);
  7134. TotalPageNum += CurtPktPageNum;
  7135. BufIndex += (CurtPktPageNum * PageSize);
  7136. #ifdef CONFIG_MCC_MODE
  7137. }
  7138. #endif /* CONFIG_MCC_MODE */
  7139. /* Qos null data * 1 page */
  7140. RsvdPageLoc.LocQosNull = TotalPageNum;
  7141. RTW_INFO("LocQosNull: %d\n", RsvdPageLoc.LocQosNull);
  7142. rtw_hal_construct_NullFunctionData(
  7143. adapter,
  7144. &ReservedPagePacket[BufIndex],
  7145. &QosNullLength,
  7146. get_my_bssid(&pmlmeinfo->network),
  7147. _TRUE, 0, 0, _FALSE);
  7148. rtw_hal_fill_fake_txdesc(adapter,
  7149. &ReservedPagePacket[BufIndex - TxDescLen],
  7150. QosNullLength, _FALSE, _FALSE, _FALSE);
  7151. CurtPktPageNum = (u8)PageNum(TxDescLen + QosNullLength, PageSize);
  7152. TotalPageNum += CurtPktPageNum;
  7153. TotalPacketLen = BufIndex + QosNullLength;
  7154. BufIndex += (CurtPktPageNum * PageSize);
  7155. #ifdef CONFIG_WOWLAN
  7156. if (pwrctl->wowlan_mode == _TRUE &&
  7157. pwrctl->wowlan_in_resume == _FALSE) {
  7158. rtw_hal_set_wow_fw_rsvd_page(adapter, ReservedPagePacket,
  7159. BufIndex, TxDescLen, PageSize,
  7160. &TotalPageNum, &TotalPacketLen, &RsvdPageLoc);
  7161. }
  7162. #endif /* CONFIG_WOWLAN */
  7163. #ifdef CONFIG_P2P_WOWLAN
  7164. if (_TRUE == pwrctl->wowlan_p2p_mode) {
  7165. rtw_hal_set_p2p_wow_fw_rsvd_page(adapter, ReservedPagePacket,
  7166. BufIndex, TxDescLen, PageSize,
  7167. &TotalPageNum, &TotalPacketLen, &RsvdPageLoc);
  7168. }
  7169. #endif /* CONFIG_P2P_WOWLAN */
  7170. #ifdef CONFIG_LPS_PG
  7171. /* must reserved last 1 x page for LPS PG Info*/
  7172. pwrctl->lpspg_rsvd_page_locate = TotalPageNum;
  7173. pwrctl->blpspg_info_up = _TRUE;
  7174. #endif
  7175. download_page:
  7176. /* RTW_INFO("%s BufIndex(%d), TxDescLen(%d), PageSize(%d)\n",__func__, BufIndex, TxDescLen, PageSize);*/
  7177. RTW_INFO("%s PageNum(%d), pktlen(%d)\n",
  7178. __func__, TotalPageNum, TotalPacketLen);
  7179. #ifdef CONFIG_LPS_PG
  7180. if ((TotalPacketLen + (LPS_PG_INFO_RSVD_PAGE_NUM * PageSize)) > MaxRsvdPageBufSize) {
  7181. pwrctl->lpspg_rsvd_page_locate = 0;
  7182. pwrctl->blpspg_info_up = _FALSE;
  7183. RTW_ERR("%s rsvd page size is not enough!!TotalPacketLen+LPS_PG_INFO_LEN %d, MaxRsvdPageBufSize %d\n",
  7184. __func__, (TotalPacketLen + (LPS_PG_INFO_RSVD_PAGE_NUM * PageSize)), MaxRsvdPageBufSize);
  7185. rtw_warn_on(1);
  7186. }
  7187. #endif
  7188. if (TotalPacketLen > MaxRsvdPageBufSize) {
  7189. RTW_ERR("%s(ERROR): rsvd page size is not enough!!TotalPacketLen %d, MaxRsvdPageBufSize %d\n",
  7190. __FUNCTION__, TotalPacketLen, MaxRsvdPageBufSize);
  7191. rtw_warn_on(1);
  7192. goto error;
  7193. } else {
  7194. /* update attribute */
  7195. pattrib = &pcmdframe->attrib;
  7196. update_mgntframe_attrib(adapter, pattrib);
  7197. pattrib->qsel = QSLT_BEACON;
  7198. pattrib->pktlen = TotalPacketLen - TxDescOffset;
  7199. pattrib->last_txcmdsz = TotalPacketLen - TxDescOffset;
  7200. #ifdef CONFIG_PCI_HCI
  7201. dump_mgntframe(adapter, pcmdframe);
  7202. #else
  7203. dump_mgntframe_and_wait(adapter, pcmdframe, 100);
  7204. #endif
  7205. }
  7206. RTW_INFO("%s: Set RSVD page location to Fw ,TotalPacketLen(%d), TotalPageNum(%d)\n",
  7207. __func__, TotalPacketLen, TotalPageNum);
  7208. #ifdef DBG_DUMP_SET_RSVD_PAGE
  7209. RTW_INFO(" ==================================================\n");
  7210. RTW_INFO_DUMP("\n", ReservedPagePacket, TotalPacketLen);
  7211. RTW_INFO(" ==================================================\n");
  7212. #endif
  7213. if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {
  7214. rtw_hal_set_FwRsvdPage_cmd(adapter, &RsvdPageLoc);
  7215. #ifdef CONFIG_WOWLAN
  7216. if (pwrctl->wowlan_mode == _TRUE &&
  7217. pwrctl->wowlan_in_resume == _FALSE)
  7218. rtw_hal_set_FwAoacRsvdPage_cmd(adapter, &RsvdPageLoc);
  7219. #endif /* CONFIG_WOWLAN */
  7220. #ifdef CONFIG_AP_WOWLAN
  7221. if (pwrctl->wowlan_ap_mode == _TRUE)
  7222. rtw_hal_set_ap_rsvdpage_loc_cmd(adapter, &RsvdPageLoc);
  7223. #endif /* CONFIG_AP_WOWLAN */
  7224. } else if (pwrctl->wowlan_pno_enable) {
  7225. #ifdef CONFIG_PNO_SUPPORT
  7226. rtw_hal_set_FwAoacRsvdPage_cmd(adapter, &RsvdPageLoc);
  7227. if (pwrctl->wowlan_in_resume)
  7228. rtw_hal_set_scan_offload_info_cmd(adapter,
  7229. &RsvdPageLoc, 0);
  7230. else
  7231. rtw_hal_set_scan_offload_info_cmd(adapter,
  7232. &RsvdPageLoc, 1);
  7233. #endif /* CONFIG_PNO_SUPPORT */
  7234. }
  7235. #ifdef CONFIG_P2P_WOWLAN
  7236. if (_TRUE == pwrctl->wowlan_p2p_mode)
  7237. rtw_hal_set_FwP2PRsvdPage_cmd(adapter, &RsvdPageLoc);
  7238. #endif /* CONFIG_P2P_WOWLAN */
  7239. return;
  7240. error:
  7241. rtw_free_xmitframe(pxmitpriv, pcmdframe);
  7242. }
  7243. static void rtw_hal_set_hw_update_tsf(PADAPTER padapter)
  7244. {
  7245. struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
  7246. struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
  7247. #if defined(CONFIG_RTL8822B) || defined(CONFIG_MI_WITH_MBSSID_CAM)
  7248. RTW_INFO("[Warn] %s "ADPT_FMT" enter func\n", __func__, ADPT_ARG(padapter));
  7249. rtw_warn_on(1);
  7250. return;
  7251. #endif
  7252. if (!pmlmeext->en_hw_update_tsf)
  7253. return;
  7254. /* check REG_RCR bit is set */
  7255. if (!(rtw_read32(padapter, REG_RCR) & RCR_CBSSID_BCN))
  7256. return;
  7257. /* enable hw update tsf function for non-AP */
  7258. if (rtw_linked_check(padapter) &&
  7259. check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) {
  7260. #ifdef CONFIG_CONCURRENT_MODE
  7261. if (padapter->hw_port == HW_PORT1)
  7262. rtw_write8(padapter, REG_BCN_CTRL_1, rtw_read8(padapter, REG_BCN_CTRL_1) & (~DIS_TSF_UDT));
  7263. else
  7264. #endif
  7265. rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL) & (~DIS_TSF_UDT));
  7266. }
  7267. pmlmeext->en_hw_update_tsf = _FALSE;
  7268. }
  7269. #ifdef CONFIG_TDLS
  7270. #ifdef CONFIG_TDLS_CH_SW
  7271. s32 rtw_hal_ch_sw_oper_offload(_adapter *padapter, u8 channel, u8 channel_offset, u16 bwmode)
  7272. {
  7273. PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
  7274. u8 ch_sw_h2c_buf[4] = {0x00, 0x00, 0x00, 0x00};
  7275. SET_H2CCMD_CH_SW_OPER_OFFLOAD_CH_NUM(ch_sw_h2c_buf, channel);
  7276. SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_MODE(ch_sw_h2c_buf, bwmode);
  7277. switch (bwmode) {
  7278. case CHANNEL_WIDTH_40:
  7279. SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_40M_SC(ch_sw_h2c_buf, channel_offset);
  7280. break;
  7281. case CHANNEL_WIDTH_80:
  7282. SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_80M_SC(ch_sw_h2c_buf, channel_offset);
  7283. break;
  7284. case CHANNEL_WIDTH_20:
  7285. default:
  7286. break;
  7287. }
  7288. SET_H2CCMD_CH_SW_OPER_OFFLOAD_RFE_TYPE(ch_sw_h2c_buf, pHalData->rfe_type);
  7289. return rtw_hal_fill_h2c_cmd(padapter, H2C_CHNL_SWITCH_OPER_OFFLOAD, sizeof(ch_sw_h2c_buf), ch_sw_h2c_buf);
  7290. }
  7291. #endif
  7292. #endif
  7293. #ifdef CONFIG_WMMPS
  7294. void rtw_hal_update_uapsd_tid(_adapter *adapter)
  7295. {
  7296. rtw_write8(adapter, REG_WMMPS_UAPSD_TID, 0xFF);
  7297. }
  7298. #endif
  7299. #if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT)
  7300. /* For multi-port support, driver needs to inform the port ID to FW for btc operations */
  7301. s32 rtw_hal_set_wifi_port_id_cmd(_adapter *adapter)
  7302. {
  7303. u8 port_id = 0;
  7304. u8 h2c_buf[H2C_BTC_WL_PORT_ID_LEN] = {0};
  7305. SET_H2CCMD_BTC_WL_PORT_ID(h2c_buf, adapter->hw_port);
  7306. return rtw_hal_fill_h2c_cmd(adapter, H2C_BTC_WL_PORT_ID, H2C_BTC_WL_PORT_ID_LEN, h2c_buf);
  7307. }
  7308. #endif
  7309. void SetHwReg(_adapter *adapter, u8 variable, u8 *val)
  7310. {
  7311. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
  7312. switch (variable) {
  7313. case HW_VAR_MEDIA_STATUS: {
  7314. u8 net_type = *((u8 *)val);
  7315. rtw_hal_set_msr(adapter, net_type);
  7316. }
  7317. break;
  7318. case HW_VAR_MAC_ADDR:
  7319. #ifdef CONFIG_MI_WITH_MBSSID_CAM
  7320. rtw_hal_set_macaddr_mbid(adapter, val);
  7321. #else
  7322. rtw_hal_set_macaddr_port(adapter, val);
  7323. #endif
  7324. break;
  7325. case HW_VAR_BSSID:
  7326. rtw_hal_set_bssid(adapter, val);
  7327. break;
  7328. #ifdef CONFIG_MBSSID_CAM
  7329. case HW_VAR_MBSSID_CAM_WRITE: {
  7330. u32 cmd = 0;
  7331. u32 *cam_val = (u32 *)val;
  7332. rtw_write32(adapter, REG_MBIDCAMCFG_1, cam_val[0]);
  7333. cmd = BIT_MBIDCAM_POLL | BIT_MBIDCAM_WT_EN | BIT_MBIDCAM_VALID | cam_val[1];
  7334. rtw_write32(adapter, REG_MBIDCAMCFG_2, cmd);
  7335. }
  7336. break;
  7337. case HW_VAR_MBSSID_CAM_CLEAR: {
  7338. u32 cmd;
  7339. u8 entry_id = *(u8 *)val;
  7340. rtw_write32(adapter, REG_MBIDCAMCFG_1, 0);
  7341. cmd = BIT_MBIDCAM_POLL | BIT_MBIDCAM_WT_EN | ((entry_id & MBIDCAM_ADDR_MASK) << MBIDCAM_ADDR_SHIFT);
  7342. rtw_write32(adapter, REG_MBIDCAMCFG_2, cmd);
  7343. }
  7344. break;
  7345. case HW_VAR_RCR_MBSSID_EN:
  7346. if (*((u8 *)val))
  7347. rtw_write32(adapter, REG_RCR, rtw_read32(adapter, REG_RCR) | RCR_ENMBID);
  7348. else {
  7349. u32 val32;
  7350. val32 = rtw_read32(adapter, REG_RCR);
  7351. val32 &= ~(RCR_ENMBID);
  7352. rtw_write32(adapter, REG_RCR, val32);
  7353. }
  7354. break;
  7355. #endif
  7356. case HW_VAR_PORT_SWITCH:
  7357. hw_var_port_switch(adapter);
  7358. break;
  7359. case HW_VAR_INIT_RTS_RATE: {
  7360. u16 brate_cfg = *((u16 *)val);
  7361. u8 rate_index = 0;
  7362. HAL_VERSION *hal_ver = &hal_data->version_id;
  7363. if (IS_8188E(*hal_ver)) {
  7364. while (brate_cfg > 0x1) {
  7365. brate_cfg = (brate_cfg >> 1);
  7366. rate_index++;
  7367. }
  7368. rtw_write8(adapter, REG_INIRTS_RATE_SEL, rate_index);
  7369. } else
  7370. rtw_warn_on(1);
  7371. }
  7372. break;
  7373. case HW_VAR_SEC_CFG: {
  7374. u16 reg_scr_ori;
  7375. u16 reg_scr;
  7376. reg_scr = reg_scr_ori = rtw_read16(adapter, REG_SECCFG);
  7377. reg_scr |= (SCR_CHK_KEYID | SCR_RxDecEnable | SCR_TxEncEnable);
  7378. if (_rtw_camctl_chk_cap(adapter, SEC_CAP_CHK_BMC))
  7379. reg_scr |= SCR_CHK_BMC;
  7380. if (_rtw_camctl_chk_flags(adapter, SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH))
  7381. reg_scr |= SCR_NoSKMC;
  7382. if (reg_scr != reg_scr_ori)
  7383. rtw_write16(adapter, REG_SECCFG, reg_scr);
  7384. }
  7385. break;
  7386. case HW_VAR_SEC_DK_CFG: {
  7387. struct security_priv *sec = &adapter->securitypriv;
  7388. u8 reg_scr = rtw_read8(adapter, REG_SECCFG);
  7389. if (val) { /* Enable default key related setting */
  7390. reg_scr |= SCR_TXBCUSEDK;
  7391. if (sec->dot11AuthAlgrthm != dot11AuthAlgrthm_8021X)
  7392. reg_scr |= (SCR_RxUseDK | SCR_TxUseDK);
  7393. } else /* Disable default key related setting */
  7394. reg_scr &= ~(SCR_RXBCUSEDK | SCR_TXBCUSEDK | SCR_RxUseDK | SCR_TxUseDK);
  7395. rtw_write8(adapter, REG_SECCFG, reg_scr);
  7396. }
  7397. break;
  7398. case HW_VAR_ASIX_IOT:
  7399. /* enable ASIX IOT function */
  7400. if (*((u8 *)val) == _TRUE) {
  7401. /* 0xa2e[0]=0 (disable rake receiver) */
  7402. rtw_write8(adapter, rCCK0_FalseAlarmReport + 2,
  7403. rtw_read8(adapter, rCCK0_FalseAlarmReport + 2) & ~(BIT0));
  7404. /* 0xa1c=0xa0 (reset channel estimation if signal quality is bad) */
  7405. rtw_write8(adapter, rCCK0_DSPParameter2, 0xa0);
  7406. } else {
  7407. /* restore reg:0xa2e, reg:0xa1c */
  7408. rtw_write8(adapter, rCCK0_FalseAlarmReport + 2,
  7409. rtw_read8(adapter, rCCK0_FalseAlarmReport + 2) | (BIT0));
  7410. rtw_write8(adapter, rCCK0_DSPParameter2, 0x00);
  7411. }
  7412. break;
  7413. #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
  7414. case HW_VAR_WOWLAN: {
  7415. struct wowlan_ioctl_param *poidparam;
  7416. poidparam = (struct wowlan_ioctl_param *)val;
  7417. switch (poidparam->subcode) {
  7418. #ifdef CONFIG_WOWLAN
  7419. case WOWLAN_PATTERN_CLEAN:
  7420. rtw_hal_dl_pattern(adapter, 2);
  7421. break;
  7422. case WOWLAN_ENABLE:
  7423. rtw_hal_wow_enable(adapter);
  7424. break;
  7425. case WOWLAN_DISABLE:
  7426. rtw_hal_wow_disable(adapter);
  7427. break;
  7428. #endif /*CONFIG_WOWLAN*/
  7429. #ifdef CONFIG_AP_WOWLAN
  7430. case WOWLAN_AP_ENABLE:
  7431. rtw_hal_ap_wow_enable(adapter);
  7432. break;
  7433. case WOWLAN_AP_DISABLE:
  7434. rtw_hal_ap_wow_disable(adapter);
  7435. break;
  7436. #endif /*CONFIG_AP_WOWLAN*/
  7437. default:
  7438. break;
  7439. }
  7440. }
  7441. break;
  7442. #endif /*defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)*/
  7443. case HW_VAR_EN_HW_UPDATE_TSF:
  7444. rtw_hal_set_hw_update_tsf(adapter);
  7445. break;
  7446. case HW_VAR_APFM_ON_MAC:
  7447. hal_data->bMacPwrCtrlOn = *val;
  7448. RTW_INFO("%s: bMacPwrCtrlOn=%d\n", __func__, hal_data->bMacPwrCtrlOn);
  7449. break;
  7450. #ifdef CONFIG_WMMPS
  7451. case HW_VAR_UAPSD_TID:
  7452. rtw_hal_update_uapsd_tid(adapter);
  7453. break;
  7454. #endif
  7455. #ifdef CONFIG_LPS_PG
  7456. case HW_VAR_LPS_PG_HANDLE:
  7457. rtw_hal_lps_pg_handler(adapter, *val);
  7458. break;
  7459. #endif
  7460. default:
  7461. if (0)
  7462. RTW_PRINT(FUNC_ADPT_FMT" variable(%d) not defined!\n",
  7463. FUNC_ADPT_ARG(adapter), variable);
  7464. break;
  7465. }
  7466. }
  7467. void GetHwReg(_adapter *adapter, u8 variable, u8 *val)
  7468. {
  7469. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
  7470. switch (variable) {
  7471. case HW_VAR_BASIC_RATE:
  7472. *((u16 *)val) = hal_data->BasicRateSet;
  7473. break;
  7474. case HW_VAR_RF_TYPE:
  7475. *((u8 *)val) = hal_data->rf_type;
  7476. break;
  7477. case HW_VAR_MEDIA_STATUS:
  7478. rtw_hal_get_msr(adapter, val);
  7479. break;
  7480. case HW_VAR_DO_IQK:
  7481. *val = hal_data->bNeedIQK;
  7482. break;
  7483. case HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO:
  7484. if (hal_is_band_support(adapter, BAND_ON_5G))
  7485. *val = _TRUE;
  7486. else
  7487. *val = _FALSE;
  7488. break;
  7489. case HW_VAR_APFM_ON_MAC:
  7490. *val = hal_data->bMacPwrCtrlOn;
  7491. break;
  7492. default:
  7493. if (0)
  7494. RTW_PRINT(FUNC_ADPT_FMT" variable(%d) not defined!\n",
  7495. FUNC_ADPT_ARG(adapter), variable);
  7496. break;
  7497. }
  7498. }
  7499. u8
  7500. SetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value)
  7501. {
  7502. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
  7503. u8 bResult = _SUCCESS;
  7504. switch (variable) {
  7505. case HAL_DEF_DBG_DUMP_RXPKT:
  7506. hal_data->bDumpRxPkt = *((u8 *)value);
  7507. break;
  7508. case HAL_DEF_DBG_DUMP_TXPKT:
  7509. hal_data->bDumpTxPkt = *((u8 *)value);
  7510. break;
  7511. case HAL_DEF_ANT_DETECT:
  7512. hal_data->AntDetection = *((u8 *)value);
  7513. break;
  7514. case HAL_DEF_DBG_DIS_PWT:
  7515. hal_data->bDisableTXPowerTraining = *((u8 *)value);
  7516. break;
  7517. default:
  7518. RTW_PRINT("%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\n", __FUNCTION__, variable);
  7519. bResult = _FAIL;
  7520. break;
  7521. }
  7522. return bResult;
  7523. }
  7524. #ifdef CONFIG_BEAMFORMING
  7525. u8 rtw_hal_query_txbfer_rf_num(_adapter *adapter)
  7526. {
  7527. struct registry_priv *pregistrypriv = &adapter->registrypriv;
  7528. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
  7529. if ((pregistrypriv->beamformer_rf_num) && (IS_HARDWARE_TYPE_8814AE(adapter) || IS_HARDWARE_TYPE_8814AU(adapter) || IS_HARDWARE_TYPE_8822BU(adapter) || IS_HARDWARE_TYPE_8821C(adapter)))
  7530. return pregistrypriv->beamformer_rf_num;
  7531. else if (IS_HARDWARE_TYPE_8814AE(adapter)
  7532. #if 0
  7533. #if defined(CONFIG_USB_HCI)
  7534. || (IS_HARDWARE_TYPE_8814AU(adapter) && (pUsbModeMech->CurUsbMode == 2 || pUsbModeMech->HubUsbMode == 2)) /* for USB3.0 */
  7535. #endif
  7536. #endif
  7537. ) {
  7538. /*BF cap provided by Yu Chen, Sean, 2015, 01 */
  7539. if (hal_data->rf_type == RF_3T3R)
  7540. return 2;
  7541. else if (hal_data->rf_type == RF_4T4R)
  7542. return 3;
  7543. else
  7544. return 1;
  7545. } else
  7546. return 1;
  7547. }
  7548. u8 rtw_hal_query_txbfee_rf_num(_adapter *adapter)
  7549. {
  7550. struct registry_priv *pregistrypriv = &adapter->registrypriv;
  7551. struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
  7552. struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
  7553. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
  7554. if ((pregistrypriv->beamformee_rf_num) && (IS_HARDWARE_TYPE_8814AE(adapter) || IS_HARDWARE_TYPE_8814AU(adapter) || IS_HARDWARE_TYPE_8822BU(adapter) || IS_HARDWARE_TYPE_8821C(adapter)))
  7555. return pregistrypriv->beamformee_rf_num;
  7556. else if (IS_HARDWARE_TYPE_8814AE(adapter) || IS_HARDWARE_TYPE_8814AU(adapter)) {
  7557. if (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM)
  7558. return 2;
  7559. else
  7560. return 2;/*TODO: May be 3 in the future, by ChenYu. */
  7561. } else
  7562. return 1;
  7563. }
  7564. #endif
  7565. u8
  7566. GetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value)
  7567. {
  7568. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
  7569. u8 bResult = _SUCCESS;
  7570. switch (variable) {
  7571. case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB: {
  7572. struct mlme_priv *pmlmepriv;
  7573. struct sta_priv *pstapriv;
  7574. struct sta_info *psta;
  7575. pmlmepriv = &adapter->mlmepriv;
  7576. pstapriv = &adapter->stapriv;
  7577. psta = rtw_get_stainfo(pstapriv, pmlmepriv->cur_network.network.MacAddress);
  7578. if (psta)
  7579. *((int *)value) = psta->rssi_stat.undecorated_smoothed_pwdb;
  7580. }
  7581. break;
  7582. case HAL_DEF_DBG_DUMP_RXPKT:
  7583. *((u8 *)value) = hal_data->bDumpRxPkt;
  7584. break;
  7585. case HAL_DEF_DBG_DUMP_TXPKT:
  7586. *((u8 *)value) = hal_data->bDumpTxPkt;
  7587. break;
  7588. case HAL_DEF_ANT_DETECT:
  7589. *((u8 *)value) = hal_data->AntDetection;
  7590. break;
  7591. case HAL_DEF_MACID_SLEEP:
  7592. *(u8 *)value = _FALSE;
  7593. break;
  7594. case HAL_DEF_TX_PAGE_SIZE:
  7595. *((u32 *)value) = PAGE_SIZE_128;
  7596. break;
  7597. case HAL_DEF_DBG_DIS_PWT:
  7598. *(u8 *)value = hal_data->bDisableTXPowerTraining;
  7599. break;
  7600. case HAL_DEF_EXPLICIT_BEAMFORMER:
  7601. case HAL_DEF_EXPLICIT_BEAMFORMEE:
  7602. case HAL_DEF_VHT_MU_BEAMFORMER:
  7603. case HAL_DEF_VHT_MU_BEAMFORMEE:
  7604. *(u8 *)value = _FALSE;
  7605. break;
  7606. #ifdef CONFIG_BEAMFORMING
  7607. case HAL_DEF_BEAMFORMER_CAP:
  7608. *(u8 *)value = rtw_hal_query_txbfer_rf_num(adapter);
  7609. break;
  7610. case HAL_DEF_BEAMFORMEE_CAP:
  7611. *(u8 *)value = rtw_hal_query_txbfee_rf_num(adapter);
  7612. break;
  7613. #endif
  7614. default:
  7615. RTW_PRINT("%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\n", __FUNCTION__, variable);
  7616. bResult = _FAIL;
  7617. break;
  7618. }
  7619. return bResult;
  7620. }
  7621. void SetHalODMVar(
  7622. PADAPTER Adapter,
  7623. HAL_ODM_VARIABLE eVariable,
  7624. PVOID pValue1,
  7625. BOOLEAN bSet)
  7626. {
  7627. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
  7628. struct PHY_DM_STRUCT *podmpriv = &pHalData->odmpriv;
  7629. /* _irqL irqL; */
  7630. switch (eVariable) {
  7631. case HAL_ODM_STA_INFO: {
  7632. struct sta_info *psta = (struct sta_info *)pValue1;
  7633. if (bSet) {
  7634. RTW_INFO("### Set STA_(%d) info ###\n", psta->mac_id);
  7635. odm_cmn_info_ptr_array_hook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->mac_id, psta);
  7636. } else {
  7637. RTW_INFO("### Clean STA_(%d) info ###\n", psta->mac_id);
  7638. /* _enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */
  7639. psta->rssi_level = 0;
  7640. odm_cmn_info_ptr_array_hook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->mac_id, NULL);
  7641. /* _exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */
  7642. }
  7643. }
  7644. break;
  7645. case HAL_ODM_P2P_STATE:
  7646. odm_cmn_info_update(podmpriv, ODM_CMNINFO_WIFI_DIRECT, bSet);
  7647. break;
  7648. case HAL_ODM_WIFI_DISPLAY_STATE:
  7649. odm_cmn_info_update(podmpriv, ODM_CMNINFO_WIFI_DISPLAY, bSet);
  7650. break;
  7651. case HAL_ODM_REGULATION:
  7652. odm_cmn_info_init(podmpriv, ODM_CMNINFO_DOMAIN_CODE_2G, pHalData->Regulation2_4G);
  7653. odm_cmn_info_init(podmpriv, ODM_CMNINFO_DOMAIN_CODE_5G, pHalData->Regulation5G);
  7654. break;
  7655. #if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR)
  7656. case HAL_ODM_NOISE_MONITOR: {
  7657. struct noise_info *pinfo = (struct noise_info *)pValue1;
  7658. #ifdef DBG_NOISE_MONITOR
  7659. RTW_INFO("### Noise monitor chan(%d)-bPauseDIG:%d,IGIValue:0x%02x,max_time:%d (ms) ###\n",
  7660. pinfo->chan, pinfo->bPauseDIG, pinfo->IGIValue, pinfo->max_time);
  7661. #endif
  7662. pHalData->noise[pinfo->chan] = odm_inband_noise_monitor(podmpriv, pinfo->is_pause_dig, pinfo->igi_value, pinfo->max_time);
  7663. RTW_INFO("chan_%d, noise = %d (dBm)\n", pinfo->chan, pHalData->noise[pinfo->chan]);
  7664. #ifdef DBG_NOISE_MONITOR
  7665. RTW_INFO("noise_a = %d, noise_b = %d noise_all:%d\n",
  7666. podmpriv->noise_level.noise[ODM_RF_PATH_A],
  7667. podmpriv->noise_level.noise[ODM_RF_PATH_B],
  7668. podmpriv->noise_level.noise_all);
  7669. #endif
  7670. }
  7671. break;
  7672. #endif/*#ifdef CONFIG_BACKGROUND_NOISE_MONITOR*/
  7673. case HAL_ODM_INITIAL_GAIN: {
  7674. u8 rx_gain = *((u8 *)(pValue1));
  7675. /*printk("rx_gain:%x\n",rx_gain);*/
  7676. if (rx_gain == 0xff) {/*restore rx gain*/
  7677. /*odm_write_dig(podmpriv,pDigTable->backup_ig_value);*/
  7678. odm_pause_dig(podmpriv, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_0, rx_gain);
  7679. } else {
  7680. /*pDigTable->backup_ig_value = pDigTable->cur_ig_value;*/
  7681. /*odm_write_dig(podmpriv,rx_gain);*/
  7682. odm_pause_dig(podmpriv, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_0, rx_gain);
  7683. }
  7684. }
  7685. break;
  7686. case HAL_ODM_FA_CNT_DUMP:
  7687. if (*((u8 *)pValue1))
  7688. podmpriv->debug_components |= (ODM_COMP_DIG | ODM_COMP_FA_CNT);
  7689. else
  7690. podmpriv->debug_components &= ~(ODM_COMP_DIG | ODM_COMP_FA_CNT);
  7691. break;
  7692. case HAL_ODM_DBG_FLAG:
  7693. odm_cmn_info_update(podmpriv, ODM_CMNINFO_DBG_COMP, *((u8Byte *)pValue1));
  7694. break;
  7695. case HAL_ODM_DBG_LEVEL:
  7696. odm_cmn_info_update(podmpriv, ODM_CMNINFO_DBG_LEVEL, *((u4Byte *)pValue1));
  7697. break;
  7698. case HAL_ODM_RX_INFO_DUMP: {
  7699. struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(podmpriv , PHYDM_FALSEALMCNT);
  7700. struct _dynamic_initial_gain_threshold_ *pDM_DigTable = &podmpriv->dm_dig_table;
  7701. void *sel;
  7702. sel = pValue1;
  7703. _RTW_PRINT_SEL(sel , "============ Rx Info dump ===================\n");
  7704. _RTW_PRINT_SEL(sel , "is_linked = %d, rssi_min = %d(%%), current_igi = 0x%x\n", podmpriv->is_linked, podmpriv->rssi_min, pDM_DigTable->cur_ig_value);
  7705. _RTW_PRINT_SEL(sel , "cnt_cck_fail = %d, cnt_ofdm_fail = %d, Total False Alarm = %d\n", false_alm_cnt->cnt_cck_fail, false_alm_cnt->cnt_ofdm_fail, false_alm_cnt->cnt_all);
  7706. if (podmpriv->is_linked) {
  7707. _RTW_PRINT_SEL(sel , "rx_rate = %s", HDATA_RATE(podmpriv->rx_rate));
  7708. _RTW_PRINT_SEL(sel , " RSSI_A = %d(%%), RSSI_B = %d(%%)\n", podmpriv->RSSI_A, podmpriv->RSSI_B);
  7709. #ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
  7710. rtw_dump_raw_rssi_info(Adapter, sel);
  7711. #endif
  7712. }
  7713. }
  7714. break;
  7715. case HAL_ODM_RX_Dframe_INFO: {
  7716. void *sel;
  7717. sel = pValue1;
  7718. /*_RTW_PRINT_SEL(sel , "HAL_ODM_RX_Dframe_INFO\n");*/
  7719. #ifdef DBG_RX_DFRAME_RAW_DATA
  7720. rtw_dump_rx_dframe_info(Adapter, sel);
  7721. #endif
  7722. }
  7723. break;
  7724. #ifdef CONFIG_AUTO_CHNL_SEL_NHM
  7725. case HAL_ODM_AUTO_CHNL_SEL: {
  7726. ACS_OP acs_op = *(ACS_OP *)pValue1;
  7727. rtw_phydm_func_set(Adapter, ODM_BB_NHM_CNT);
  7728. if (ACS_INIT == acs_op) {
  7729. #ifdef DBG_AUTO_CHNL_SEL_NHM
  7730. RTW_INFO("[ACS-"ADPT_FMT"] HAL_ODM_AUTO_CHNL_SEL: ACS_INIT\n", ADPT_ARG(Adapter));
  7731. #endif
  7732. odm_AutoChannelSelectInit(podmpriv);
  7733. } else if (ACS_RESET == acs_op) {
  7734. /* Reset statistics for auto channel selection mechanism.*/
  7735. #ifdef DBG_AUTO_CHNL_SEL_NHM
  7736. RTW_INFO("[ACS-"ADPT_FMT"] HAL_ODM_AUTO_CHNL_SEL: ACS_RESET\n", ADPT_ARG(Adapter));
  7737. #endif
  7738. odm_auto_channel_select_reset(podmpriv);
  7739. } else if (ACS_SELECT == acs_op) {
  7740. /* Collect NHM measurement result after current channel */
  7741. #ifdef DBG_AUTO_CHNL_SEL_NHM
  7742. RTW_INFO("[ACS-"ADPT_FMT"] HAL_ODM_AUTO_CHNL_SEL: ACS_SELECT, CH(%d)\n", ADPT_ARG(Adapter), rtw_get_acs_channel(Adapter));
  7743. #endif
  7744. odm_AutoChannelSelect(podmpriv, rtw_get_acs_channel(Adapter));
  7745. } else
  7746. RTW_INFO("[ACS-"ADPT_FMT"] HAL_ODM_AUTO_CHNL_SEL: Unexpected OP\n", ADPT_ARG(Adapter));
  7747. }
  7748. break;
  7749. #endif
  7750. #ifdef CONFIG_ANTENNA_DIVERSITY
  7751. case HAL_ODM_ANTDIV_SELECT: {
  7752. u8 antenna = (*(u8 *)pValue1);
  7753. /*switch antenna*/
  7754. odm_update_rx_idle_ant(&pHalData->odmpriv, antenna);
  7755. /*RTW_INFO("==> HAL_ODM_ANTDIV_SELECT, Ant_(%s)\n", (antenna == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");*/
  7756. }
  7757. break;
  7758. #endif
  7759. default:
  7760. break;
  7761. }
  7762. }
  7763. void GetHalODMVar(
  7764. PADAPTER Adapter,
  7765. HAL_ODM_VARIABLE eVariable,
  7766. PVOID pValue1,
  7767. PVOID pValue2)
  7768. {
  7769. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
  7770. struct PHY_DM_STRUCT *podmpriv = &pHalData->odmpriv;
  7771. switch (eVariable) {
  7772. #if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR)
  7773. case HAL_ODM_NOISE_MONITOR: {
  7774. u8 chan = *(u8 *)pValue1;
  7775. *(s16 *)pValue2 = pHalData->noise[chan];
  7776. #ifdef DBG_NOISE_MONITOR
  7777. RTW_INFO("### Noise monitor chan(%d)-noise:%d (dBm) ###\n",
  7778. chan, pHalData->noise[chan]);
  7779. #endif
  7780. }
  7781. break;
  7782. #endif/*#ifdef CONFIG_BACKGROUND_NOISE_MONITOR*/
  7783. case HAL_ODM_DBG_FLAG:
  7784. *((u8Byte *)pValue1) = podmpriv->debug_components;
  7785. break;
  7786. case HAL_ODM_DBG_LEVEL:
  7787. *((u4Byte *)pValue1) = podmpriv->debug_level;
  7788. break;
  7789. #ifdef CONFIG_AUTO_CHNL_SEL_NHM
  7790. case HAL_ODM_AUTO_CHNL_SEL: {
  7791. #ifdef DBG_AUTO_CHNL_SEL_NHM
  7792. RTW_INFO("[ACS-"ADPT_FMT"] HAL_ODM_AUTO_CHNL_SEL: GET_BEST_CHAN\n", ADPT_ARG(Adapter));
  7793. #endif
  7794. /* Retrieve better channel from NHM mechanism */
  7795. if (IsSupported24G(Adapter->registrypriv.wireless_mode))
  7796. *((u8 *)(pValue1)) = odm_get_auto_channel_select_result(podmpriv, BAND_ON_2_4G);
  7797. if (is_supported_5g(Adapter->registrypriv.wireless_mode))
  7798. *((u8 *)(pValue2)) = odm_get_auto_channel_select_result(podmpriv, BAND_ON_5G);
  7799. }
  7800. break;
  7801. #endif
  7802. #ifdef CONFIG_ANTENNA_DIVERSITY
  7803. case HAL_ODM_ANTDIV_SELECT: {
  7804. struct _FAST_ANTENNA_TRAINNING_ *pDM_FatTable = &podmpriv->dm_fat_table;
  7805. *((u8 *)pValue1) = pDM_FatTable->rx_idle_ant;
  7806. }
  7807. break;
  7808. #endif
  7809. case HAL_ODM_INITIAL_GAIN: {
  7810. struct _dynamic_initial_gain_threshold_ *pDM_DigTable = &podmpriv->dm_dig_table;
  7811. *((u8 *)pValue1) = pDM_DigTable->cur_ig_value;
  7812. }
  7813. break;
  7814. default:
  7815. break;
  7816. }
  7817. }
  7818. u32 rtw_phydm_ability_ops(_adapter *adapter, HAL_PHYDM_OPS ops, u32 ability)
  7819. {
  7820. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
  7821. struct PHY_DM_STRUCT *podmpriv = &pHalData->odmpriv;
  7822. u32 result = 0;
  7823. switch (ops) {
  7824. case HAL_PHYDM_DIS_ALL_FUNC:
  7825. podmpriv->support_ability = DYNAMIC_FUNC_DISABLE;
  7826. break;
  7827. case HAL_PHYDM_FUNC_SET:
  7828. podmpriv->support_ability |= ability;
  7829. break;
  7830. case HAL_PHYDM_FUNC_CLR:
  7831. podmpriv->support_ability &= ~(ability);
  7832. break;
  7833. case HAL_PHYDM_ABILITY_BK:
  7834. /* dm flag backup*/
  7835. podmpriv->bk_support_ability = podmpriv->support_ability;
  7836. break;
  7837. case HAL_PHYDM_ABILITY_RESTORE:
  7838. /* restore dm flag */
  7839. podmpriv->support_ability = podmpriv->bk_support_ability;
  7840. break;
  7841. case HAL_PHYDM_ABILITY_SET:
  7842. podmpriv->support_ability = ability;
  7843. break;
  7844. case HAL_PHYDM_ABILITY_GET:
  7845. result = podmpriv->support_ability;
  7846. break;
  7847. }
  7848. return result;
  7849. }
  7850. BOOLEAN
  7851. eqNByte(
  7852. u8 *str1,
  7853. u8 *str2,
  7854. u32 num
  7855. )
  7856. {
  7857. if (num == 0)
  7858. return _FALSE;
  7859. while (num > 0) {
  7860. num--;
  7861. if (str1[num] != str2[num])
  7862. return _FALSE;
  7863. }
  7864. return _TRUE;
  7865. }
  7866. /*
  7867. * Description:
  7868. * Translate a character to hex digit.
  7869. * */
  7870. u32
  7871. MapCharToHexDigit(
  7872. IN char chTmp
  7873. )
  7874. {
  7875. if (chTmp >= '0' && chTmp <= '9')
  7876. return chTmp - '0';
  7877. else if (chTmp >= 'a' && chTmp <= 'f')
  7878. return 10 + (chTmp - 'a');
  7879. else if (chTmp >= 'A' && chTmp <= 'F')
  7880. return 10 + (chTmp - 'A');
  7881. else
  7882. return 0;
  7883. }
  7884. /*
  7885. * Description:
  7886. * Parse hex number from the string pucStr.
  7887. * */
  7888. BOOLEAN
  7889. GetHexValueFromString(
  7890. IN char *szStr,
  7891. IN OUT u32 *pu4bVal,
  7892. IN OUT u32 *pu4bMove
  7893. )
  7894. {
  7895. char *szScan = szStr;
  7896. /* Check input parameter. */
  7897. if (szStr == NULL || pu4bVal == NULL || pu4bMove == NULL) {
  7898. RTW_INFO("GetHexValueFromString(): Invalid inpur argumetns! szStr: %p, pu4bVal: %p, pu4bMove: %p\n", szStr, pu4bVal, pu4bMove);
  7899. return _FALSE;
  7900. }
  7901. /* Initialize output. */
  7902. *pu4bMove = 0;
  7903. *pu4bVal = 0;
  7904. /* Skip leading space. */
  7905. while (*szScan != '\0' &&
  7906. (*szScan == ' ' || *szScan == '\t')) {
  7907. szScan++;
  7908. (*pu4bMove)++;
  7909. }
  7910. /* Skip leading '0x' or '0X'. */
  7911. if (*szScan == '0' && (*(szScan + 1) == 'x' || *(szScan + 1) == 'X')) {
  7912. szScan += 2;
  7913. (*pu4bMove) += 2;
  7914. }
  7915. /* Check if szScan is now pointer to a character for hex digit, */
  7916. /* if not, it means this is not a valid hex number. */
  7917. if (!IsHexDigit(*szScan))
  7918. return _FALSE;
  7919. /* Parse each digit. */
  7920. do {
  7921. (*pu4bVal) <<= 4;
  7922. *pu4bVal += MapCharToHexDigit(*szScan);
  7923. szScan++;
  7924. (*pu4bMove)++;
  7925. } while (IsHexDigit(*szScan));
  7926. return _TRUE;
  7927. }
  7928. BOOLEAN
  7929. GetFractionValueFromString(
  7930. IN char *szStr,
  7931. IN OUT u8 *pInteger,
  7932. IN OUT u8 *pFraction,
  7933. IN OUT u32 *pu4bMove
  7934. )
  7935. {
  7936. char *szScan = szStr;
  7937. /* Initialize output. */
  7938. *pu4bMove = 0;
  7939. *pInteger = 0;
  7940. *pFraction = 0;
  7941. /* Skip leading space. */
  7942. while (*szScan != '\0' && (*szScan == ' ' || *szScan == '\t')) {
  7943. ++szScan;
  7944. ++(*pu4bMove);
  7945. }
  7946. /* Parse each digit. */
  7947. do {
  7948. (*pInteger) *= 10;
  7949. *pInteger += (*szScan - '0');
  7950. ++szScan;
  7951. ++(*pu4bMove);
  7952. if (*szScan == '.') {
  7953. ++szScan;
  7954. ++(*pu4bMove);
  7955. if (*szScan < '0' || *szScan > '9')
  7956. return _FALSE;
  7957. else {
  7958. *pFraction = *szScan - '0';
  7959. ++szScan;
  7960. ++(*pu4bMove);
  7961. return _TRUE;
  7962. }
  7963. }
  7964. } while (*szScan >= '0' && *szScan <= '9');
  7965. return _TRUE;
  7966. }
  7967. /*
  7968. * Description:
  7969. * Return TRUE if szStr is comment out with leading " */ /* ".
  7970. * */
  7971. BOOLEAN
  7972. IsCommentString(
  7973. IN char *szStr
  7974. )
  7975. {
  7976. if (*szStr == '/' && *(szStr + 1) == '/')
  7977. return _TRUE;
  7978. else
  7979. return _FALSE;
  7980. }
  7981. BOOLEAN
  7982. GetU1ByteIntegerFromStringInDecimal(
  7983. IN char *Str,
  7984. IN OUT u8 *pInt
  7985. )
  7986. {
  7987. u16 i = 0;
  7988. *pInt = 0;
  7989. while (Str[i] != '\0') {
  7990. if (Str[i] >= '0' && Str[i] <= '9') {
  7991. *pInt *= 10;
  7992. *pInt += (Str[i] - '0');
  7993. } else
  7994. return _FALSE;
  7995. ++i;
  7996. }
  7997. return _TRUE;
  7998. }
  7999. /* <20121004, Kordan> For example,
  8000. * ParseQualifiedString(inString, 0, outString, '[', ']') gets "Kordan" from a string "Hello [Kordan]".
  8001. * If RightQualifier does not exist, it will hang on in the while loop */
  8002. BOOLEAN
  8003. ParseQualifiedString(
  8004. IN char *In,
  8005. IN OUT u32 *Start,
  8006. OUT char *Out,
  8007. IN char LeftQualifier,
  8008. IN char RightQualifier
  8009. )
  8010. {
  8011. u32 i = 0, j = 0;
  8012. char c = In[(*Start)++];
  8013. if (c != LeftQualifier)
  8014. return _FALSE;
  8015. i = (*Start);
  8016. while ((c = In[(*Start)++]) != RightQualifier)
  8017. ; /* find ']' */
  8018. j = (*Start) - 2;
  8019. strncpy((char *)Out, (const char *)(In + i), j - i + 1);
  8020. return _TRUE;
  8021. }
  8022. BOOLEAN
  8023. isAllSpaceOrTab(
  8024. u8 *data,
  8025. u8 size
  8026. )
  8027. {
  8028. u8 cnt = 0, NumOfSpaceAndTab = 0;
  8029. while (size > cnt) {
  8030. if (data[cnt] == ' ' || data[cnt] == '\t' || data[cnt] == '\0')
  8031. ++NumOfSpaceAndTab;
  8032. ++cnt;
  8033. }
  8034. return size == NumOfSpaceAndTab;
  8035. }
  8036. void rtw_hal_check_rxfifo_full(_adapter *adapter)
  8037. {
  8038. struct dvobj_priv *psdpriv = adapter->dvobj;
  8039. struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
  8040. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
  8041. struct registry_priv *regsty = &adapter->registrypriv;
  8042. int save_cnt = _FALSE;
  8043. if (regsty->check_hw_status == 1) {
  8044. /* switch counter to RX fifo */
  8045. if (IS_8188E(pHalData->version_id) ||
  8046. IS_8188F(pHalData->version_id) ||
  8047. IS_8812_SERIES(pHalData->version_id) ||
  8048. IS_8821_SERIES(pHalData->version_id) ||
  8049. IS_8723B_SERIES(pHalData->version_id) ||
  8050. IS_8192E(pHalData->version_id) ||
  8051. IS_8703B_SERIES(pHalData->version_id) ||
  8052. IS_8723D_SERIES(pHalData->version_id)) {
  8053. rtw_write8(adapter, REG_RXERR_RPT + 3, rtw_read8(adapter, REG_RXERR_RPT + 3) | 0xa0);
  8054. save_cnt = _TRUE;
  8055. } else {
  8056. /* todo: other chips */
  8057. }
  8058. if (save_cnt) {
  8059. pdbgpriv->dbg_rx_fifo_last_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow;
  8060. pdbgpriv->dbg_rx_fifo_curr_overflow = rtw_read16(adapter, REG_RXERR_RPT);
  8061. pdbgpriv->dbg_rx_fifo_diff_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow - pdbgpriv->dbg_rx_fifo_last_overflow;
  8062. } else {
  8063. /* special value to indicate no implementation */
  8064. pdbgpriv->dbg_rx_fifo_last_overflow = 1;
  8065. pdbgpriv->dbg_rx_fifo_curr_overflow = 1;
  8066. pdbgpriv->dbg_rx_fifo_diff_overflow = 1;
  8067. }
  8068. }
  8069. }
  8070. void linked_info_dump(_adapter *padapter, u8 benable)
  8071. {
  8072. struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
  8073. if (padapter->bLinkInfoDump == benable)
  8074. return;
  8075. RTW_INFO("%s %s\n", __FUNCTION__, (benable) ? "enable" : "disable");
  8076. if (benable) {
  8077. #ifdef CONFIG_LPS
  8078. pwrctrlpriv->org_power_mgnt = pwrctrlpriv->power_mgnt;/* keep org value */
  8079. rtw_pm_set_lps(padapter, PS_MODE_ACTIVE);
  8080. #endif
  8081. #ifdef CONFIG_IPS
  8082. pwrctrlpriv->ips_org_mode = pwrctrlpriv->ips_mode;/* keep org value */
  8083. rtw_pm_set_ips(padapter, IPS_NONE);
  8084. #endif
  8085. } else {
  8086. #ifdef CONFIG_IPS
  8087. rtw_pm_set_ips(padapter, pwrctrlpriv->ips_org_mode);
  8088. #endif /* CONFIG_IPS */
  8089. #ifdef CONFIG_LPS
  8090. rtw_pm_set_lps(padapter, pwrctrlpriv->org_power_mgnt);
  8091. #endif /* CONFIG_LPS */
  8092. }
  8093. padapter->bLinkInfoDump = benable ;
  8094. }
  8095. #ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
  8096. void rtw_get_raw_rssi_info(void *sel, _adapter *padapter)
  8097. {
  8098. u8 isCCKrate, rf_path;
  8099. PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
  8100. struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;
  8101. RTW_PRINT_SEL(sel, "RxRate = %s, PWDBALL = %d(%%), rx_pwr_all = %d(dBm)\n",
  8102. HDATA_RATE(psample_pkt_rssi->data_rate), psample_pkt_rssi->pwdball, psample_pkt_rssi->pwr_all);
  8103. isCCKrate = (psample_pkt_rssi->data_rate <= DESC_RATE11M) ? TRUE : FALSE;
  8104. if (isCCKrate)
  8105. psample_pkt_rssi->mimo_signal_strength[0] = psample_pkt_rssi->pwdball;
  8106. for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {
  8107. RTW_PRINT_SEL(sel, "RF_PATH_%d=>signal_strength:%d(%%),signal_quality:%d(%%)\n"
  8108. , rf_path, psample_pkt_rssi->mimo_signal_strength[rf_path], psample_pkt_rssi->mimo_signal_quality[rf_path]);
  8109. if (!isCCKrate) {
  8110. RTW_PRINT_SEL(sel, "\trx_ofdm_pwr:%d(dBm),rx_ofdm_snr:%d(dB)\n",
  8111. psample_pkt_rssi->ofdm_pwr[rf_path], psample_pkt_rssi->ofdm_snr[rf_path]);
  8112. }
  8113. }
  8114. }
  8115. void rtw_dump_raw_rssi_info(_adapter *padapter, void *sel)
  8116. {
  8117. u8 isCCKrate, rf_path;
  8118. PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
  8119. struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;
  8120. _RTW_PRINT_SEL(sel, "============ RAW Rx Info dump ===================\n");
  8121. _RTW_PRINT_SEL(sel, "RxRate = %s, PWDBALL = %d(%%), rx_pwr_all = %d(dBm)\n", HDATA_RATE(psample_pkt_rssi->data_rate), psample_pkt_rssi->pwdball, psample_pkt_rssi->pwr_all);
  8122. isCCKrate = (psample_pkt_rssi->data_rate <= DESC_RATE11M) ? TRUE : FALSE;
  8123. if (isCCKrate)
  8124. psample_pkt_rssi->mimo_signal_strength[0] = psample_pkt_rssi->pwdball;
  8125. for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {
  8126. _RTW_PRINT_SEL(sel , "RF_PATH_%d=>signal_strength:%d(%%),signal_quality:%d(%%)"
  8127. , rf_path, psample_pkt_rssi->mimo_signal_strength[rf_path], psample_pkt_rssi->mimo_signal_quality[rf_path]);
  8128. if (!isCCKrate)
  8129. _RTW_PRINT_SEL(sel , ",rx_ofdm_pwr:%d(dBm),rx_ofdm_snr:%d(dB)\n", psample_pkt_rssi->ofdm_pwr[rf_path], psample_pkt_rssi->ofdm_snr[rf_path]);
  8130. else
  8131. _RTW_PRINT_SEL(sel , "\n");
  8132. }
  8133. }
  8134. #endif
  8135. #ifdef DBG_RX_DFRAME_RAW_DATA
  8136. void rtw_dump_rx_dframe_info(_adapter *padapter, void *sel)
  8137. {
  8138. _irqL irqL;
  8139. u8 isCCKrate, rf_path;
  8140. struct recv_priv *precvpriv = &(padapter->recvpriv);
  8141. PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
  8142. struct sta_priv *pstapriv = &padapter->stapriv;
  8143. struct sta_info *psta;
  8144. struct sta_recv_dframe_info *psta_dframe_info;
  8145. int i;
  8146. _list *plist, *phead;
  8147. char *BW;
  8148. u8 bc_addr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
  8149. u8 null_addr[6] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
  8150. if (precvpriv->store_law_data_flag) {
  8151. _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
  8152. for (i = 0; i < NUM_STA; i++) {
  8153. phead = &(pstapriv->sta_hash[i]);
  8154. plist = get_next(phead);
  8155. while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
  8156. psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
  8157. plist = get_next(plist);
  8158. if (psta) {
  8159. psta_dframe_info = &psta->sta_dframe_info;
  8160. if ((_rtw_memcmp(psta->hwaddr, bc_addr, 6) != _TRUE)
  8161. && (_rtw_memcmp(psta->hwaddr, null_addr, 6) != _TRUE)
  8162. && (_rtw_memcmp(psta->hwaddr, adapter_mac_addr(padapter), 6) != _TRUE)) {
  8163. isCCKrate = (psta_dframe_info->sta_data_rate <= DESC_RATE11M) ? TRUE : FALSE;
  8164. switch (psta_dframe_info->sta_bw_mode) {
  8165. case CHANNEL_WIDTH_20:
  8166. BW = "20M";
  8167. break;
  8168. case CHANNEL_WIDTH_40:
  8169. BW = "40M";
  8170. break;
  8171. case CHANNEL_WIDTH_80:
  8172. BW = "80M";
  8173. break;
  8174. case CHANNEL_WIDTH_160:
  8175. BW = "160M";
  8176. break;
  8177. default:
  8178. BW = "";
  8179. break;
  8180. }
  8181. RTW_PRINT_SEL(sel, "==============================\n");
  8182. _RTW_PRINT_SEL(sel, "macaddr =" MAC_FMT "\n", MAC_ARG(psta->hwaddr));
  8183. _RTW_PRINT_SEL(sel, "BW=%s, sgi =%d\n", BW, psta_dframe_info->sta_sgi);
  8184. _RTW_PRINT_SEL(sel, "Rx_Data_Rate = %s\n", HDATA_RATE(psta_dframe_info->sta_data_rate));
  8185. for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {
  8186. if (!isCCKrate) {
  8187. _RTW_PRINT_SEL(sel , "RF_PATH_%d RSSI:%d(dBm)", rf_path, psta_dframe_info->sta_RxPwr[rf_path]);
  8188. _RTW_PRINT_SEL(sel , ",rx_ofdm_snr:%d(dB)\n", psta_dframe_info->sta_ofdm_snr[rf_path]);
  8189. } else
  8190. _RTW_PRINT_SEL(sel , "RF_PATH_%d RSSI:%d(dBm)\n", rf_path, (psta_dframe_info->sta_mimo_signal_strength[rf_path]) - 100);
  8191. }
  8192. }
  8193. }
  8194. }
  8195. }
  8196. _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
  8197. }
  8198. }
  8199. #endif
  8200. void rtw_store_phy_info(_adapter *padapter, union recv_frame *prframe)
  8201. {
  8202. u8 isCCKrate, rf_path , dframe_type;
  8203. u8 *ptr;
  8204. u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
  8205. #ifdef DBG_RX_DFRAME_RAW_DATA
  8206. struct sta_recv_dframe_info *psta_dframe_info;
  8207. #endif
  8208. struct recv_priv *precvpriv = &(padapter->recvpriv);
  8209. PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
  8210. struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
  8211. struct sta_info *psta = prframe->u.hdr.psta;
  8212. struct _odm_phy_status_info_ *p_phy_info = (struct _odm_phy_status_info_ *)(&pattrib->phy_info);
  8213. struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;
  8214. psample_pkt_rssi->data_rate = pattrib->data_rate;
  8215. ptr = prframe->u.hdr.rx_data;
  8216. dframe_type = GetFrameType(ptr);
  8217. /*RTW_INFO("=>%s\n", __FUNCTION__);*/
  8218. if (precvpriv->store_law_data_flag) {
  8219. isCCKrate = (pattrib->data_rate <= DESC_RATE11M) ? TRUE : FALSE;
  8220. psample_pkt_rssi->pwdball = p_phy_info->rx_pwdb_all;
  8221. psample_pkt_rssi->pwr_all = p_phy_info->recv_signal_power;
  8222. for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {
  8223. psample_pkt_rssi->mimo_signal_strength[rf_path] = p_phy_info->rx_mimo_signal_strength[rf_path];
  8224. psample_pkt_rssi->mimo_signal_quality[rf_path] = p_phy_info->rx_mimo_signal_quality[rf_path];
  8225. if (!isCCKrate) {
  8226. psample_pkt_rssi->ofdm_pwr[rf_path] = p_phy_info->rx_pwr[rf_path];
  8227. psample_pkt_rssi->ofdm_snr[rf_path] = p_phy_info->rx_snr[rf_path];
  8228. }
  8229. }
  8230. #ifdef DBG_RX_DFRAME_RAW_DATA
  8231. if ((dframe_type == WIFI_DATA_TYPE) || (dframe_type == WIFI_QOS_DATA_TYPE) || (padapter->registrypriv.mp_mode == 1)) {
  8232. /*RTW_INFO("=>%s WIFI_DATA_TYPE or WIFI_QOS_DATA_TYPE\n", __FUNCTION__);*/
  8233. if (psta) {
  8234. psta_dframe_info = &psta->sta_dframe_info;
  8235. /*RTW_INFO("=>%s psta->hwaddr="MAC_FMT" !\n", __FUNCTION__, MAC_ARG(psta->hwaddr));*/
  8236. if ((_rtw_memcmp(psta->hwaddr, bc_addr, ETH_ALEN) != _TRUE) || (padapter->registrypriv.mp_mode == 1)) {
  8237. psta_dframe_info->sta_data_rate = pattrib->data_rate;
  8238. psta_dframe_info->sta_sgi = pattrib->sgi;
  8239. psta_dframe_info->sta_bw_mode = pattrib->bw;
  8240. for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {
  8241. psta_dframe_info->sta_mimo_signal_strength[rf_path] = (p_phy_info->rx_mimo_signal_strength[rf_path]);/*Percentage to dbm*/
  8242. if (!isCCKrate) {
  8243. psta_dframe_info->sta_ofdm_snr[rf_path] = p_phy_info->rx_snr[rf_path];
  8244. psta_dframe_info->sta_RxPwr[rf_path] = p_phy_info->rx_pwr[rf_path];
  8245. }
  8246. }
  8247. }
  8248. }
  8249. }
  8250. #endif
  8251. }
  8252. }
  8253. int check_phy_efuse_tx_power_info_valid(PADAPTER padapter)
  8254. {
  8255. PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
  8256. u8 *pContent = pHalData->efuse_eeprom_data;
  8257. int index = 0;
  8258. u16 tx_index_offset = 0x0000;
  8259. switch (rtw_get_chip_type(padapter)) {
  8260. case RTL8723B:
  8261. tx_index_offset = EEPROM_TX_PWR_INX_8723B;
  8262. break;
  8263. case RTL8703B:
  8264. tx_index_offset = EEPROM_TX_PWR_INX_8703B;
  8265. break;
  8266. case RTL8723D:
  8267. tx_index_offset = EEPROM_TX_PWR_INX_8723D;
  8268. break;
  8269. case RTL8188E:
  8270. tx_index_offset = EEPROM_TX_PWR_INX_88E;
  8271. break;
  8272. case RTL8188F:
  8273. tx_index_offset = EEPROM_TX_PWR_INX_8188F;
  8274. break;
  8275. case RTL8192E:
  8276. tx_index_offset = EEPROM_TX_PWR_INX_8192E;
  8277. break;
  8278. case RTL8821:
  8279. tx_index_offset = EEPROM_TX_PWR_INX_8821;
  8280. break;
  8281. case RTL8812:
  8282. tx_index_offset = EEPROM_TX_PWR_INX_8812;
  8283. break;
  8284. case RTL8814A:
  8285. tx_index_offset = EEPROM_TX_PWR_INX_8814;
  8286. break;
  8287. case RTL8822B:
  8288. tx_index_offset = EEPROM_TX_PWR_INX_8822B;
  8289. break;
  8290. case RTL8821C:
  8291. tx_index_offset = EEPROM_TX_PWR_INX_8821C;
  8292. break;
  8293. default:
  8294. tx_index_offset = 0x0010;
  8295. break;
  8296. }
  8297. /* TODO: chacking length by ICs */
  8298. for (index = 0 ; index < 11 ; index++) {
  8299. if (pContent[tx_index_offset + index] == 0xFF)
  8300. return _FALSE;
  8301. }
  8302. return _TRUE;
  8303. }
  8304. int hal_efuse_macaddr_offset(_adapter *adapter)
  8305. {
  8306. u8 interface_type = 0;
  8307. int addr_offset = -1;
  8308. interface_type = rtw_get_intf_type(adapter);
  8309. switch (rtw_get_chip_type(adapter)) {
  8310. #ifdef CONFIG_RTL8723B
  8311. case RTL8723B:
  8312. if (interface_type == RTW_USB)
  8313. addr_offset = EEPROM_MAC_ADDR_8723BU;
  8314. else if (interface_type == RTW_SDIO)
  8315. addr_offset = EEPROM_MAC_ADDR_8723BS;
  8316. else if (interface_type == RTW_PCIE)
  8317. addr_offset = EEPROM_MAC_ADDR_8723BE;
  8318. break;
  8319. #endif
  8320. #ifdef CONFIG_RTL8703B
  8321. case RTL8703B:
  8322. if (interface_type == RTW_USB)
  8323. addr_offset = EEPROM_MAC_ADDR_8703BU;
  8324. else if (interface_type == RTW_SDIO)
  8325. addr_offset = EEPROM_MAC_ADDR_8703BS;
  8326. break;
  8327. #endif
  8328. #ifdef CONFIG_RTL8723D
  8329. case RTL8723D:
  8330. if (interface_type == RTW_USB)
  8331. addr_offset = EEPROM_MAC_ADDR_8723DU;
  8332. else if (interface_type == RTW_SDIO)
  8333. addr_offset = EEPROM_MAC_ADDR_8723DS;
  8334. else if (interface_type == RTW_PCIE)
  8335. addr_offset = EEPROM_MAC_ADDR_8723DE;
  8336. break;
  8337. #endif
  8338. #ifdef CONFIG_RTL8188E
  8339. case RTL8188E:
  8340. if (interface_type == RTW_USB)
  8341. addr_offset = EEPROM_MAC_ADDR_88EU;
  8342. else if (interface_type == RTW_SDIO)
  8343. addr_offset = EEPROM_MAC_ADDR_88ES;
  8344. else if (interface_type == RTW_PCIE)
  8345. addr_offset = EEPROM_MAC_ADDR_88EE;
  8346. break;
  8347. #endif
  8348. #ifdef CONFIG_RTL8188F
  8349. case RTL8188F:
  8350. if (interface_type == RTW_USB)
  8351. addr_offset = EEPROM_MAC_ADDR_8188FU;
  8352. else if (interface_type == RTW_SDIO)
  8353. addr_offset = EEPROM_MAC_ADDR_8188FS;
  8354. break;
  8355. #endif
  8356. #ifdef CONFIG_RTL8812A
  8357. case RTL8812:
  8358. if (interface_type == RTW_USB)
  8359. addr_offset = EEPROM_MAC_ADDR_8812AU;
  8360. else if (interface_type == RTW_PCIE)
  8361. addr_offset = EEPROM_MAC_ADDR_8812AE;
  8362. break;
  8363. #endif
  8364. #ifdef CONFIG_RTL8821A
  8365. case RTL8821:
  8366. if (interface_type == RTW_USB)
  8367. addr_offset = EEPROM_MAC_ADDR_8821AU;
  8368. else if (interface_type == RTW_SDIO)
  8369. addr_offset = EEPROM_MAC_ADDR_8821AS;
  8370. else if (interface_type == RTW_PCIE)
  8371. addr_offset = EEPROM_MAC_ADDR_8821AE;
  8372. break;
  8373. #endif
  8374. #ifdef CONFIG_RTL8192E
  8375. case RTL8192E:
  8376. if (interface_type == RTW_USB)
  8377. addr_offset = EEPROM_MAC_ADDR_8192EU;
  8378. else if (interface_type == RTW_SDIO)
  8379. addr_offset = EEPROM_MAC_ADDR_8192ES;
  8380. else if (interface_type == RTW_PCIE)
  8381. addr_offset = EEPROM_MAC_ADDR_8192EE;
  8382. break;
  8383. #endif
  8384. #ifdef CONFIG_RTL8814A
  8385. case RTL8814A:
  8386. if (interface_type == RTW_USB)
  8387. addr_offset = EEPROM_MAC_ADDR_8814AU;
  8388. else if (interface_type == RTW_PCIE)
  8389. addr_offset = EEPROM_MAC_ADDR_8814AE;
  8390. break;
  8391. #endif
  8392. #ifdef CONFIG_RTL8822B
  8393. case RTL8822B:
  8394. if (interface_type == RTW_USB)
  8395. addr_offset = EEPROM_MAC_ADDR_8822BU;
  8396. else if (interface_type == RTW_SDIO)
  8397. addr_offset = EEPROM_MAC_ADDR_8822BS;
  8398. else if (interface_type == RTW_PCIE)
  8399. addr_offset = EEPROM_MAC_ADDR_8822BE;
  8400. break;
  8401. #endif /* CONFIG_RTL8822B */
  8402. #ifdef CONFIG_RTL8821C
  8403. case RTL8821C:
  8404. if (interface_type == RTW_USB)
  8405. addr_offset = EEPROM_MAC_ADDR_8821CU;
  8406. else if (interface_type == RTW_SDIO)
  8407. addr_offset = EEPROM_MAC_ADDR_8821CS;
  8408. else if (interface_type == RTW_PCIE)
  8409. addr_offset = EEPROM_MAC_ADDR_8821CE;
  8410. break;
  8411. #endif /* CONFIG_RTL8821C */
  8412. }
  8413. if (addr_offset == -1) {
  8414. RTW_ERR("%s: unknown combination - chip_type:%u, interface:%u\n"
  8415. , __func__, rtw_get_chip_type(adapter), rtw_get_intf_type(adapter));
  8416. }
  8417. return addr_offset;
  8418. }
  8419. int Hal_GetPhyEfuseMACAddr(PADAPTER padapter, u8 *mac_addr)
  8420. {
  8421. int ret = _FAIL;
  8422. int addr_offset;
  8423. addr_offset = hal_efuse_macaddr_offset(padapter);
  8424. if (addr_offset == -1)
  8425. goto exit;
  8426. ret = rtw_efuse_map_read(padapter, addr_offset, ETH_ALEN, mac_addr);
  8427. exit:
  8428. return ret;
  8429. }
  8430. void rtw_dump_cur_efuse(PADAPTER padapter)
  8431. {
  8432. int i =0;
  8433. int mapsize =0;
  8434. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
  8435. EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&mapsize, _FALSE);
  8436. if (mapsize <= 0 || mapsize > EEPROM_MAX_SIZE) {
  8437. RTW_ERR("wrong map size %d\n", mapsize);
  8438. return;
  8439. }
  8440. if (hal_data->efuse_file_status == EFUSE_FILE_LOADED)
  8441. RTW_INFO("EFUSE FILE\n");
  8442. else
  8443. RTW_INFO("HW EFUSE\n");
  8444. #ifdef CONFIG_RTW_DEBUG
  8445. for (i = 0; i < mapsize; i++) {
  8446. if (i % 16 == 0)
  8447. RTW_PRINT_SEL(RTW_DBGDUMP, "0x%03x: ", i);
  8448. _RTW_PRINT_SEL(RTW_DBGDUMP, "%02X%s"
  8449. , hal_data->efuse_eeprom_data[i]
  8450. , ((i + 1) % 16 == 0) ? "\n" : (((i + 1) % 8 == 0) ? " " : " ")
  8451. );
  8452. }
  8453. _RTW_PRINT_SEL(RTW_DBGDUMP, "\n");
  8454. #endif
  8455. }
  8456. #ifdef CONFIG_EFUSE_CONFIG_FILE
  8457. u32 Hal_readPGDataFromConfigFile(PADAPTER padapter)
  8458. {
  8459. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
  8460. u32 ret = _FALSE;
  8461. u32 maplen = 0;
  8462. EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&maplen, _FALSE);
  8463. if (maplen < 256 || maplen > EEPROM_MAX_SIZE) {
  8464. RTW_ERR("eFuse length error :%d\n", maplen);
  8465. return _FALSE;
  8466. }
  8467. ret = rtw_read_efuse_from_file(EFUSE_MAP_PATH, hal_data->efuse_eeprom_data, maplen);
  8468. hal_data->efuse_file_status = ((ret == _FAIL) ? EFUSE_FILE_FAILED : EFUSE_FILE_LOADED);
  8469. if (hal_data->efuse_file_status == EFUSE_FILE_LOADED)
  8470. rtw_dump_cur_efuse(padapter);
  8471. return ret;
  8472. }
  8473. u32 Hal_ReadMACAddrFromFile(PADAPTER padapter, u8 *mac_addr)
  8474. {
  8475. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
  8476. u32 ret = _FAIL;
  8477. if (rtw_read_macaddr_from_file(WIFIMAC_PATH, mac_addr) == _SUCCESS
  8478. && rtw_check_invalid_mac_address(mac_addr, _TRUE) == _FALSE
  8479. ) {
  8480. hal_data->macaddr_file_status = MACADDR_FILE_LOADED;
  8481. ret = _SUCCESS;
  8482. } else
  8483. hal_data->macaddr_file_status = MACADDR_FILE_FAILED;
  8484. return ret;
  8485. }
  8486. #endif /* CONFIG_EFUSE_CONFIG_FILE */
  8487. int hal_config_macaddr(_adapter *adapter, bool autoload_fail)
  8488. {
  8489. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
  8490. u8 addr[ETH_ALEN];
  8491. int addr_offset = hal_efuse_macaddr_offset(adapter);
  8492. u8 *hw_addr = NULL;
  8493. int ret = _SUCCESS;
  8494. if (autoload_fail)
  8495. goto bypass_hw_pg;
  8496. if (addr_offset != -1)
  8497. hw_addr = &hal_data->efuse_eeprom_data[addr_offset];
  8498. #ifdef CONFIG_EFUSE_CONFIG_FILE
  8499. /* if the hw_addr is written by efuse file, set to NULL */
  8500. if (hal_data->efuse_file_status == EFUSE_FILE_LOADED)
  8501. hw_addr = NULL;
  8502. #endif
  8503. if (!hw_addr) {
  8504. /* try getting hw pg data */
  8505. if (Hal_GetPhyEfuseMACAddr(adapter, addr) == _SUCCESS)
  8506. hw_addr = addr;
  8507. }
  8508. /* check hw pg data */
  8509. if (hw_addr && rtw_check_invalid_mac_address(hw_addr, _TRUE) == _FALSE) {
  8510. _rtw_memcpy(hal_data->EEPROMMACAddr, hw_addr, ETH_ALEN);
  8511. goto exit;
  8512. }
  8513. bypass_hw_pg:
  8514. #ifdef CONFIG_EFUSE_CONFIG_FILE
  8515. /* check wifi mac file */
  8516. if (Hal_ReadMACAddrFromFile(adapter, addr) == _SUCCESS) {
  8517. _rtw_memcpy(hal_data->EEPROMMACAddr, addr, ETH_ALEN);
  8518. goto exit;
  8519. }
  8520. #endif
  8521. _rtw_memset(hal_data->EEPROMMACAddr, 0, ETH_ALEN);
  8522. ret = _FAIL;
  8523. exit:
  8524. return ret;
  8525. }
  8526. #ifdef CONFIG_RF_POWER_TRIM
  8527. u32 Array_kfreemap[] = {
  8528. 0x08, 0xe,
  8529. 0x06, 0xc,
  8530. 0x04, 0xa,
  8531. 0x02, 0x8,
  8532. 0x00, 0x6,
  8533. 0x03, 0x4,
  8534. 0x05, 0x2,
  8535. 0x07, 0x0,
  8536. 0x09, 0x0,
  8537. 0x0c, 0x0,
  8538. };
  8539. void rtw_bb_rf_gain_offset(_adapter *padapter)
  8540. {
  8541. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
  8542. struct registry_priv *registry_par = &padapter->registrypriv;
  8543. struct kfree_data_t *kfree_data = &pHalData->kfree_data;
  8544. u8 value = pHalData->EEPROMRFGainOffset;
  8545. u8 tmp = 0x3e;
  8546. u32 res, i = 0;
  8547. u4Byte ArrayLen = sizeof(Array_kfreemap) / sizeof(u32);
  8548. pu4Byte Array = Array_kfreemap;
  8549. u4Byte v1 = 0, v2 = 0, GainValue = 0, target = 0;
  8550. if (registry_par->RegPwrTrimEnable == 2) {
  8551. RTW_INFO("Registry kfree default force disable.\n");
  8552. return;
  8553. }
  8554. #if defined(CONFIG_RTL8723B)
  8555. if (value & BIT4 || (registry_par->RegPwrTrimEnable == 1)) {
  8556. RTW_INFO("Offset RF Gain.\n");
  8557. RTW_INFO("Offset RF Gain. pHalData->EEPROMRFGainVal=0x%x\n", pHalData->EEPROMRFGainVal);
  8558. if (pHalData->EEPROMRFGainVal != 0xff) {
  8559. if (pHalData->ant_path == ODM_RF_PATH_A)
  8560. GainValue = (pHalData->EEPROMRFGainVal & 0x0f);
  8561. else
  8562. GainValue = (pHalData->EEPROMRFGainVal & 0xf0) >> 4;
  8563. RTW_INFO("Ant PATH_%d GainValue Offset = 0x%x\n", (pHalData->ant_path == ODM_RF_PATH_A) ? (ODM_RF_PATH_A) : (ODM_RF_PATH_B), GainValue);
  8564. for (i = 0; i < ArrayLen; i += 2) {
  8565. /* RTW_INFO("ArrayLen in =%d ,Array 1 =0x%x ,Array2 =0x%x\n",i,Array[i],Array[i]+1); */
  8566. v1 = Array[i];
  8567. v2 = Array[i + 1];
  8568. if (v1 == GainValue) {
  8569. RTW_INFO("Offset RF Gain. got v1 =0x%x ,v2 =0x%x\n", v1, v2);
  8570. target = v2;
  8571. break;
  8572. }
  8573. }
  8574. RTW_INFO("pHalData->EEPROMRFGainVal=0x%x ,Gain offset Target Value=0x%x\n", pHalData->EEPROMRFGainVal, target);
  8575. res = rtw_hal_read_rfreg(padapter, RF_PATH_A, 0x7f, 0xffffffff);
  8576. RTW_INFO("Offset RF Gain. before reg 0x7f=0x%08x\n", res);
  8577. phy_set_rf_reg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET, BIT18 | BIT17 | BIT16 | BIT15, target);
  8578. res = rtw_hal_read_rfreg(padapter, RF_PATH_A, 0x7f, 0xffffffff);
  8579. RTW_INFO("Offset RF Gain. After reg 0x7f=0x%08x\n", res);
  8580. } else
  8581. RTW_INFO("Offset RF Gain. pHalData->EEPROMRFGainVal=0x%x != 0xff, didn't run Kfree\n", pHalData->EEPROMRFGainVal);
  8582. } else
  8583. RTW_INFO("Using the default RF gain.\n");
  8584. #elif defined(CONFIG_RTL8188E)
  8585. if (value & BIT4 || (registry_par->RegPwrTrimEnable == 1)) {
  8586. RTW_INFO("8188ES Offset RF Gain.\n");
  8587. RTW_INFO("8188ES Offset RF Gain. EEPROMRFGainVal=0x%x\n",
  8588. pHalData->EEPROMRFGainVal);
  8589. if (pHalData->EEPROMRFGainVal != 0xff) {
  8590. res = rtw_hal_read_rfreg(padapter, RF_PATH_A,
  8591. REG_RF_BB_GAIN_OFFSET, 0xffffffff);
  8592. RTW_INFO("Offset RF Gain. reg 0x55=0x%x\n", res);
  8593. res &= 0xfff87fff;
  8594. res |= (pHalData->EEPROMRFGainVal & 0x0f) << 15;
  8595. RTW_INFO("Offset RF Gain. res=0x%x\n", res);
  8596. rtw_hal_write_rfreg(padapter, RF_PATH_A,
  8597. REG_RF_BB_GAIN_OFFSET,
  8598. RF_GAIN_OFFSET_MASK, res);
  8599. } else {
  8600. RTW_INFO("Offset RF Gain. EEPROMRFGainVal=0x%x == 0xff, didn't run Kfree\n",
  8601. pHalData->EEPROMRFGainVal);
  8602. }
  8603. } else
  8604. RTW_INFO("Using the default RF gain.\n");
  8605. #else
  8606. /* TODO: call this when channel switch */
  8607. if (kfree_data->flag & KFREE_FLAG_ON)
  8608. rtw_rf_apply_tx_gain_offset(padapter, 6); /* input ch6 to select BB_GAIN_2G */
  8609. #endif
  8610. }
  8611. #endif /*CONFIG_RF_POWER_TRIM */
  8612. bool kfree_data_is_bb_gain_empty(struct kfree_data_t *data)
  8613. {
  8614. #ifdef CONFIG_RF_POWER_TRIM
  8615. int i, j;
  8616. for (i = 0; i < BB_GAIN_NUM; i++)
  8617. for (j = 0; j < RF_PATH_MAX; j++)
  8618. if (data->bb_gain[i][j] != 0)
  8619. return 0;
  8620. #endif
  8621. return 1;
  8622. }
  8623. #ifdef CONFIG_USB_RX_AGGREGATION
  8624. void rtw_set_usb_agg_by_mode_normal(_adapter *padapter, u8 cur_wireless_mode)
  8625. {
  8626. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
  8627. if (cur_wireless_mode < WIRELESS_11_24N
  8628. && cur_wireless_mode > 0) { /* ABG mode */
  8629. #ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
  8630. u32 remainder = 0;
  8631. u8 quotient = 0;
  8632. remainder = MAX_RECVBUF_SZ % (4 * 1024);
  8633. quotient = (u8)(MAX_RECVBUF_SZ >> 12);
  8634. if (quotient > 5) {
  8635. pHalData->rxagg_usb_size = 0x6;
  8636. pHalData->rxagg_usb_timeout = 0x10;
  8637. } else {
  8638. if (remainder >= 2048) {
  8639. pHalData->rxagg_usb_size = quotient;
  8640. pHalData->rxagg_usb_timeout = 0x10;
  8641. } else {
  8642. pHalData->rxagg_usb_size = (quotient - 1);
  8643. pHalData->rxagg_usb_timeout = 0x10;
  8644. }
  8645. }
  8646. #else /* !CONFIG_PREALLOC_RX_SKB_BUFFER */
  8647. if (0x6 != pHalData->rxagg_usb_size || 0x10 != pHalData->rxagg_usb_timeout) {
  8648. pHalData->rxagg_usb_size = 0x6;
  8649. pHalData->rxagg_usb_timeout = 0x10;
  8650. rtw_write16(padapter, REG_RXDMA_AGG_PG_TH,
  8651. pHalData->rxagg_usb_size | (pHalData->rxagg_usb_timeout << 8));
  8652. }
  8653. #endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */
  8654. } else if (cur_wireless_mode >= WIRELESS_11_24N
  8655. && cur_wireless_mode <= WIRELESS_MODE_MAX) { /* N AC mode */
  8656. #ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
  8657. u32 remainder = 0;
  8658. u8 quotient = 0;
  8659. remainder = MAX_RECVBUF_SZ % (4 * 1024);
  8660. quotient = (u8)(MAX_RECVBUF_SZ >> 12);
  8661. if (quotient > 5) {
  8662. pHalData->rxagg_usb_size = 0x5;
  8663. pHalData->rxagg_usb_timeout = 0x20;
  8664. } else {
  8665. if (remainder >= 2048) {
  8666. pHalData->rxagg_usb_size = quotient;
  8667. pHalData->rxagg_usb_timeout = 0x10;
  8668. } else {
  8669. pHalData->rxagg_usb_size = (quotient - 1);
  8670. pHalData->rxagg_usb_timeout = 0x10;
  8671. }
  8672. }
  8673. #else /* !CONFIG_PREALLOC_RX_SKB_BUFFER */
  8674. if ((0x5 != pHalData->rxagg_usb_size) || (0x20 != pHalData->rxagg_usb_timeout)) {
  8675. pHalData->rxagg_usb_size = 0x5;
  8676. pHalData->rxagg_usb_timeout = 0x20;
  8677. rtw_write16(padapter, REG_RXDMA_AGG_PG_TH,
  8678. pHalData->rxagg_usb_size | (pHalData->rxagg_usb_timeout << 8));
  8679. }
  8680. #endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */
  8681. } else {
  8682. /* RTW_INFO("%s: Unknow wireless mode(0x%x)\n",__func__,padapter->mlmeextpriv.cur_wireless_mode); */
  8683. }
  8684. }
  8685. void rtw_set_usb_agg_by_mode_customer(_adapter *padapter, u8 cur_wireless_mode, u8 UsbDmaSize, u8 Legacy_UsbDmaSize)
  8686. {
  8687. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
  8688. if (cur_wireless_mode < WIRELESS_11_24N
  8689. && cur_wireless_mode > 0) { /* ABG mode */
  8690. if (Legacy_UsbDmaSize != pHalData->rxagg_usb_size
  8691. || 0x10 != pHalData->rxagg_usb_timeout) {
  8692. pHalData->rxagg_usb_size = Legacy_UsbDmaSize;
  8693. pHalData->rxagg_usb_timeout = 0x10;
  8694. rtw_write16(padapter, REG_RXDMA_AGG_PG_TH,
  8695. pHalData->rxagg_usb_size | (pHalData->rxagg_usb_timeout << 8));
  8696. }
  8697. } else if (cur_wireless_mode >= WIRELESS_11_24N
  8698. && cur_wireless_mode <= WIRELESS_MODE_MAX) { /* N AC mode */
  8699. if (UsbDmaSize != pHalData->rxagg_usb_size
  8700. || 0x20 != pHalData->rxagg_usb_timeout) {
  8701. pHalData->rxagg_usb_size = UsbDmaSize;
  8702. pHalData->rxagg_usb_timeout = 0x20;
  8703. rtw_write16(padapter, REG_RXDMA_AGG_PG_TH,
  8704. pHalData->rxagg_usb_size | (pHalData->rxagg_usb_timeout << 8));
  8705. }
  8706. } else {
  8707. /* RTW_INFO("%s: Unknown wireless mode(0x%x)\n",__func__,padapter->mlmeextpriv.cur_wireless_mode); */
  8708. }
  8709. }
  8710. void rtw_set_usb_agg_by_mode(_adapter *padapter, u8 cur_wireless_mode)
  8711. {
  8712. #ifdef CONFIG_PLATFORM_NOVATEK_NT72668
  8713. rtw_set_usb_agg_by_mode_customer(padapter, cur_wireless_mode, 0x3, 0x3);
  8714. return;
  8715. #endif /* CONFIG_PLATFORM_NOVATEK_NT72668 */
  8716. rtw_set_usb_agg_by_mode_normal(padapter, cur_wireless_mode);
  8717. }
  8718. #endif /* CONFIG_USB_RX_AGGREGATION */
  8719. /* To avoid RX affect TX throughput */
  8720. void dm_DynamicUsbTxAgg(_adapter *padapter, u8 from_timer)
  8721. {
  8722. struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
  8723. struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
  8724. struct registry_priv *registry_par = &padapter->registrypriv;
  8725. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
  8726. u8 cur_wireless_mode = WIRELESS_INVALID;
  8727. #ifdef CONFIG_USB_RX_AGGREGATION
  8728. if (!registry_par->dynamic_agg_enable)
  8729. return;
  8730. #ifdef RTW_HALMAC
  8731. if (IS_HARDWARE_TYPE_8822BU(padapter) || IS_HARDWARE_TYPE_8821CU(padapter))
  8732. rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, NULL);
  8733. #else /* !RTW_HALMAC */
  8734. if (IS_HARDWARE_TYPE_8821U(padapter)) { /* || IS_HARDWARE_TYPE_8192EU(padapter)) */
  8735. /* This AGG_PH_TH only for UsbRxAggMode == USB_RX_AGG_USB */
  8736. if ((pHalData->rxagg_mode == RX_AGG_USB) && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)) {
  8737. if (pdvobjpriv->traffic_stat.cur_tx_tp > 2 && pdvobjpriv->traffic_stat.cur_rx_tp < 30)
  8738. rtw_write16(padapter , REG_RXDMA_AGG_PG_TH , 0x1010);
  8739. else if (pdvobjpriv->traffic_stat.last_tx_bytes > 220000 && pdvobjpriv->traffic_stat.cur_rx_tp < 30)
  8740. rtw_write16(padapter , REG_RXDMA_AGG_PG_TH , 0x1006);
  8741. else
  8742. rtw_write16(padapter, REG_RXDMA_AGG_PG_TH, 0x2005); /* dmc agg th 20K */
  8743. /* RTW_INFO("TX_TP=%u, RX_TP=%u\n", pdvobjpriv->traffic_stat.cur_tx_tp, pdvobjpriv->traffic_stat.cur_rx_tp); */
  8744. }
  8745. } else if (IS_HARDWARE_TYPE_8812(padapter)) {
  8746. #ifdef CONFIG_CONCURRENT_MODE
  8747. u8 i;
  8748. _adapter *iface;
  8749. u8 bassocaed = _FALSE;
  8750. struct mlme_ext_priv *mlmeext;
  8751. for (i = 0; i < pdvobjpriv->iface_nums; i++) {
  8752. iface = pdvobjpriv->padapters[i];
  8753. mlmeext = &iface->mlmeextpriv;
  8754. if (rtw_linked_check(iface) == _TRUE) {
  8755. if (mlmeext->cur_wireless_mode >= cur_wireless_mode)
  8756. cur_wireless_mode = mlmeext->cur_wireless_mode;
  8757. bassocaed = _TRUE;
  8758. }
  8759. }
  8760. if (bassocaed)
  8761. #endif
  8762. rtw_set_usb_agg_by_mode(padapter, cur_wireless_mode);
  8763. #ifdef CONFIG_PLATFORM_NOVATEK_NT72668
  8764. } else {
  8765. rtw_set_usb_agg_by_mode(padapter, cur_wireless_mode);
  8766. #endif /* CONFIG_PLATFORM_NOVATEK_NT72668 */
  8767. }
  8768. #endif /* RTW_HALMAC */
  8769. #endif /* CONFIG_USB_RX_AGGREGATION */
  8770. }
  8771. /* bus-agg check for SoftAP mode */
  8772. inline u8 rtw_hal_busagg_qsel_check(_adapter *padapter, u8 pre_qsel, u8 next_qsel)
  8773. {
  8774. struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
  8775. u8 chk_rst = _SUCCESS;
  8776. if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
  8777. return chk_rst;
  8778. /* if((pre_qsel == 0xFF)||(next_qsel== 0xFF)) */
  8779. /* return chk_rst; */
  8780. if (((pre_qsel == QSLT_HIGH) || ((next_qsel == QSLT_HIGH)))
  8781. && (pre_qsel != next_qsel)) {
  8782. /* RTW_INFO("### bus-agg break cause of qsel misatch, pre_qsel=0x%02x,next_qsel=0x%02x ###\n", */
  8783. /* pre_qsel,next_qsel); */
  8784. chk_rst = _FAIL;
  8785. }
  8786. return chk_rst;
  8787. }
  8788. /*
  8789. * Description:
  8790. * dump_TX_FIFO: This is only used to dump TX_FIFO for debug WoW mode offload
  8791. * contant.
  8792. *
  8793. * Input:
  8794. * adapter: adapter pointer.
  8795. * page_num: The max. page number that user want to dump.
  8796. * page_size: page size of each page. eg. 128 bytes, 256 bytes, 512byte.
  8797. */
  8798. void dump_TX_FIFO(_adapter *padapter, u8 page_num, u16 page_size)
  8799. {
  8800. int i;
  8801. u8 val = 0;
  8802. u8 base = 0;
  8803. u32 addr = 0;
  8804. u32 count = (page_size / 8);
  8805. if (page_num <= 0) {
  8806. RTW_INFO("!!%s: incorrect input page_num paramter!\n", __func__);
  8807. return;
  8808. }
  8809. if (page_size < 128 || page_size > 512) {
  8810. RTW_INFO("!!%s: incorrect input page_size paramter!\n", __func__);
  8811. return;
  8812. }
  8813. RTW_INFO("+%s+\n", __func__);
  8814. val = rtw_read8(padapter, 0x106);
  8815. rtw_write8(padapter, 0x106, 0x69);
  8816. RTW_INFO("0x106: 0x%02x\n", val);
  8817. base = rtw_read8(padapter, 0x209);
  8818. RTW_INFO("0x209: 0x%02x\n", base);
  8819. addr = ((base)*page_size) / 8;
  8820. for (i = 0 ; i < page_num * count ; i += 2) {
  8821. rtw_write32(padapter, 0x140, addr + i);
  8822. printk(" %08x %08x ", rtw_read32(padapter, 0x144), rtw_read32(padapter, 0x148));
  8823. rtw_write32(padapter, 0x140, addr + i + 1);
  8824. printk(" %08x %08x\n", rtw_read32(padapter, 0x144), rtw_read32(padapter, 0x148));
  8825. }
  8826. }
  8827. #ifdef CONFIG_GPIO_API
  8828. u8 rtw_hal_get_gpio(_adapter *adapter, u8 gpio_num)
  8829. {
  8830. u8 value = 0;
  8831. u8 direction = 0;
  8832. u32 gpio_ctrl_reg_to_set = REG_GPIO_PIN_CTRL + 2;
  8833. u8 gpio_num_to_set = gpio_num;
  8834. struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
  8835. if (rtw_hal_gpio_func_check(adapter, gpio_num) == _FAIL)
  8836. return value;
  8837. rtw_ps_deny(adapter, PS_DENY_IOCTL);
  8838. RTW_INFO("rf_pwrstate=0x%02x\n", pwrpriv->rf_pwrstate);
  8839. LeaveAllPowerSaveModeDirect(adapter);
  8840. if (gpio_num > 7) {
  8841. gpio_ctrl_reg_to_set = REG_GPIO_PIN_CTRL_2 + 2;
  8842. gpio_num_to_set = gpio_num - 8;
  8843. }
  8844. /* Read GPIO Direction */
  8845. direction = (rtw_read8(adapter, gpio_ctrl_reg_to_set) & BIT(gpio_num_to_set)) >> gpio_num;
  8846. /* According the direction to read register value */
  8847. if (direction)
  8848. value = (rtw_read8(adapter, gpio_ctrl_reg_to_set) & BIT(gpio_num_to_set)) >> gpio_num;
  8849. else
  8850. value = (rtw_read8(adapter, gpio_ctrl_reg_to_set) & BIT(gpio_num_to_set)) >> gpio_num;
  8851. rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
  8852. RTW_INFO("%s direction=%d value=%d\n", __FUNCTION__, direction, value);
  8853. return value;
  8854. }
  8855. int rtw_hal_set_gpio_output_value(_adapter *adapter, u8 gpio_num, bool isHigh)
  8856. {
  8857. u8 direction = 0;
  8858. u8 res = -1;
  8859. u32 gpio_ctrl_reg_to_set = REG_GPIO_PIN_CTRL + 2;
  8860. u8 gpio_num_to_set = gpio_num;
  8861. if (rtw_hal_gpio_func_check(adapter, gpio_num) == _FAIL)
  8862. return -1;
  8863. rtw_ps_deny(adapter, PS_DENY_IOCTL);
  8864. LeaveAllPowerSaveModeDirect(adapter);
  8865. if (gpio_num > 7) {
  8866. gpio_ctrl_reg_to_set = REG_GPIO_PIN_CTRL_2 + 2;
  8867. gpio_num_to_set = gpio_num - 8;
  8868. }
  8869. /* Read GPIO direction */
  8870. direction = (rtw_read8(adapter, REG_GPIO_PIN_CTRL + 2) & BIT(gpio_num)) >> gpio_num;
  8871. /* If GPIO is output direction, setting value. */
  8872. if (direction) {
  8873. if (isHigh)
  8874. rtw_write8(adapter, gpio_ctrl_reg_to_set, rtw_read8(adapter, gpio_ctrl_reg_to_set) | BIT(gpio_num_to_set));
  8875. else
  8876. rtw_write8(adapter, gpio_ctrl_reg_to_set, rtw_read8(adapter, gpio_ctrl_reg_to_set) & ~BIT(gpio_num_to_set));
  8877. RTW_INFO("%s Set gpio %x[%d]=%d\n", __FUNCTION__, REG_GPIO_PIN_CTRL + 1, gpio_num, isHigh);
  8878. res = 0;
  8879. } else {
  8880. RTW_INFO("%s The gpio is input,not be set!\n", __FUNCTION__);
  8881. res = -1;
  8882. }
  8883. rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
  8884. return res;
  8885. }
  8886. int rtw_hal_config_gpio(_adapter *adapter, u8 gpio_num, bool isOutput)
  8887. {
  8888. u32 gpio_ctrl_reg_to_set = REG_GPIO_PIN_CTRL + 2;
  8889. u8 gpio_num_to_set = gpio_num;
  8890. if (rtw_hal_gpio_func_check(adapter, gpio_num) == _FAIL)
  8891. return -1;
  8892. RTW_INFO("%s gpio_num =%d direction=%d\n", __FUNCTION__, gpio_num, isOutput);
  8893. rtw_ps_deny(adapter, PS_DENY_IOCTL);
  8894. LeaveAllPowerSaveModeDirect(adapter);
  8895. rtw_hal_gpio_multi_func_reset(adapter, gpio_num);
  8896. if (gpio_num > 7) {
  8897. gpio_ctrl_reg_to_set = REG_GPIO_PIN_CTRL_2 + 2;
  8898. gpio_num_to_set = gpio_num - 8;
  8899. }
  8900. if (isOutput)
  8901. rtw_write8(adapter, gpio_ctrl_reg_to_set, rtw_read8(adapter, gpio_ctrl_reg_to_set) | BIT(gpio_num_to_set));
  8902. else
  8903. rtw_write8(adapter, gpio_ctrl_reg_to_set, rtw_read8(adapter, gpio_ctrl_reg_to_set) & ~BIT(gpio_num_to_set));
  8904. rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
  8905. return 0;
  8906. }
  8907. int rtw_hal_register_gpio_interrupt(_adapter *adapter, int gpio_num, void(*callback)(u8 level))
  8908. {
  8909. u8 value;
  8910. u8 direction;
  8911. PHAL_DATA_TYPE phal = GET_HAL_DATA(adapter);
  8912. if (IS_HARDWARE_TYPE_8188E(adapter)) {
  8913. if (gpio_num > 7 || gpio_num < 4) {
  8914. RTW_PRINT("%s The gpio number does not included 4~7.\n", __FUNCTION__);
  8915. return -1;
  8916. }
  8917. }
  8918. rtw_ps_deny(adapter, PS_DENY_IOCTL);
  8919. LeaveAllPowerSaveModeDirect(adapter);
  8920. /* Read GPIO direction */
  8921. direction = (rtw_read8(adapter, REG_GPIO_PIN_CTRL + 2) & BIT(gpio_num)) >> gpio_num;
  8922. if (direction) {
  8923. RTW_PRINT("%s Can't register output gpio as interrupt.\n", __FUNCTION__);
  8924. return -1;
  8925. }
  8926. /* Config GPIO Mode */
  8927. rtw_write8(adapter, REG_GPIO_PIN_CTRL + 3, rtw_read8(adapter, REG_GPIO_PIN_CTRL + 3) | BIT(gpio_num));
  8928. /* Register GPIO interrupt handler*/
  8929. adapter->gpiointpriv.callback[gpio_num] = callback;
  8930. /* Set GPIO interrupt mode, 0:positive edge, 1:negative edge */
  8931. value = rtw_read8(adapter, REG_GPIO_PIN_CTRL) & BIT(gpio_num);
  8932. adapter->gpiointpriv.interrupt_mode = rtw_read8(adapter, REG_HSIMR + 2) ^ value;
  8933. rtw_write8(adapter, REG_GPIO_INTM, adapter->gpiointpriv.interrupt_mode);
  8934. /* Enable GPIO interrupt */
  8935. adapter->gpiointpriv.interrupt_enable_mask = rtw_read8(adapter, REG_HSIMR + 2) | BIT(gpio_num);
  8936. rtw_write8(adapter, REG_HSIMR + 2, adapter->gpiointpriv.interrupt_enable_mask);
  8937. rtw_hal_update_hisr_hsisr_ind(adapter, 1);
  8938. rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
  8939. return 0;
  8940. }
  8941. int rtw_hal_disable_gpio_interrupt(_adapter *adapter, int gpio_num)
  8942. {
  8943. u8 value;
  8944. u8 direction;
  8945. PHAL_DATA_TYPE phal = GET_HAL_DATA(adapter);
  8946. if (IS_HARDWARE_TYPE_8188E(adapter)) {
  8947. if (gpio_num > 7 || gpio_num < 4) {
  8948. RTW_INFO("%s The gpio number does not included 4~7.\n", __FUNCTION__);
  8949. return -1;
  8950. }
  8951. }
  8952. rtw_ps_deny(adapter, PS_DENY_IOCTL);
  8953. LeaveAllPowerSaveModeDirect(adapter);
  8954. /* Config GPIO Mode */
  8955. rtw_write8(adapter, REG_GPIO_PIN_CTRL + 3, rtw_read8(adapter, REG_GPIO_PIN_CTRL + 3) & ~BIT(gpio_num));
  8956. /* Unregister GPIO interrupt handler*/
  8957. adapter->gpiointpriv.callback[gpio_num] = NULL;
  8958. /* Reset GPIO interrupt mode, 0:positive edge, 1:negative edge */
  8959. adapter->gpiointpriv.interrupt_mode = rtw_read8(adapter, REG_GPIO_INTM) & ~BIT(gpio_num);
  8960. rtw_write8(adapter, REG_GPIO_INTM, 0x00);
  8961. /* Disable GPIO interrupt */
  8962. adapter->gpiointpriv.interrupt_enable_mask = rtw_read8(adapter, REG_HSIMR + 2) & ~BIT(gpio_num);
  8963. rtw_write8(adapter, REG_HSIMR + 2, adapter->gpiointpriv.interrupt_enable_mask);
  8964. if (!adapter->gpiointpriv.interrupt_enable_mask)
  8965. rtw_hal_update_hisr_hsisr_ind(adapter, 0);
  8966. rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
  8967. return 0;
  8968. }
  8969. #endif
  8970. s8 rtw_hal_ch_sw_iqk_info_search(_adapter *padapter, u8 central_chnl, u8 bw_mode)
  8971. {
  8972. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
  8973. u8 i;
  8974. for (i = 0; i < MAX_IQK_INFO_BACKUP_CHNL_NUM; i++) {
  8975. if ((pHalData->iqk_reg_backup[i].central_chnl != 0)) {
  8976. if ((pHalData->iqk_reg_backup[i].central_chnl == central_chnl)
  8977. && (pHalData->iqk_reg_backup[i].bw_mode == bw_mode))
  8978. return i;
  8979. }
  8980. }
  8981. return -1;
  8982. }
  8983. void rtw_hal_ch_sw_iqk_info_backup(_adapter *padapter)
  8984. {
  8985. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
  8986. s8 res;
  8987. u8 i;
  8988. /* If it's an existed record, overwrite it */
  8989. res = rtw_hal_ch_sw_iqk_info_search(padapter, pHalData->current_channel, pHalData->current_channel_bw);
  8990. if ((res >= 0) && (res < MAX_IQK_INFO_BACKUP_CHNL_NUM)) {
  8991. rtw_hal_set_hwreg(padapter, HW_VAR_CH_SW_IQK_INFO_BACKUP, (u8 *)&(pHalData->iqk_reg_backup[res]));
  8992. return;
  8993. }
  8994. /* Search for the empty record to use */
  8995. for (i = 0; i < MAX_IQK_INFO_BACKUP_CHNL_NUM; i++) {
  8996. if (pHalData->iqk_reg_backup[i].central_chnl == 0) {
  8997. rtw_hal_set_hwreg(padapter, HW_VAR_CH_SW_IQK_INFO_BACKUP, (u8 *)&(pHalData->iqk_reg_backup[i]));
  8998. return;
  8999. }
  9000. }
  9001. /* Else, overwrite the oldest record */
  9002. for (i = 1; i < MAX_IQK_INFO_BACKUP_CHNL_NUM; i++)
  9003. _rtw_memcpy(&(pHalData->iqk_reg_backup[i - 1]), &(pHalData->iqk_reg_backup[i]), sizeof(struct hal_iqk_reg_backup));
  9004. rtw_hal_set_hwreg(padapter, HW_VAR_CH_SW_IQK_INFO_BACKUP, (u8 *)&(pHalData->iqk_reg_backup[MAX_IQK_INFO_BACKUP_CHNL_NUM - 1]));
  9005. }
  9006. void rtw_hal_ch_sw_iqk_info_restore(_adapter *padapter, u8 ch_sw_use_case)
  9007. {
  9008. rtw_hal_set_hwreg(padapter, HW_VAR_CH_SW_IQK_INFO_RESTORE, &ch_sw_use_case);
  9009. }
  9010. void rtw_dump_mac_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter)
  9011. {
  9012. u32 mac_cck_ok = 0, mac_ofdm_ok = 0, mac_ht_ok = 0, mac_vht_ok = 0;
  9013. u32 mac_cck_err = 0, mac_ofdm_err = 0, mac_ht_err = 0, mac_vht_err = 0;
  9014. u32 mac_cck_fa = 0, mac_ofdm_fa = 0, mac_ht_fa = 0;
  9015. u32 DropPacket = 0;
  9016. if (!rx_counter) {
  9017. rtw_warn_on(1);
  9018. return;
  9019. }
  9020. if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter))
  9021. phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x0);/*clear bit-26*/
  9022. phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x3);
  9023. mac_cck_ok = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */
  9024. phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x0);
  9025. mac_ofdm_ok = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */
  9026. phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x6);
  9027. mac_ht_ok = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */
  9028. mac_vht_ok = 0;
  9029. if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) {
  9030. phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x0);
  9031. phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x1);
  9032. mac_vht_ok = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]*/
  9033. phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x0);/*clear bit-26*/
  9034. }
  9035. phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x4);
  9036. mac_cck_err = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */
  9037. phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x1);
  9038. mac_ofdm_err = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */
  9039. phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x7);
  9040. mac_ht_err = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */
  9041. mac_vht_err = 0;
  9042. if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) {
  9043. phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x1);
  9044. phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x1);
  9045. mac_vht_err = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]*/
  9046. phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x0);/*clear bit-26*/
  9047. }
  9048. phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x5);
  9049. mac_cck_fa = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */
  9050. phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x2);
  9051. mac_ofdm_fa = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */
  9052. phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x9);
  9053. mac_ht_fa = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */
  9054. /* Mac_DropPacket */
  9055. rtw_write32(padapter, REG_RXERR_RPT, (rtw_read32(padapter, REG_RXERR_RPT) & 0x0FFFFFFF) | Mac_DropPacket);
  9056. DropPacket = rtw_read32(padapter, REG_RXERR_RPT) & 0x0000FFFF;
  9057. rx_counter->rx_pkt_ok = mac_cck_ok + mac_ofdm_ok + mac_ht_ok + mac_vht_ok;
  9058. rx_counter->rx_pkt_crc_error = mac_cck_err + mac_ofdm_err + mac_ht_err + mac_vht_err;
  9059. rx_counter->rx_cck_fa = mac_cck_fa;
  9060. rx_counter->rx_ofdm_fa = mac_ofdm_fa;
  9061. rx_counter->rx_ht_fa = mac_ht_fa;
  9062. rx_counter->rx_pkt_drop = DropPacket;
  9063. }
  9064. void rtw_reset_mac_rx_counters(_adapter *padapter)
  9065. {
  9066. /* If no packet rx, MaxRx clock be gating ,BIT_DISGCLK bit19 set 1 for fix*/
  9067. if (IS_HARDWARE_TYPE_8703B(padapter) ||
  9068. IS_HARDWARE_TYPE_8723D(padapter) ||
  9069. IS_HARDWARE_TYPE_8188F(padapter))
  9070. phy_set_mac_reg(padapter, REG_RCR, BIT19, 0x1);
  9071. /* reset mac counter */
  9072. phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT27, 0x1);
  9073. phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT27, 0x0);
  9074. }
  9075. void rtw_dump_phy_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter)
  9076. {
  9077. u32 cckok = 0, cckcrc = 0, ofdmok = 0, ofdmcrc = 0, htok = 0, htcrc = 0, OFDM_FA = 0, CCK_FA = 0, vht_ok = 0, vht_err = 0;
  9078. if (!rx_counter) {
  9079. rtw_warn_on(1);
  9080. return;
  9081. }
  9082. if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) {
  9083. cckok = phy_query_bb_reg(padapter, 0xF04, 0x3FFF); /* [13:0] */
  9084. ofdmok = phy_query_bb_reg(padapter, 0xF14, 0x3FFF); /* [13:0] */
  9085. htok = phy_query_bb_reg(padapter, 0xF10, 0x3FFF); /* [13:0] */
  9086. vht_ok = phy_query_bb_reg(padapter, 0xF0C, 0x3FFF); /* [13:0] */
  9087. cckcrc = phy_query_bb_reg(padapter, 0xF04, 0x3FFF0000); /* [29:16] */
  9088. ofdmcrc = phy_query_bb_reg(padapter, 0xF14, 0x3FFF0000); /* [29:16] */
  9089. htcrc = phy_query_bb_reg(padapter, 0xF10, 0x3FFF0000); /* [29:16] */
  9090. vht_err = phy_query_bb_reg(padapter, 0xF0C, 0x3FFF0000); /* [29:16] */
  9091. CCK_FA = phy_query_bb_reg(padapter, 0xA5C, bMaskLWord);
  9092. OFDM_FA = phy_query_bb_reg(padapter, 0xF48, bMaskLWord);
  9093. } else {
  9094. cckok = phy_query_bb_reg(padapter, 0xF88, bMaskDWord);
  9095. ofdmok = phy_query_bb_reg(padapter, 0xF94, bMaskLWord);
  9096. htok = phy_query_bb_reg(padapter, 0xF90, bMaskLWord);
  9097. vht_ok = 0;
  9098. cckcrc = phy_query_bb_reg(padapter, 0xF84, bMaskDWord);
  9099. ofdmcrc = phy_query_bb_reg(padapter, 0xF94, bMaskHWord);
  9100. htcrc = phy_query_bb_reg(padapter, 0xF90, bMaskHWord);
  9101. vht_err = 0;
  9102. OFDM_FA = phy_query_bb_reg(padapter, 0xCF0, bMaskLWord) + phy_query_bb_reg(padapter, 0xCF2, bMaskLWord) +
  9103. phy_query_bb_reg(padapter, 0xDA2, bMaskLWord) + phy_query_bb_reg(padapter, 0xDA4, bMaskLWord) +
  9104. phy_query_bb_reg(padapter, 0xDA6, bMaskLWord) + phy_query_bb_reg(padapter, 0xDA8, bMaskLWord);
  9105. CCK_FA = (rtw_read8(padapter, 0xA5B) << 8) | (rtw_read8(padapter, 0xA5C));
  9106. }
  9107. rx_counter->rx_pkt_ok = cckok + ofdmok + htok + vht_ok;
  9108. rx_counter->rx_pkt_crc_error = cckcrc + ofdmcrc + htcrc + vht_err;
  9109. rx_counter->rx_ofdm_fa = OFDM_FA;
  9110. rx_counter->rx_cck_fa = CCK_FA;
  9111. }
  9112. void rtw_reset_phy_trx_ok_counters(_adapter *padapter)
  9113. {
  9114. if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) {
  9115. phy_set_bb_reg(padapter, 0xB58, BIT0, 0x1);
  9116. phy_set_bb_reg(padapter, 0xB58, BIT0, 0x0);
  9117. }
  9118. }
  9119. void rtw_reset_phy_rx_counters(_adapter *padapter)
  9120. {
  9121. /* reset phy counter */
  9122. if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) {
  9123. rtw_reset_phy_trx_ok_counters(padapter);
  9124. phy_set_bb_reg(padapter, 0x9A4, BIT17, 0x1);/* reset OFDA FA counter */
  9125. phy_set_bb_reg(padapter, 0x9A4, BIT17, 0x0);
  9126. phy_set_bb_reg(padapter, 0xA2C, BIT15, 0x0);/* reset CCK FA counter */
  9127. phy_set_bb_reg(padapter, 0xA2C, BIT15, 0x1);
  9128. } else {
  9129. phy_set_bb_reg(padapter, 0xF14, BIT16, 0x1);
  9130. rtw_msleep_os(10);
  9131. phy_set_bb_reg(padapter, 0xF14, BIT16, 0x0);
  9132. phy_set_bb_reg(padapter, 0xD00, BIT27, 0x1);/* reset OFDA FA counter */
  9133. phy_set_bb_reg(padapter, 0xC0C, BIT31, 0x1);/* reset OFDA FA counter */
  9134. phy_set_bb_reg(padapter, 0xD00, BIT27, 0x0);
  9135. phy_set_bb_reg(padapter, 0xC0C, BIT31, 0x0);
  9136. phy_set_bb_reg(padapter, 0xA2C, BIT15, 0x0);/* reset CCK FA counter */
  9137. phy_set_bb_reg(padapter, 0xA2C, BIT15, 0x1);
  9138. }
  9139. }
  9140. #ifdef DBG_RX_COUNTER_DUMP
  9141. void rtw_dump_drv_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter)
  9142. {
  9143. struct recv_priv *precvpriv = &padapter->recvpriv;
  9144. if (!rx_counter) {
  9145. rtw_warn_on(1);
  9146. return;
  9147. }
  9148. rx_counter->rx_pkt_ok = padapter->drv_rx_cnt_ok;
  9149. rx_counter->rx_pkt_crc_error = padapter->drv_rx_cnt_crcerror;
  9150. rx_counter->rx_pkt_drop = precvpriv->rx_drop - padapter->drv_rx_cnt_drop;
  9151. }
  9152. void rtw_reset_drv_rx_counters(_adapter *padapter)
  9153. {
  9154. struct recv_priv *precvpriv = &padapter->recvpriv;
  9155. padapter->drv_rx_cnt_ok = 0;
  9156. padapter->drv_rx_cnt_crcerror = 0;
  9157. padapter->drv_rx_cnt_drop = precvpriv->rx_drop;
  9158. }
  9159. void rtw_dump_phy_rxcnts_preprocess(_adapter *padapter, u8 rx_cnt_mode)
  9160. {
  9161. u8 initialgain;
  9162. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
  9163. if ((!(padapter->dump_rx_cnt_mode & DUMP_PHY_RX_COUNTER)) && (rx_cnt_mode & DUMP_PHY_RX_COUNTER)) {
  9164. rtw_hal_get_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &initialgain, NULL);
  9165. RTW_INFO("%s CurIGValue:0x%02x\n", __FUNCTION__, initialgain);
  9166. rtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &initialgain, _FALSE);
  9167. /*disable dynamic functions, such as high power, DIG*/
  9168. rtw_phydm_ability_backup(padapter);
  9169. rtw_phydm_func_clr(padapter, (ODM_BB_DIG | ODM_BB_FA_CNT));
  9170. } else if ((padapter->dump_rx_cnt_mode & DUMP_PHY_RX_COUNTER) && (!(rx_cnt_mode & DUMP_PHY_RX_COUNTER))) {
  9171. /* turn on phy-dynamic functions */
  9172. rtw_phydm_ability_restore(padapter);
  9173. initialgain = 0xff; /* restore RX GAIN */
  9174. rtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &initialgain, _FALSE);
  9175. }
  9176. }
  9177. void rtw_dump_rx_counters(_adapter *padapter)
  9178. {
  9179. struct dbg_rx_counter rx_counter;
  9180. if (padapter->dump_rx_cnt_mode & DUMP_DRV_RX_COUNTER) {
  9181. _rtw_memset(&rx_counter, 0, sizeof(struct dbg_rx_counter));
  9182. rtw_dump_drv_rx_counters(padapter, &rx_counter);
  9183. RTW_INFO("Drv Received packet OK:%d CRC error:%d Drop Packets: %d\n",
  9184. rx_counter.rx_pkt_ok, rx_counter.rx_pkt_crc_error, rx_counter.rx_pkt_drop);
  9185. rtw_reset_drv_rx_counters(padapter);
  9186. }
  9187. if (padapter->dump_rx_cnt_mode & DUMP_MAC_RX_COUNTER) {
  9188. _rtw_memset(&rx_counter, 0, sizeof(struct dbg_rx_counter));
  9189. rtw_dump_mac_rx_counters(padapter, &rx_counter);
  9190. RTW_INFO("Mac Received packet OK:%d CRC error:%d FA Counter: %d Drop Packets: %d\n",
  9191. rx_counter.rx_pkt_ok, rx_counter.rx_pkt_crc_error,
  9192. rx_counter.rx_cck_fa + rx_counter.rx_ofdm_fa + rx_counter.rx_ht_fa,
  9193. rx_counter.rx_pkt_drop);
  9194. rtw_reset_mac_rx_counters(padapter);
  9195. }
  9196. if (padapter->dump_rx_cnt_mode & DUMP_PHY_RX_COUNTER) {
  9197. _rtw_memset(&rx_counter, 0, sizeof(struct dbg_rx_counter));
  9198. rtw_dump_phy_rx_counters(padapter, &rx_counter);
  9199. /* RTW_INFO("%s: OFDM_FA =%d\n", __FUNCTION__, rx_counter.rx_ofdm_fa); */
  9200. /* RTW_INFO("%s: CCK_FA =%d\n", __FUNCTION__, rx_counter.rx_cck_fa); */
  9201. RTW_INFO("Phy Received packet OK:%d CRC error:%d FA Counter: %d\n", rx_counter.rx_pkt_ok, rx_counter.rx_pkt_crc_error,
  9202. rx_counter.rx_ofdm_fa + rx_counter.rx_cck_fa);
  9203. rtw_reset_phy_rx_counters(padapter);
  9204. }
  9205. }
  9206. #endif
  9207. void rtw_get_noise(_adapter *padapter)
  9208. {
  9209. #if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR)
  9210. struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
  9211. struct noise_info info;
  9212. if (rtw_linked_check(padapter)) {
  9213. info.bPauseDIG = _TRUE;
  9214. info.IGIValue = 0x1e;
  9215. info.max_time = 100;/* ms */
  9216. info.chan = pmlmeext->cur_channel ;/* rtw_get_oper_ch(padapter); */
  9217. rtw_ps_deny(padapter, PS_DENY_IOCTL);
  9218. LeaveAllPowerSaveModeDirect(padapter);
  9219. rtw_hal_set_odm_var(padapter, HAL_ODM_NOISE_MONITOR, &info, _FALSE);
  9220. /* odm_inband_noise_monitor(podmpriv,_TRUE,0x20,100); */
  9221. rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL);
  9222. rtw_hal_get_odm_var(padapter, HAL_ODM_NOISE_MONITOR, &(info.chan), &(padapter->recvpriv.noise));
  9223. #ifdef DBG_NOISE_MONITOR
  9224. RTW_INFO("chan:%d,noise_level:%d\n", info.chan, padapter->recvpriv.noise);
  9225. #endif
  9226. }
  9227. #endif
  9228. }
  9229. u8 rtw_get_current_tx_sgi(_adapter *padapter, u8 macid)
  9230. {
  9231. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
  9232. struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv;
  9233. struct _rate_adaptive_table_ *pRA_Table = &pDM_Odm->dm_ra_table;
  9234. u8 curr_tx_sgi = 0;
  9235. #if defined(CONFIG_RTL8188E)
  9236. curr_tx_sgi = odm_ra_get_decision_rate_8188e(pDM_Odm, macid);
  9237. #else
  9238. curr_tx_sgi = ((pRA_Table->link_tx_rate[macid]) & 0x80) >> 7;
  9239. #endif
  9240. return curr_tx_sgi;
  9241. }
  9242. u8 rtw_get_current_tx_rate(_adapter *padapter, u8 macid)
  9243. {
  9244. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
  9245. struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv;
  9246. struct _rate_adaptive_table_ *pRA_Table = &pDM_Odm->dm_ra_table;
  9247. u8 rate_id = 0;
  9248. #if (RATE_ADAPTIVE_SUPPORT == 1)
  9249. rate_id = odm_ra_get_decision_rate_8188e(pDM_Odm, macid);
  9250. #else
  9251. rate_id = (pRA_Table->link_tx_rate[macid]) & 0x7f;
  9252. #endif
  9253. return rate_id;
  9254. }
  9255. void update_IOT_info(_adapter *padapter)
  9256. {
  9257. struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
  9258. struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
  9259. switch (pmlmeinfo->assoc_AP_vendor) {
  9260. case HT_IOT_PEER_MARVELL:
  9261. pmlmeinfo->turboMode_cts2self = 1;
  9262. pmlmeinfo->turboMode_rtsen = 0;
  9263. break;
  9264. case HT_IOT_PEER_RALINK:
  9265. pmlmeinfo->turboMode_cts2self = 0;
  9266. pmlmeinfo->turboMode_rtsen = 1;
  9267. /* disable high power */
  9268. rtw_phydm_func_clr(padapter, ODM_BB_DYNAMIC_TXPWR);
  9269. break;
  9270. case HT_IOT_PEER_REALTEK:
  9271. /* rtw_write16(padapter, 0x4cc, 0xffff); */
  9272. /* rtw_write16(padapter, 0x546, 0x01c0); */
  9273. /* disable high power */
  9274. rtw_phydm_func_clr(padapter, ODM_BB_DYNAMIC_TXPWR);
  9275. break;
  9276. default:
  9277. pmlmeinfo->turboMode_cts2self = 0;
  9278. pmlmeinfo->turboMode_rtsen = 1;
  9279. break;
  9280. }
  9281. }
  9282. #ifdef CONFIG_AUTO_CHNL_SEL_NHM
  9283. void rtw_acs_start(_adapter *padapter, bool bStart)
  9284. {
  9285. if (_TRUE == bStart) {
  9286. ACS_OP acs_op = ACS_INIT;
  9287. rtw_hal_set_odm_var(padapter, HAL_ODM_AUTO_CHNL_SEL, &acs_op, _TRUE);
  9288. rtw_set_acs_channel(padapter, 0);
  9289. SET_ACS_STATE(padapter, ACS_ENABLE);
  9290. } else {
  9291. SET_ACS_STATE(padapter, ACS_DISABLE);
  9292. #ifdef DBG_AUTO_CHNL_SEL_NHM
  9293. if (1) {
  9294. u8 best_24g_ch = 0;
  9295. u8 best_5g_ch = 0;
  9296. rtw_hal_get_odm_var(padapter, HAL_ODM_AUTO_CHNL_SEL, &(best_24g_ch), &(best_5g_ch));
  9297. RTW_INFO("[ACS-"ADPT_FMT"] Best 2.4G CH:%u\n", ADPT_ARG(padapter), best_24g_ch);
  9298. RTW_INFO("[ACS-"ADPT_FMT"] Best 5G CH:%u\n", ADPT_ARG(padapter), best_5g_ch);
  9299. }
  9300. #endif
  9301. }
  9302. }
  9303. #endif
  9304. /* TODO: merge with phydm, see odm_SetCrystalCap() */
  9305. void hal_set_crystal_cap(_adapter *adapter, u8 crystal_cap)
  9306. {
  9307. crystal_cap = crystal_cap & 0x3F;
  9308. switch (rtw_get_chip_type(adapter)) {
  9309. #if defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8188F)
  9310. case RTL8188E:
  9311. case RTL8188F:
  9312. /* write 0x24[16:11] = 0x24[22:17] = CrystalCap */
  9313. phy_set_bb_reg(adapter, REG_AFE_XTAL_CTRL, 0x007FF800, (crystal_cap | (crystal_cap << 6)));
  9314. break;
  9315. #endif
  9316. #if defined(CONFIG_RTL8812A)
  9317. case RTL8812:
  9318. /* write 0x2C[30:25] = 0x2C[24:19] = CrystalCap */
  9319. phy_set_bb_reg(adapter, REG_MAC_PHY_CTRL, 0x7FF80000, (crystal_cap | (crystal_cap << 6)));
  9320. break;
  9321. #endif
  9322. #if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || \
  9323. defined(CONFIG_RTL8723D) || defined(CONFIG_RTL8821A) || \
  9324. defined(CONFIG_RTL8192E)
  9325. case RTL8723B:
  9326. case RTL8703B:
  9327. case RTL8723D:
  9328. case RTL8821:
  9329. case RTL8192E:
  9330. /* write 0x2C[23:18] = 0x2C[17:12] = CrystalCap */
  9331. phy_set_bb_reg(adapter, REG_MAC_PHY_CTRL, 0x00FFF000, (crystal_cap | (crystal_cap << 6)));
  9332. break;
  9333. #endif
  9334. #if defined(CONFIG_RTL8814A)
  9335. case RTL8814A:
  9336. /* write 0x2C[26:21] = 0x2C[20:15] = CrystalCap*/
  9337. phy_set_bb_reg(adapter, REG_MAC_PHY_CTRL, 0x07FF8000, (crystal_cap | (crystal_cap << 6)));
  9338. break;
  9339. #endif
  9340. #if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
  9341. case RTL8822B:
  9342. case RTL8821C:
  9343. /* write 0x28[6:1] = 0x24[30:25] = CrystalCap */
  9344. crystal_cap = crystal_cap & 0x3F;
  9345. phy_set_bb_reg(adapter, REG_AFE_XTAL_CTRL, 0x7E000000, crystal_cap);
  9346. phy_set_bb_reg(adapter, REG_AFE_PLL_CTRL, 0x7E, crystal_cap);
  9347. break;
  9348. #endif
  9349. default:
  9350. rtw_warn_on(1);
  9351. }
  9352. }
  9353. int hal_spec_init(_adapter *adapter)
  9354. {
  9355. u8 interface_type = 0;
  9356. int ret = _SUCCESS;
  9357. interface_type = rtw_get_intf_type(adapter);
  9358. switch (rtw_get_chip_type(adapter)) {
  9359. #ifdef CONFIG_RTL8723B
  9360. case RTL8723B:
  9361. init_hal_spec_8723b(adapter);
  9362. break;
  9363. #endif
  9364. #ifdef CONFIG_RTL8703B
  9365. case RTL8703B:
  9366. init_hal_spec_8703b(adapter);
  9367. break;
  9368. #endif
  9369. #ifdef CONFIG_RTL8723D
  9370. case RTL8723D:
  9371. init_hal_spec_8723d(adapter);
  9372. break;
  9373. #endif
  9374. #ifdef CONFIG_RTL8188E
  9375. case RTL8188E:
  9376. init_hal_spec_8188e(adapter);
  9377. break;
  9378. #endif
  9379. #ifdef CONFIG_RTL8188F
  9380. case RTL8188F:
  9381. init_hal_spec_8188f(adapter);
  9382. break;
  9383. #endif
  9384. #ifdef CONFIG_RTL8812A
  9385. case RTL8812:
  9386. init_hal_spec_8812a(adapter);
  9387. break;
  9388. #endif
  9389. #ifdef CONFIG_RTL8821A
  9390. case RTL8821:
  9391. init_hal_spec_8821a(adapter);
  9392. break;
  9393. #endif
  9394. #ifdef CONFIG_RTL8192E
  9395. case RTL8192E:
  9396. init_hal_spec_8192e(adapter);
  9397. break;
  9398. #endif
  9399. #ifdef CONFIG_RTL8814A
  9400. case RTL8814A:
  9401. init_hal_spec_8814a(adapter);
  9402. break;
  9403. #endif
  9404. #ifdef CONFIG_RTL8822B
  9405. case RTL8822B:
  9406. rtl8822b_init_hal_spec(adapter);
  9407. break;
  9408. #endif
  9409. #ifdef CONFIG_RTL8821C
  9410. case RTL8821C:
  9411. init_hal_spec_rtl8821c(adapter);
  9412. break;
  9413. #endif
  9414. default:
  9415. RTW_ERR("%s: unknown chip_type:%u\n"
  9416. , __func__, rtw_get_chip_type(adapter));
  9417. ret = _FAIL;
  9418. break;
  9419. }
  9420. return ret;
  9421. }
  9422. static const char *const _band_cap_str[] = {
  9423. /* BIT0 */"2G",
  9424. /* BIT1 */"5G",
  9425. };
  9426. static const char *const _bw_cap_str[] = {
  9427. /* BIT0 */"5M",
  9428. /* BIT1 */"10M",
  9429. /* BIT2 */"20M",
  9430. /* BIT3 */"40M",
  9431. /* BIT4 */"80M",
  9432. /* BIT5 */"160M",
  9433. /* BIT6 */"80_80M",
  9434. };
  9435. static const char *const _proto_cap_str[] = {
  9436. /* BIT0 */"b",
  9437. /* BIT1 */"g",
  9438. /* BIT2 */"n",
  9439. /* BIT3 */"ac",
  9440. };
  9441. static const char *const _wl_func_str[] = {
  9442. /* BIT0 */"P2P",
  9443. /* BIT1 */"MIRACAST",
  9444. /* BIT2 */"TDLS",
  9445. /* BIT3 */"FTM",
  9446. };
  9447. void dump_hal_spec(void *sel, _adapter *adapter)
  9448. {
  9449. struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
  9450. int i;
  9451. RTW_PRINT_SEL(sel, "macid_num:%u\n", hal_spec->macid_num);
  9452. RTW_PRINT_SEL(sel, "sec_cap:0x%02x\n", hal_spec->sec_cap);
  9453. RTW_PRINT_SEL(sel, "sec_cam_ent_num:%u\n", hal_spec->sec_cam_ent_num);
  9454. RTW_PRINT_SEL(sel, "rfpath_num_2g:%u\n", hal_spec->rfpath_num_2g);
  9455. RTW_PRINT_SEL(sel, "rfpath_num_5g:%u\n", hal_spec->rfpath_num_5g);
  9456. RTW_PRINT_SEL(sel, "max_tx_cnt:%u\n", hal_spec->max_tx_cnt);
  9457. RTW_PRINT_SEL(sel, "tx_nss_num:%u\n", hal_spec->tx_nss_num);
  9458. RTW_PRINT_SEL(sel, "rx_nss_num:%u\n", hal_spec->rx_nss_num);
  9459. RTW_PRINT_SEL(sel, "band_cap:");
  9460. for (i = 0; i < BAND_CAP_BIT_NUM; i++) {
  9461. if (((hal_spec->band_cap) >> i) & BIT0 && _band_cap_str[i])
  9462. _RTW_PRINT_SEL(sel, "%s ", _band_cap_str[i]);
  9463. }
  9464. _RTW_PRINT_SEL(sel, "\n");
  9465. RTW_PRINT_SEL(sel, "bw_cap:");
  9466. for (i = 0; i < BW_CAP_BIT_NUM; i++) {
  9467. if (((hal_spec->bw_cap) >> i) & BIT0 && _bw_cap_str[i])
  9468. _RTW_PRINT_SEL(sel, "%s ", _bw_cap_str[i]);
  9469. }
  9470. _RTW_PRINT_SEL(sel, "\n");
  9471. RTW_PRINT_SEL(sel, "proto_cap:");
  9472. for (i = 0; i < PROTO_CAP_BIT_NUM; i++) {
  9473. if (((hal_spec->proto_cap) >> i) & BIT0 && _proto_cap_str[i])
  9474. _RTW_PRINT_SEL(sel, "%s ", _proto_cap_str[i]);
  9475. }
  9476. _RTW_PRINT_SEL(sel, "\n");
  9477. RTW_PRINT_SEL(sel, "wl_func:");
  9478. for (i = 0; i < WL_FUNC_BIT_NUM; i++) {
  9479. if (((hal_spec->wl_func) >> i) & BIT0 && _wl_func_str[i])
  9480. _RTW_PRINT_SEL(sel, "%s ", _wl_func_str[i]);
  9481. }
  9482. _RTW_PRINT_SEL(sel, "\n");
  9483. }
  9484. inline bool hal_chk_band_cap(_adapter *adapter, u8 cap)
  9485. {
  9486. return GET_HAL_SPEC(adapter)->band_cap & cap;
  9487. }
  9488. inline bool hal_chk_bw_cap(_adapter *adapter, u8 cap)
  9489. {
  9490. return GET_HAL_SPEC(adapter)->bw_cap & cap;
  9491. }
  9492. inline bool hal_chk_proto_cap(_adapter *adapter, u8 cap)
  9493. {
  9494. return GET_HAL_SPEC(adapter)->proto_cap & cap;
  9495. }
  9496. inline bool hal_chk_wl_func(_adapter *adapter, u8 func)
  9497. {
  9498. return GET_HAL_SPEC(adapter)->wl_func & func;
  9499. }
  9500. inline bool hal_is_band_support(_adapter *adapter, u8 band)
  9501. {
  9502. return GET_HAL_SPEC(adapter)->band_cap & band_to_band_cap(band);
  9503. }
  9504. inline bool hal_is_bw_support(_adapter *adapter, u8 bw)
  9505. {
  9506. return GET_HAL_SPEC(adapter)->bw_cap & ch_width_to_bw_cap(bw);
  9507. }
  9508. inline bool hal_is_wireless_mode_support(_adapter *adapter, u8 mode)
  9509. {
  9510. u8 proto_cap = GET_HAL_SPEC(adapter)->proto_cap;
  9511. if (mode == WIRELESS_11B)
  9512. if ((proto_cap & PROTO_CAP_11B) && hal_chk_band_cap(adapter, BAND_CAP_2G))
  9513. return 1;
  9514. if (mode == WIRELESS_11G)
  9515. if ((proto_cap & PROTO_CAP_11G) && hal_chk_band_cap(adapter, BAND_CAP_2G))
  9516. return 1;
  9517. if (mode == WIRELESS_11A)
  9518. if ((proto_cap & PROTO_CAP_11G) && hal_chk_band_cap(adapter, BAND_CAP_5G))
  9519. return 1;
  9520. if (mode == WIRELESS_11_24N)
  9521. if ((proto_cap & PROTO_CAP_11N) && hal_chk_band_cap(adapter, BAND_CAP_2G))
  9522. return 1;
  9523. if (mode == WIRELESS_11_5N)
  9524. if ((proto_cap & PROTO_CAP_11N) && hal_chk_band_cap(adapter, BAND_CAP_5G))
  9525. return 1;
  9526. if (mode == WIRELESS_11AC)
  9527. if ((proto_cap & PROTO_CAP_11AC) && hal_chk_band_cap(adapter, BAND_CAP_5G))
  9528. return 1;
  9529. return 0;
  9530. }
  9531. /*
  9532. * hal_largest_bw - starting from in_bw, get largest bw supported by HAL
  9533. * @adapter:
  9534. * @in_bw: starting bw, value of CHANNEL_WIDTH
  9535. *
  9536. * Returns: value of CHANNEL_WIDTH
  9537. */
  9538. u8 hal_largest_bw(_adapter *adapter, u8 in_bw)
  9539. {
  9540. for (; in_bw > CHANNEL_WIDTH_20; in_bw--) {
  9541. if (hal_is_bw_support(adapter, in_bw))
  9542. break;
  9543. }
  9544. if (!hal_is_bw_support(adapter, in_bw))
  9545. rtw_warn_on(1);
  9546. return in_bw;
  9547. }
  9548. void rtw_hal_correct_tsf(_adapter *padapter, u8 hw_port, u64 tsf)
  9549. {
  9550. if (hw_port == HW_PORT0) {
  9551. /*disable related TSF function*/
  9552. rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL) & (~EN_BCN_FUNCTION));
  9553. rtw_write32(padapter, REG_TSFTR, tsf);
  9554. rtw_write32(padapter, REG_TSFTR + 4, tsf >> 32);
  9555. /*enable related TSF function*/
  9556. rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL) | EN_BCN_FUNCTION);
  9557. } else if (hw_port == HW_PORT1) {
  9558. /*disable related TSF function*/
  9559. rtw_write8(padapter, REG_BCN_CTRL_1, rtw_read8(padapter, REG_BCN_CTRL_1) & (~EN_BCN_FUNCTION));
  9560. rtw_write32(padapter, REG_TSFTR1, tsf);
  9561. rtw_write32(padapter, REG_TSFTR1 + 4, tsf >> 32);
  9562. /*enable related TSF function*/
  9563. rtw_write8(padapter, REG_BCN_CTRL_1, rtw_read8(padapter, REG_BCN_CTRL_1) | EN_BCN_FUNCTION);
  9564. } else
  9565. RTW_INFO("%s-[WARN] "ADPT_FMT" invalid hw_port:%d\n", __func__, ADPT_ARG(padapter), hw_port);
  9566. }
  9567. void ResumeTxBeacon(_adapter *padapter)
  9568. {
  9569. PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
  9570. /* 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value */
  9571. /* which should be read from register to a global variable. */
  9572. pHalData->RegFwHwTxQCtrl |= BIT(6);
  9573. rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2, pHalData->RegFwHwTxQCtrl);
  9574. rtw_write8(padapter, REG_TBTT_PROHIBIT + 1, 0xff);
  9575. pHalData->RegReg542 |= BIT(0);
  9576. rtw_write8(padapter, REG_TBTT_PROHIBIT + 2, pHalData->RegReg542);
  9577. }
  9578. void StopTxBeacon(_adapter *padapter)
  9579. {
  9580. PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
  9581. /* 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value */
  9582. /* which should be read from register to a global variable. */
  9583. pHalData->RegFwHwTxQCtrl &= ~BIT(6);
  9584. rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2, pHalData->RegFwHwTxQCtrl);
  9585. rtw_write8(padapter, REG_TBTT_PROHIBIT + 1, 0x64);
  9586. pHalData->RegReg542 &= ~BIT(0);
  9587. rtw_write8(padapter, REG_TBTT_PROHIBIT + 2, pHalData->RegReg542);
  9588. /*CheckFwRsvdPageContent(padapter);*/ /* 2010.06.23. Added by tynli. */
  9589. }
  9590. #ifdef CONFIG_MI_WITH_MBSSID_CAM /*HW port0 - MBSS*/
  9591. void hw_var_set_opmode_mbid(_adapter *Adapter, u8 mode)
  9592. {
  9593. RTW_INFO("%s()-"ADPT_FMT" mode = %d\n", __func__, ADPT_ARG(Adapter), mode);
  9594. rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR) & (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN)));
  9595. /* disable Port0 TSF update*/
  9596. rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL) | DIS_TSF_UDT);
  9597. /* set net_type */
  9598. Set_MSR(Adapter, mode);
  9599. if ((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) {
  9600. if (!rtw_mi_check_status(Adapter, MI_AP_MODE))
  9601. StopTxBeacon(Adapter);
  9602. rtw_write8(Adapter, REG_BCN_CTRL, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_ATIM);/*disable atim wnd*/
  9603. } else if (mode == _HW_STATE_ADHOC_) {
  9604. ResumeTxBeacon(Adapter);
  9605. rtw_write8(Adapter, REG_BCN_CTRL, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_BCNQ_SUB);
  9606. } else if (mode == _HW_STATE_AP_) {
  9607. ResumeTxBeacon(Adapter);
  9608. rtw_write8(Adapter, REG_BCN_CTRL, DIS_TSF_UDT | DIS_BCNQ_SUB);
  9609. /*enable to rx data frame*/
  9610. rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
  9611. /*Beacon Control related register for first time*/
  9612. rtw_write8(Adapter, REG_BCNDMATIM, 0x02); /* 2ms */
  9613. /*rtw_write8(Adapter, REG_BCN_MAX_ERR, 0xFF);*/
  9614. rtw_write8(Adapter, REG_ATIMWND, 0x0a); /* 10ms */
  9615. rtw_write16(Adapter, REG_BCNTCFG, 0x00);
  9616. rtw_write16(Adapter, REG_TBTT_PROHIBIT, 0xff04);
  9617. rtw_write16(Adapter, REG_TSFTR_SYN_OFFSET, 0x7fff);/* +32767 (~32ms) */
  9618. /*reset TSF*/
  9619. rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(0));
  9620. /*enable BCN0 Function for if1*/
  9621. /*don't enable update TSF0 for if1 (due to TSF update when beacon,probe rsp are received)*/
  9622. rtw_write8(Adapter, REG_BCN_CTRL, (DIS_TSF_UDT | EN_BCN_FUNCTION | EN_TXBCN_RPT | DIS_BCNQ_SUB));
  9623. if (IS_HARDWARE_TYPE_8821(Adapter) || IS_HARDWARE_TYPE_8192E(Adapter))/* select BCN on port 0 for DualBeacon*/
  9624. rtw_write8(Adapter, REG_CCK_CHECK, rtw_read8(Adapter, REG_CCK_CHECK) & (~BIT_BCN_PORT_SEL));
  9625. }
  9626. }
  9627. #endif
  9628. #ifdef CONFIG_ANTENNA_DIVERSITY
  9629. u8 rtw_hal_antdiv_before_linked(_adapter *padapter)
  9630. {
  9631. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
  9632. u8 cur_ant, change_ant;
  9633. if (!pHalData->AntDivCfg)
  9634. return _FALSE;
  9635. if (pHalData->sw_antdiv_bl_state == 0) {
  9636. pHalData->sw_antdiv_bl_state = 1;
  9637. rtw_hal_get_odm_var(padapter, HAL_ODM_ANTDIV_SELECT, &cur_ant, NULL);
  9638. change_ant = (cur_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;
  9639. return rtw_antenna_select_cmd(padapter, change_ant, _FALSE);
  9640. }
  9641. pHalData->sw_antdiv_bl_state = 0;
  9642. return _FALSE;
  9643. }
  9644. void rtw_hal_antdiv_rssi_compared(_adapter *padapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src)
  9645. {
  9646. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
  9647. if (pHalData->AntDivCfg) {
  9648. /*RTW_INFO("update_network=> org-RSSI(%d), new-RSSI(%d)\n", dst->Rssi, src->Rssi);*/
  9649. /*select optimum_antenna for before linked =>For antenna diversity*/
  9650. if (dst->Rssi >= src->Rssi) {/*keep org parameter*/
  9651. src->Rssi = dst->Rssi;
  9652. src->PhyInfo.Optimum_antenna = dst->PhyInfo.Optimum_antenna;
  9653. }
  9654. }
  9655. }
  9656. #endif
  9657. #ifdef CONFIG_PHY_CAPABILITY_QUERY
  9658. void rtw_dump_phy_cap_by_phydmapi(void *sel, _adapter *adapter)
  9659. {
  9660. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
  9661. struct phy_spec_t *phy_spec = &pHalData->phy_spec;
  9662. RTW_PRINT_SEL(sel, "[PHY SPEC] TRx Capability : 0x%08x\n", phy_spec->trx_cap);
  9663. RTW_PRINT_SEL(sel, "[PHY SPEC] Tx Stream Num Index : %d\n", (phy_spec->trx_cap >> 24) & 0xFF); /*Tx Stream Num Index [31:24]*/
  9664. RTW_PRINT_SEL(sel, "[PHY SPEC] Rx Stream Num Index : %d\n", (phy_spec->trx_cap >> 16) & 0xFF); /*Rx Stream Num Index [23:16]*/
  9665. RTW_PRINT_SEL(sel, "[PHY SPEC] Tx Path Num Index : %d\n", (phy_spec->trx_cap >> 8) & 0xFF);/*Tx Path Num Index [15:8]*/
  9666. RTW_PRINT_SEL(sel, "[PHY SPEC] Rx Path Num Index : %d\n\n", (phy_spec->trx_cap & 0xFF));/*Rx Path Num Index [7:0]*/
  9667. RTW_PRINT_SEL(sel, "[PHY SPEC] STBC Capability : 0x%08x\n", phy_spec->stbc_cap);
  9668. RTW_PRINT_SEL(sel, "[PHY SPEC] VHT STBC Tx : %s\n", ((phy_spec->stbc_cap >> 24) & 0xFF) ? "Supported" : "N/A"); /*VHT STBC Tx [31:24]*/
  9669. /*VHT STBC Rx [23:16]
  9670. 0 = not support
  9671. 1 = support for 1 spatial stream
  9672. 2 = support for 1 or 2 spatial streams
  9673. 3 = support for 1 or 2 or 3 spatial streams
  9674. 4 = support for 1 or 2 or 3 or 4 spatial streams*/
  9675. RTW_PRINT_SEL(sel, "[PHY SPEC] VHT STBC Rx :%d\n", ((phy_spec->stbc_cap >> 16) & 0xFF));
  9676. RTW_PRINT_SEL(sel, "[PHY SPEC] HT STBC Tx : %s\n", ((phy_spec->stbc_cap >> 8) & 0xFF) ? "Supported" : "N/A"); /*HT STBC Tx [15:8]*/
  9677. /*HT STBC Rx [7:0]
  9678. 0 = not support
  9679. 1 = support for 1 spatial stream
  9680. 2 = support for 1 or 2 spatial streams
  9681. 3 = support for 1 or 2 or 3 spatial streams*/
  9682. RTW_PRINT_SEL(sel, "[PHY SPEC] HT STBC Rx : %d\n\n", (phy_spec->stbc_cap & 0xFF));
  9683. RTW_PRINT_SEL(sel, "[PHY SPEC] LDPC Capability : 0x%08x\n", phy_spec->ldpc_cap);
  9684. RTW_PRINT_SEL(sel, "[PHY SPEC] VHT LDPC Tx : %s\n", ((phy_spec->ldpc_cap >> 24) & 0xFF) ? "Supported" : "N/A"); /*VHT LDPC Tx [31:24]*/
  9685. RTW_PRINT_SEL(sel, "[PHY SPEC] VHT LDPC Rx : %s\n", ((phy_spec->ldpc_cap >> 16) & 0xFF) ? "Supported" : "N/A"); /*VHT LDPC Rx [23:16]*/
  9686. RTW_PRINT_SEL(sel, "[PHY SPEC] HT LDPC Tx : %s\n", ((phy_spec->ldpc_cap >> 8) & 0xFF) ? "Supported" : "N/A"); /*HT LDPC Tx [15:8]*/
  9687. RTW_PRINT_SEL(sel, "[PHY SPEC] HT LDPC Rx : %s\n\n", (phy_spec->ldpc_cap & 0xFF) ? "Supported" : "N/A"); /*HT LDPC Rx [7:0]*/
  9688. #ifdef CONFIG_BEAMFORMING
  9689. RTW_PRINT_SEL(sel, "[PHY SPEC] TxBF Capability : 0x%08x\n", phy_spec->txbf_cap);
  9690. RTW_PRINT_SEL(sel, "[PHY SPEC] VHT MU Bfer : %s\n", ((phy_spec->txbf_cap >> 28) & 0xF) ? "Supported" : "N/A"); /*VHT MU Bfer [31:28]*/
  9691. RTW_PRINT_SEL(sel, "[PHY SPEC] VHT MU Bfee : %s\n", ((phy_spec->txbf_cap >> 24) & 0xF) ? "Supported" : "N/A"); /*VHT MU Bfee [27:24]*/
  9692. RTW_PRINT_SEL(sel, "[PHY SPEC] VHT SU Bfer : %s\n", ((phy_spec->txbf_cap >> 20) & 0xF) ? "Supported" : "N/A"); /*VHT SU Bfer [23:20]*/
  9693. RTW_PRINT_SEL(sel, "[PHY SPEC] VHT SU Bfee : %s\n", ((phy_spec->txbf_cap >> 16) & 0xF) ? "Supported" : "N/A"); /*VHT SU Bfee [19:16]*/
  9694. RTW_PRINT_SEL(sel, "[PHY SPEC] HT Bfer : %s\n", ((phy_spec->txbf_cap >> 4) & 0xF) ? "Supported" : "N/A"); /*HT Bfer [7:4]*/
  9695. RTW_PRINT_SEL(sel, "[PHY SPEC] HT Bfee : %s\n\n", (phy_spec->txbf_cap & 0xF) ? "Supported" : "N/A"); /*HT Bfee [3:0]*/
  9696. RTW_PRINT_SEL(sel, "[PHY SPEC] TxBF parameter : 0x%08x\n", phy_spec->txbf_param);
  9697. RTW_PRINT_SEL(sel, "[PHY SPEC] VHT Sounding Dim : %d\n", (phy_spec->txbf_param >> 24) & 0xFF); /*VHT Sounding Dim [31:24]*/
  9698. RTW_PRINT_SEL(sel, "[PHY SPEC] VHT Steering Ant : %d\n", (phy_spec->txbf_param >> 16) & 0xFF); /*VHT Steering Ant [23:16]*/
  9699. RTW_PRINT_SEL(sel, "[PHY SPEC] HT Sounding Dim : %d\n", (phy_spec->txbf_param >> 8) & 0xFF); /*HT Sounding Dim [15:8]*/
  9700. RTW_PRINT_SEL(sel, "[PHY SPEC] HT Steering Ant : %d\n", phy_spec->txbf_param & 0xFF); /*HT Steering Ant [7:0]*/
  9701. #endif
  9702. }
  9703. #else
  9704. void rtw_dump_phy_cap_by_hal(void *sel, _adapter *adapter)
  9705. {
  9706. u8 phy_cap = _FALSE;
  9707. /* STBC */
  9708. rtw_hal_get_def_var(adapter, HAL_DEF_TX_STBC, (u8 *)&phy_cap);
  9709. RTW_PRINT_SEL(sel, "[HAL] STBC Tx : %s\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
  9710. phy_cap = _FALSE;
  9711. rtw_hal_get_def_var(adapter, HAL_DEF_RX_STBC, (u8 *)&phy_cap);
  9712. RTW_PRINT_SEL(sel, "[HAL] STBC Rx : %s\n\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
  9713. /* LDPC support */
  9714. phy_cap = _FALSE;
  9715. rtw_hal_get_def_var(adapter, HAL_DEF_TX_LDPC, (u8 *)&phy_cap);
  9716. RTW_PRINT_SEL(sel, "[HAL] LDPC Tx : %s\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
  9717. phy_cap = _FALSE;
  9718. rtw_hal_get_def_var(adapter, HAL_DEF_RX_LDPC, (u8 *)&phy_cap);
  9719. RTW_PRINT_SEL(sel, "[HAL] LDPC Rx : %s\n\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
  9720. #ifdef CONFIG_BEAMFORMING
  9721. phy_cap = _FALSE;
  9722. rtw_hal_get_def_var(adapter, HAL_DEF_EXPLICIT_BEAMFORMER, (u8 *)&phy_cap);
  9723. RTW_PRINT_SEL(sel, "[HAL] Beamformer: %s\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
  9724. phy_cap = _FALSE;
  9725. rtw_hal_get_def_var(adapter, HAL_DEF_EXPLICIT_BEAMFORMEE, (u8 *)&phy_cap);
  9726. RTW_PRINT_SEL(sel, "[HAL] Beamformee: %s\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
  9727. phy_cap = _FALSE;
  9728. rtw_hal_get_def_var(adapter, HAL_DEF_VHT_MU_BEAMFORMER, &phy_cap);
  9729. RTW_PRINT_SEL(sel, "[HAL] VHT MU Beamformer: %s\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
  9730. phy_cap = _FALSE;
  9731. rtw_hal_get_def_var(adapter, HAL_DEF_VHT_MU_BEAMFORMEE, &phy_cap);
  9732. RTW_PRINT_SEL(sel, "[HAL] VHT MU Beamformee: %s\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
  9733. #endif
  9734. }
  9735. #endif
  9736. void rtw_dump_phy_cap(void *sel, _adapter *adapter)
  9737. {
  9738. RTW_PRINT_SEL(sel, "\n ======== PHY Capability ========\n");
  9739. #ifdef CONFIG_PHY_CAPABILITY_QUERY
  9740. rtw_dump_phy_cap_by_phydmapi(sel, adapter);
  9741. #else
  9742. rtw_dump_phy_cap_by_hal(sel, adapter);
  9743. #endif
  9744. }