phydm_edcaturbocheck.c 24 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698
  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. *
  19. ******************************************************************************/
  20. /* ************************************************************
  21. * include files
  22. * ************************************************************ */
  23. #include "mp_precomp.h"
  24. #include "phydm_precomp.h"
  25. #if PHYDM_SUPPORT_EDCA
  26. void
  27. odm_edca_turbo_init(
  28. void *p_dm_void)
  29. {
  30. struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
  31. #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
  32. struct _ADAPTER *adapter = NULL;
  33. HAL_DATA_TYPE *p_hal_data = NULL;
  34. if (p_dm_odm->adapter == NULL) {
  35. ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("EdcaTurboInit fail!!!\n"));
  36. return;
  37. }
  38. adapter = p_dm_odm->adapter;
  39. p_hal_data = GET_HAL_DATA(adapter);
  40. p_dm_odm->dm_edca_table.is_current_turbo_edca = false;
  41. p_dm_odm->dm_edca_table.is_cur_rdl_state = false;
  42. p_hal_data->is_any_non_be_pkts = false;
  43. #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
  44. struct _ADAPTER *adapter = p_dm_odm->adapter;
  45. p_dm_odm->dm_edca_table.is_current_turbo_edca = false;
  46. p_dm_odm->dm_edca_table.is_cur_rdl_state = false;
  47. adapter->recvpriv.is_any_non_be_pkts = false;
  48. #endif
  49. ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VO PARAM: 0x%x\n", odm_read_4byte(p_dm_odm, ODM_EDCA_VO_PARAM)));
  50. ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VI PARAM: 0x%x\n", odm_read_4byte(p_dm_odm, ODM_EDCA_VI_PARAM)));
  51. ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BE PARAM: 0x%x\n", odm_read_4byte(p_dm_odm, ODM_EDCA_BE_PARAM)));
  52. ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BK PARAM: 0x%x\n", odm_read_4byte(p_dm_odm, ODM_EDCA_BK_PARAM)));
  53. } /* ODM_InitEdcaTurbo */
  54. void
  55. odm_edca_turbo_check(
  56. void *p_dm_void
  57. )
  58. {
  59. /* */
  60. /* For AP/ADSL use struct rtl8192cd_priv* */
  61. /* For CE/NIC use struct _ADAPTER* */
  62. /* */
  63. /* */
  64. /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
  65. /* at the same time. In the stage2/3, we need to prive universal interface and merge all */
  66. /* HW dynamic mechanism. */
  67. /* */
  68. struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
  69. ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("odm_edca_turbo_check========================>\n"));
  70. if (!(p_dm_odm->support_ability & ODM_MAC_EDCA_TURBO))
  71. return;
  72. switch (p_dm_odm->support_platform) {
  73. case ODM_WIN:
  74. #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
  75. odm_edca_turbo_check_mp(p_dm_odm);
  76. #endif
  77. break;
  78. case ODM_CE:
  79. #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
  80. odm_edca_turbo_check_ce(p_dm_odm);
  81. #endif
  82. break;
  83. }
  84. ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("<========================odm_edca_turbo_check\n"));
  85. } /* odm_CheckEdcaTurbo */
  86. #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
  87. void
  88. odm_edca_turbo_check_ce(
  89. void *p_dm_void
  90. )
  91. {
  92. struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
  93. struct _ADAPTER *adapter = p_dm_odm->adapter;
  94. u32 EDCA_BE_UL = 0x5ea42b;/* Parameter suggested by Scott */ /* edca_setting_UL[p_mgnt_info->iot_peer]; */
  95. u32 EDCA_BE_DL = 0x00a42b;/* Parameter suggested by Scott */ /* edca_setting_DL[p_mgnt_info->iot_peer]; */
  96. u32 ic_type = p_dm_odm->support_ic_type;
  97. u32 iot_peer = 0;
  98. u8 wireless_mode = 0xFF; /* invalid value */
  99. u32 traffic_index;
  100. u32 edca_param;
  101. u64 cur_tx_bytes = 0;
  102. u64 cur_rx_bytes = 0;
  103. u8 bbtchange = _TRUE;
  104. u8 is_bias_on_rx = _FALSE;
  105. HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
  106. struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(adapter);
  107. struct xmit_priv *pxmitpriv = &(adapter->xmitpriv);
  108. struct recv_priv *precvpriv = &(adapter->recvpriv);
  109. struct registry_priv *pregpriv = &adapter->registrypriv;
  110. struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
  111. struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
  112. if (p_dm_odm->is_linked != _TRUE) {
  113. precvpriv->is_any_non_be_pkts = _FALSE;
  114. return;
  115. }
  116. if ((pregpriv->wifi_spec == 1)) { /* || (pmlmeinfo->HT_enable == 0)) */
  117. precvpriv->is_any_non_be_pkts = _FALSE;
  118. return;
  119. }
  120. if (p_dm_odm->p_wireless_mode != NULL)
  121. wireless_mode = *(p_dm_odm->p_wireless_mode);
  122. iot_peer = pmlmeinfo->assoc_AP_vendor;
  123. if (iot_peer >= HT_IOT_PEER_MAX) {
  124. precvpriv->is_any_non_be_pkts = _FALSE;
  125. return;
  126. }
  127. if (p_dm_odm->support_ic_type & ODM_RTL8188E) {
  128. if ((iot_peer == HT_IOT_PEER_RALINK) || (iot_peer == HT_IOT_PEER_ATHEROS))
  129. is_bias_on_rx = _TRUE;
  130. }
  131. /* Check if the status needs to be changed. */
  132. if ((bbtchange) || (!precvpriv->is_any_non_be_pkts)) {
  133. cur_tx_bytes = pdvobjpriv->traffic_stat.cur_tx_bytes;
  134. cur_rx_bytes = pdvobjpriv->traffic_stat.cur_rx_bytes;
  135. /* traffic, TX or RX */
  136. if (is_bias_on_rx) {
  137. if (cur_tx_bytes > (cur_rx_bytes << 2)) {
  138. /* Uplink TP is present. */
  139. traffic_index = UP_LINK;
  140. } else {
  141. /* Balance TP is present. */
  142. traffic_index = DOWN_LINK;
  143. }
  144. } else {
  145. if (cur_rx_bytes > (cur_tx_bytes << 2)) {
  146. /* Downlink TP is present. */
  147. traffic_index = DOWN_LINK;
  148. } else {
  149. /* Balance TP is present. */
  150. traffic_index = UP_LINK;
  151. }
  152. }
  153. /* if ((p_dm_odm->dm_edca_table.prv_traffic_idx != traffic_index) || (!p_dm_odm->dm_edca_table.is_current_turbo_edca)) */
  154. {
  155. if (p_dm_odm->support_interface == ODM_ITRF_PCIE) {
  156. EDCA_BE_UL = 0x6ea42b;
  157. EDCA_BE_DL = 0x6ea42b;
  158. }
  159. /* 92D txop can't be set to 0x3e for cisco1250 */
  160. if ((iot_peer == HT_IOT_PEER_CISCO) && (wireless_mode == ODM_WM_N24G)) {
  161. EDCA_BE_DL = edca_setting_DL[iot_peer];
  162. EDCA_BE_UL = edca_setting_UL[iot_peer];
  163. }
  164. /* merge from 92s_92c_merge temp brunch v2445 20120215 */
  165. else if ((iot_peer == HT_IOT_PEER_CISCO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == (ODM_WM_B | ODM_WM_G)) || (wireless_mode == ODM_WM_A) || (wireless_mode == ODM_WM_B)))
  166. EDCA_BE_DL = edca_setting_dl_g_mode[iot_peer];
  167. else if ((iot_peer == HT_IOT_PEER_AIRGO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == ODM_WM_A)))
  168. EDCA_BE_DL = 0xa630;
  169. else if (iot_peer == HT_IOT_PEER_MARVELL) {
  170. EDCA_BE_DL = edca_setting_DL[iot_peer];
  171. EDCA_BE_UL = edca_setting_UL[iot_peer];
  172. } else if (iot_peer == HT_IOT_PEER_ATHEROS) {
  173. /* Set DL EDCA for Atheros peer to 0x3ea42b. Suggested by SD3 Wilson for ASUS TP issue. */
  174. EDCA_BE_DL = edca_setting_DL[iot_peer];
  175. }
  176. if ((ic_type == ODM_RTL8812) || (ic_type == ODM_RTL8821) || (ic_type == ODM_RTL8192E)) { /* add 8812AU/8812AE */
  177. EDCA_BE_UL = 0x5ea42b;
  178. EDCA_BE_DL = 0x5ea42b;
  179. ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("8812A: EDCA_BE_UL=0x%x EDCA_BE_DL =0x%x", EDCA_BE_UL, EDCA_BE_DL));
  180. }
  181. if (traffic_index == DOWN_LINK)
  182. edca_param = EDCA_BE_DL;
  183. else
  184. edca_param = EDCA_BE_UL;
  185. rtw_write32(adapter, REG_EDCA_BE_PARAM, edca_param);
  186. p_dm_odm->dm_edca_table.prv_traffic_idx = traffic_index;
  187. }
  188. p_dm_odm->dm_edca_table.is_current_turbo_edca = _TRUE;
  189. } else {
  190. /* */
  191. /* Turn Off EDCA turbo here. */
  192. /* Restore original EDCA according to the declaration of AP. */
  193. /* */
  194. if (p_dm_odm->dm_edca_table.is_current_turbo_edca) {
  195. rtw_write32(adapter, REG_EDCA_BE_PARAM, p_hal_data->ac_param_be);
  196. p_dm_odm->dm_edca_table.is_current_turbo_edca = _FALSE;
  197. }
  198. }
  199. }
  200. #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
  201. void
  202. odm_edca_turbo_check_mp(
  203. void *p_dm_void
  204. )
  205. {
  206. struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
  207. struct _ADAPTER *adapter = p_dm_odm->adapter;
  208. HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
  209. struct _ADAPTER *p_default_adapter = get_default_adapter(adapter);
  210. struct _ADAPTER *p_ext_adapter = get_first_ext_adapter(adapter); /* NULL; */
  211. PMGNT_INFO p_mgnt_info = &adapter->MgntInfo;
  212. PSTA_QOS p_sta_qos = adapter->MgntInfo.p_sta_qos;
  213. /* [Win7 count Tx/Rx statistic for Extension Port] odm_CheckEdcaTurbo's adapter is always Default. 2009.08.20, by Bohn */
  214. u64 ext_cur_tx_ok_cnt = 0;
  215. u64 ext_cur_rx_ok_cnt = 0;
  216. /* For future Win7 Enable Default Port to modify AMPDU size dynamically, 2009.08.20, Bohn. */
  217. u8 two_port_status = (u8)TWO_PORT_STATUS__WITHOUT_ANY_ASSOCIATE;
  218. /* Keep past Tx/Rx packet count for RT-to-RT EDCA turbo. */
  219. u64 cur_tx_ok_cnt = 0;
  220. u64 cur_rx_ok_cnt = 0;
  221. u32 EDCA_BE_UL = 0x5ea42b;/* Parameter suggested by Scott */ /* edca_setting_UL[p_mgnt_info->iot_peer]; */
  222. u32 EDCA_BE_DL = 0x5ea42b;/* Parameter suggested by Scott */ /* edca_setting_DL[p_mgnt_info->iot_peer]; */
  223. u32 EDCA_BE = 0x5ea42b;
  224. u8 iot_peer = 0;
  225. boolean *p_is_cur_rdl_state = NULL;
  226. boolean is_last_is_cur_rdl_state = false;
  227. boolean is_bias_on_rx = false;
  228. boolean is_edca_turbo_on = false;
  229. u8 tx_rate = 0xFF;
  230. u64 value64;
  231. ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("odm_edca_turbo_check_mp========================>"));
  232. ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BE PARAM: 0x%x\n", odm_read_4byte(p_dm_odm, ODM_EDCA_BE_PARAM)));
  233. /* *******************************
  234. * list paramter for different platform
  235. * ******************************* */
  236. is_last_is_cur_rdl_state = p_dm_odm->dm_edca_table.is_cur_rdl_state;
  237. p_is_cur_rdl_state = &(p_dm_odm->dm_edca_table.is_cur_rdl_state);
  238. /* 2012/09/14 MH Add */
  239. if (p_mgnt_info->num_non_be_pkt > p_mgnt_info->reg_edca_thresh && !(adapter->MgntInfo.wifi_confg & RT_WIFI_LOGO))
  240. p_hal_data->is_any_non_be_pkts = true;
  241. p_mgnt_info->num_non_be_pkt = 0;
  242. /* Caculate TX/RX TP: */
  243. cur_tx_ok_cnt = p_dm_odm->cur_tx_ok_cnt;
  244. cur_rx_ok_cnt = p_dm_odm->cur_rx_ok_cnt;
  245. if (p_ext_adapter == NULL)
  246. p_ext_adapter = p_default_adapter;
  247. ext_cur_tx_ok_cnt = p_ext_adapter->tx_stats.num_tx_bytes_unicast - p_mgnt_info->ext_last_tx_ok_cnt;
  248. ext_cur_rx_ok_cnt = p_ext_adapter->rx_stats.num_rx_bytes_unicast - p_mgnt_info->ext_last_rx_ok_cnt;
  249. get_two_port_shared_resource(adapter, TWO_PORT_SHARED_OBJECT__STATUS, NULL, &two_port_status);
  250. /* For future Win7 Enable Default Port to modify AMPDU size dynamically, 2009.08.20, Bohn. */
  251. if (two_port_status == TWO_PORT_STATUS__EXTENSION_ONLY) {
  252. cur_tx_ok_cnt = ext_cur_tx_ok_cnt ;
  253. cur_rx_ok_cnt = ext_cur_rx_ok_cnt ;
  254. }
  255. /* */
  256. iot_peer = p_mgnt_info->iot_peer;
  257. is_bias_on_rx = (p_mgnt_info->iot_action & HT_IOT_ACT_EDCA_BIAS_ON_RX) ? true : false;
  258. is_edca_turbo_on = ((!p_hal_data->is_any_non_be_pkts)) ? true : false;
  259. ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("is_any_non_be_pkts : 0x%lx\n", p_hal_data->is_any_non_be_pkts));
  260. /* *******************************
  261. * check if edca turbo is disabled
  262. * ******************************* */
  263. if (odm_is_edca_turbo_disable(p_dm_odm)) {
  264. p_hal_data->is_any_non_be_pkts = false;
  265. p_mgnt_info->last_tx_ok_cnt = adapter->tx_stats.num_tx_bytes_unicast;
  266. p_mgnt_info->last_rx_ok_cnt = adapter->rx_stats.num_rx_bytes_unicast;
  267. p_mgnt_info->ext_last_tx_ok_cnt = p_ext_adapter->tx_stats.num_tx_bytes_unicast;
  268. p_mgnt_info->ext_last_rx_ok_cnt = p_ext_adapter->rx_stats.num_rx_bytes_unicast;
  269. }
  270. /* *******************************
  271. * remove iot case out
  272. * ******************************* */
  273. odm_edca_para_sel_by_iot(p_dm_odm, &EDCA_BE_UL, &EDCA_BE_DL);
  274. /* *******************************
  275. * Check if the status needs to be changed.
  276. * ******************************* */
  277. if (is_edca_turbo_on) {
  278. ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("is_edca_turbo_on : 0x%x is_bias_on_rx : 0x%x\n", is_edca_turbo_on, is_bias_on_rx));
  279. ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("cur_tx_ok_cnt : 0x%lx\n", cur_tx_ok_cnt));
  280. ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("cur_rx_ok_cnt : 0x%lx\n", cur_rx_ok_cnt));
  281. if (is_bias_on_rx)
  282. odm_edca_choose_traffic_idx(p_dm_odm, cur_tx_ok_cnt, cur_rx_ok_cnt, true, p_is_cur_rdl_state);
  283. else
  284. odm_edca_choose_traffic_idx(p_dm_odm, cur_tx_ok_cnt, cur_rx_ok_cnt, false, p_is_cur_rdl_state);
  285. /* modify by Guo.Mingzhi 2011-12-29 */
  286. if (adapter->AP_EDCA_PARAM[0] != EDCA_BE)
  287. EDCA_BE = adapter->AP_EDCA_PARAM[0];
  288. else
  289. EDCA_BE = ((*p_is_cur_rdl_state) == true) ? EDCA_BE_DL : EDCA_BE_UL;
  290. /*For TPLINK 8188EU test*/
  291. if ((IS_HARDWARE_TYPE_8188EU(adapter)) && (p_hal_data->UndecoratedSmoothedPWDB < 28)) { /* Set to origimal EDCA 0x5EA42B now need to update.*/
  292. } else { /*Use TPLINK preferred EDCA parameters.*/
  293. EDCA_BE = p_mgnt_info->EDCABEPara;
  294. }
  295. if (IS_HARDWARE_TYPE_8821U(adapter)) {
  296. if (p_mgnt_info->reg_tx_duty_enable) {
  297. /* 2013.01.23 LukeLee: debug for 8811AU thermal issue (reduce Tx duty cycle) */
  298. if (!p_mgnt_info->forced_data_rate) { /* auto rate */
  299. if (p_dm_odm->tx_rate != 0xFF)
  300. tx_rate = adapter->HalFunc.GetHwRateFromMRateHandler(p_dm_odm->tx_rate);
  301. } else /* force rate */
  302. tx_rate = (u8) p_mgnt_info->forced_data_rate;
  303. value64 = (cur_rx_ok_cnt << 2);
  304. if (cur_tx_ok_cnt < value64) /* Downlink */
  305. odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, EDCA_BE);
  306. else { /* Uplink */
  307. /*dbg_print("p_rf_calibrate_info->thermal_value = 0x%X\n", p_rf_calibrate_info->thermal_value);*/
  308. /*if(p_rf_calibrate_info->thermal_value < p_hal_data->eeprom_thermal_meter)*/
  309. if ((p_dm_odm->rf_calibrate_info.thermal_value < 0x2c) || (*p_dm_odm->p_band_type == BAND_ON_2_4G))
  310. odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, EDCA_BE);
  311. else {
  312. switch (tx_rate) {
  313. case MGN_VHT1SS_MCS6:
  314. case MGN_VHT1SS_MCS5:
  315. case MGN_MCS6:
  316. case MGN_MCS5:
  317. case MGN_48M:
  318. case MGN_54M:
  319. odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0x1ea42b);
  320. break;
  321. case MGN_VHT1SS_MCS4:
  322. case MGN_MCS4:
  323. case MGN_36M:
  324. odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa42b);
  325. break;
  326. case MGN_VHT1SS_MCS3:
  327. case MGN_MCS3:
  328. case MGN_24M:
  329. odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa47f);
  330. break;
  331. case MGN_VHT1SS_MCS2:
  332. case MGN_MCS2:
  333. case MGN_18M:
  334. odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa57f);
  335. break;
  336. case MGN_VHT1SS_MCS1:
  337. case MGN_MCS1:
  338. case MGN_9M:
  339. case MGN_12M:
  340. odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa77f);
  341. break;
  342. case MGN_VHT1SS_MCS0:
  343. case MGN_MCS0:
  344. case MGN_6M:
  345. odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa87f);
  346. break;
  347. default:
  348. odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, EDCA_BE);
  349. break;
  350. }
  351. }
  352. }
  353. } else
  354. odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, EDCA_BE);
  355. } else if (IS_HARDWARE_TYPE_8812AU(adapter)) {
  356. if (p_mgnt_info->reg_tx_duty_enable) {
  357. /* 2013.07.26 Wilson: debug for 8812AU thermal issue (reduce Tx duty cycle) */
  358. /* it;s the same issue as 8811AU */
  359. if (!p_mgnt_info->forced_data_rate) { /* auto rate */
  360. if (p_dm_odm->tx_rate != 0xFF)
  361. tx_rate = adapter->HalFunc.GetHwRateFromMRateHandler(p_dm_odm->tx_rate);
  362. } else /* force rate */
  363. tx_rate = (u8) p_mgnt_info->forced_data_rate;
  364. value64 = (cur_rx_ok_cnt << 2);
  365. if (cur_tx_ok_cnt < value64) /* Downlink */
  366. odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, EDCA_BE);
  367. else { /* Uplink */
  368. /*dbg_print("p_rf_calibrate_info->thermal_value = 0x%X\n", p_rf_calibrate_info->thermal_value);*/
  369. /*if(p_rf_calibrate_info->thermal_value < p_hal_data->eeprom_thermal_meter)*/
  370. if ((p_dm_odm->rf_calibrate_info.thermal_value < 0x2c) || (*p_dm_odm->p_band_type == BAND_ON_2_4G))
  371. odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, EDCA_BE);
  372. else {
  373. switch (tx_rate) {
  374. case MGN_VHT2SS_MCS9:
  375. case MGN_VHT1SS_MCS9:
  376. case MGN_VHT1SS_MCS8:
  377. case MGN_MCS15:
  378. case MGN_MCS7:
  379. odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0x1ea44f);
  380. case MGN_VHT2SS_MCS8:
  381. case MGN_VHT1SS_MCS7:
  382. case MGN_MCS14:
  383. case MGN_MCS6:
  384. case MGN_54M:
  385. odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa44f);
  386. case MGN_VHT2SS_MCS7:
  387. case MGN_VHT2SS_MCS6:
  388. case MGN_VHT1SS_MCS6:
  389. case MGN_VHT1SS_MCS5:
  390. case MGN_MCS13:
  391. case MGN_MCS5:
  392. case MGN_48M:
  393. odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa630);
  394. break;
  395. case MGN_VHT2SS_MCS5:
  396. case MGN_VHT2SS_MCS4:
  397. case MGN_VHT1SS_MCS4:
  398. case MGN_VHT1SS_MCS3:
  399. case MGN_MCS12:
  400. case MGN_MCS4:
  401. case MGN_MCS3:
  402. case MGN_36M:
  403. case MGN_24M:
  404. odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa730);
  405. break;
  406. case MGN_VHT2SS_MCS3:
  407. case MGN_VHT2SS_MCS2:
  408. case MGN_VHT2SS_MCS1:
  409. case MGN_VHT1SS_MCS2:
  410. case MGN_VHT1SS_MCS1:
  411. case MGN_MCS11:
  412. case MGN_MCS10:
  413. case MGN_MCS9:
  414. case MGN_MCS2:
  415. case MGN_MCS1:
  416. case MGN_18M:
  417. case MGN_12M:
  418. odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa830);
  419. break;
  420. case MGN_VHT2SS_MCS0:
  421. case MGN_VHT1SS_MCS0:
  422. case MGN_MCS0:
  423. case MGN_MCS8:
  424. case MGN_9M:
  425. case MGN_6M:
  426. odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa87f);
  427. break;
  428. default:
  429. odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, EDCA_BE);
  430. break;
  431. }
  432. }
  433. }
  434. } else
  435. odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, EDCA_BE);
  436. } else
  437. odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, EDCA_BE);
  438. ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("EDCA Turbo on: EDCA_BE:0x%lx\n", EDCA_BE));
  439. p_dm_odm->dm_edca_table.is_current_turbo_edca = true;
  440. ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("EDCA_BE_DL : 0x%lx EDCA_BE_UL : 0x%lx EDCA_BE : 0x%lx\n", EDCA_BE_DL, EDCA_BE_UL, EDCA_BE));
  441. } else {
  442. /* Turn Off EDCA turbo here. */
  443. /* Restore original EDCA according to the declaration of AP. */
  444. if (p_dm_odm->dm_edca_table.is_current_turbo_edca) {
  445. phydm_set_hw_reg_handler_interface(p_dm_odm, HW_VAR_AC_PARAM, GET_WMM_PARAM_ELE_SINGLE_AC_PARAM(p_sta_qos->wmm_param_ele, AC0_BE));
  446. p_dm_odm->dm_edca_table.is_current_turbo_edca = false;
  447. ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Restore EDCA BE: 0x%lx\n", p_dm_odm->WMMEDCA_BE));
  448. }
  449. }
  450. }
  451. /* check if edca turbo is disabled */
  452. boolean
  453. odm_is_edca_turbo_disable(
  454. void *p_dm_void
  455. )
  456. {
  457. struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
  458. struct _ADAPTER *adapter = p_dm_odm->adapter;
  459. PMGNT_INFO p_mgnt_info = &adapter->MgntInfo;
  460. u32 iot_peer = p_mgnt_info->iot_peer;
  461. if (p_dm_odm->is_bt_disable_edca_turbo) {
  462. ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("EdcaTurboDisable for BT!!\n"));
  463. return true;
  464. }
  465. if ((!(p_dm_odm->support_ability & ODM_MAC_EDCA_TURBO)) ||
  466. (p_dm_odm->wifi_test & RT_WIFI_LOGO) ||
  467. (iot_peer >= HT_IOT_PEER_MAX)) {
  468. ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("EdcaTurboDisable\n"));
  469. return true;
  470. }
  471. /* 1. We do not turn on EDCA turbo mode for some AP that has IOT issue */
  472. /* 2. User may disable EDCA Turbo mode with OID settings. */
  473. if (p_mgnt_info->iot_action & HT_IOT_ACT_DISABLE_EDCA_TURBO) {
  474. ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("iot_action:EdcaTurboDisable\n"));
  475. return true;
  476. }
  477. return false;
  478. }
  479. /* add iot case here: for MP/CE */
  480. void
  481. odm_edca_para_sel_by_iot(
  482. void *p_dm_void,
  483. u32 *EDCA_BE_UL,
  484. u32 *EDCA_BE_DL
  485. )
  486. {
  487. struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
  488. struct _ADAPTER *adapter = p_dm_odm->adapter;
  489. u32 iot_peer = 0;
  490. u32 ic_type = p_dm_odm->support_ic_type;
  491. u8 wireless_mode = 0xFF; /* invalid value */
  492. u32 iot_peer_sub_type = 0;
  493. PMGNT_INFO p_mgnt_info = &adapter->MgntInfo;
  494. u8 two_port_status = (u8)TWO_PORT_STATUS__WITHOUT_ANY_ASSOCIATE;
  495. if (p_dm_odm->p_wireless_mode != NULL)
  496. wireless_mode = *(p_dm_odm->p_wireless_mode);
  497. /* ========================================================= */
  498. /* list paramter for different platform */
  499. iot_peer = p_mgnt_info->iot_peer;
  500. iot_peer_sub_type = p_mgnt_info->iot_peer_subtype;
  501. get_two_port_shared_resource(adapter, TWO_PORT_SHARED_OBJECT__STATUS, NULL, &two_port_status);
  502. /* ****************************
  503. * / IOT case for MP
  504. * **************************** */
  505. if (p_dm_odm->support_interface == ODM_ITRF_PCIE) {
  506. (*EDCA_BE_UL) = 0x6ea42b;
  507. (*EDCA_BE_DL) = 0x6ea42b;
  508. }
  509. if (two_port_status == TWO_PORT_STATUS__EXTENSION_ONLY) {
  510. (*EDCA_BE_UL) = 0x5ea42b;/* Parameter suggested by Scott */ /* edca_setting_UL[ExtAdapter->mgnt_info.iot_peer]; */
  511. (*EDCA_BE_DL) = 0x5ea42b;/* Parameter suggested by Scott */ /* edca_setting_DL[ExtAdapter->mgnt_info.iot_peer]; */
  512. }
  513. #if (INTEL_PROXIMITY_SUPPORT == 1)
  514. if (p_mgnt_info->intel_class_mode_info.is_enable_ca == true)
  515. (*EDCA_BE_UL) = (*EDCA_BE_DL) = 0xa44f;
  516. else
  517. #endif
  518. {
  519. if ((p_mgnt_info->iot_action & (HT_IOT_ACT_FORCED_ENABLE_BE_TXOP | HT_IOT_ACT_AMSDU_ENABLE))) {
  520. /* To check whether we shall force turn on TXOP configuration. */
  521. if (!((*EDCA_BE_UL) & 0xffff0000))
  522. (*EDCA_BE_UL) |= 0x005e0000; /* Force TxOP limit to 0x005e for UL. */
  523. if (!((*EDCA_BE_DL) & 0xffff0000))
  524. (*EDCA_BE_DL) |= 0x005e0000; /* Force TxOP limit to 0x005e for DL. */
  525. }
  526. /* 92D txop can't be set to 0x3e for cisco1250 */
  527. if ((iot_peer == HT_IOT_PEER_CISCO) && (wireless_mode == ODM_WM_N24G)) {
  528. (*EDCA_BE_DL) = edca_setting_DL[iot_peer];
  529. (*EDCA_BE_UL) = edca_setting_UL[iot_peer];
  530. }
  531. /* merge from 92s_92c_merge temp brunch v2445 20120215 */
  532. else if ((iot_peer == HT_IOT_PEER_CISCO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == (ODM_WM_B | ODM_WM_G)) || (wireless_mode == ODM_WM_A) || (wireless_mode == ODM_WM_B)))
  533. (*EDCA_BE_DL) = edca_setting_dl_g_mode[iot_peer];
  534. else if ((iot_peer == HT_IOT_PEER_AIRGO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == ODM_WM_A)))
  535. (*EDCA_BE_DL) = 0xa630;
  536. else if (iot_peer == HT_IOT_PEER_MARVELL) {
  537. (*EDCA_BE_DL) = edca_setting_DL[iot_peer];
  538. (*EDCA_BE_UL) = edca_setting_UL[iot_peer];
  539. } else if (iot_peer == HT_IOT_PEER_ATHEROS && iot_peer_sub_type != HT_IOT_PEER_TPLINK_AC1750) {
  540. /* Set DL EDCA for Atheros peer to 0x3ea42b. Suggested by SD3 Wilson for ASUS TP issue. */
  541. if (wireless_mode == ODM_WM_G)
  542. (*EDCA_BE_DL) = edca_setting_dl_g_mode[iot_peer];
  543. else
  544. (*EDCA_BE_DL) = edca_setting_DL[iot_peer];
  545. if (ic_type == ODM_RTL8821)
  546. (*EDCA_BE_DL) = 0x5ea630;
  547. }
  548. }
  549. if ((ic_type == ODM_RTL8812) || (ic_type == ODM_RTL8192E)) { /* add 8812AU/8812AE */
  550. (*EDCA_BE_UL) = 0x5ea42b;
  551. (*EDCA_BE_DL) = 0x5ea42b;
  552. ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("8812A: EDCA_BE_UL=0x%lx EDCA_BE_DL =0x%lx\n", (*EDCA_BE_UL), (*EDCA_BE_DL)));
  553. }
  554. if ((ic_type == ODM_RTL8814A) && (iot_peer == HT_IOT_PEER_REALTEK)) { /*8814AU and 8814AR*/
  555. (*EDCA_BE_UL) = 0x5ea42b;
  556. (*EDCA_BE_DL) = 0xa42b;
  557. ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("8814A: EDCA_BE_UL=0x%lx EDCA_BE_DL =0x%lx\n", (*EDCA_BE_UL), (*EDCA_BE_DL)));
  558. }
  559. ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Special: EDCA_BE_UL=0x%lx EDCA_BE_DL =0x%lx, iot_peer = %d\n", (*EDCA_BE_UL), (*EDCA_BE_DL), iot_peer));
  560. }
  561. void
  562. odm_edca_choose_traffic_idx(
  563. void *p_dm_void,
  564. u64 cur_tx_bytes,
  565. u64 cur_rx_bytes,
  566. boolean is_bias_on_rx,
  567. boolean *p_is_cur_rdl_state
  568. )
  569. {
  570. struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
  571. if (is_bias_on_rx) {
  572. if (cur_tx_bytes > (cur_rx_bytes * 4)) {
  573. *p_is_cur_rdl_state = false;
  574. ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Uplink Traffic\n "));
  575. } else {
  576. *p_is_cur_rdl_state = true;
  577. ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Balance Traffic\n"));
  578. }
  579. } else {
  580. if (cur_rx_bytes > (cur_tx_bytes * 4)) {
  581. *p_is_cur_rdl_state = true;
  582. ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Downlink Traffic\n"));
  583. } else {
  584. *p_is_cur_rdl_state = false;
  585. ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Balance Traffic\n"));
  586. }
  587. }
  588. return ;
  589. }
  590. #endif
  591. #endif /*PHYDM_SUPPORT_EDCA*/