rtw_mp.c 94 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. *
  19. ******************************************************************************/
  20. #define _RTW_MP_C_
  21. #include <drv_types.h>
  22. #ifdef PLATFORM_FREEBSD
  23. #include <sys/unistd.h> /* for RFHIGHPID */
  24. #endif
  25. #include "../hal/phydm/phydm_precomp.h"
  26. #if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8821A)
  27. #include <rtw_bt_mp.h>
  28. #endif
  29. #ifdef CONFIG_MP_VHT_HW_TX_MODE
  30. #define CEILING_POS(X) ((X - (int)(X)) > 0 ? (int)(X + 1) : (int)(X))
  31. #define CEILING_NEG(X) ((X - (int)(X)) < 0 ? (int)(X - 1) : (int)(X))
  32. #define ceil(X) (((X) > 0) ? CEILING_POS(X) : CEILING_NEG(X))
  33. int rtfloor(float x)
  34. {
  35. int i = x - 2;
  36. while
  37. (++i <= x - 1)
  38. ;
  39. return i;
  40. }
  41. #endif
  42. #ifdef CONFIG_MP_INCLUDED
  43. u32 read_macreg(_adapter *padapter, u32 addr, u32 sz)
  44. {
  45. u32 val = 0;
  46. switch (sz) {
  47. case 1:
  48. val = rtw_read8(padapter, addr);
  49. break;
  50. case 2:
  51. val = rtw_read16(padapter, addr);
  52. break;
  53. case 4:
  54. val = rtw_read32(padapter, addr);
  55. break;
  56. default:
  57. val = 0xffffffff;
  58. break;
  59. }
  60. return val;
  61. }
  62. void write_macreg(_adapter *padapter, u32 addr, u32 val, u32 sz)
  63. {
  64. switch (sz) {
  65. case 1:
  66. rtw_write8(padapter, addr, (u8)val);
  67. break;
  68. case 2:
  69. rtw_write16(padapter, addr, (u16)val);
  70. break;
  71. case 4:
  72. rtw_write32(padapter, addr, val);
  73. break;
  74. default:
  75. break;
  76. }
  77. }
  78. u32 read_bbreg(_adapter *padapter, u32 addr, u32 bitmask)
  79. {
  80. return rtw_hal_read_bbreg(padapter, addr, bitmask);
  81. }
  82. void write_bbreg(_adapter *padapter, u32 addr, u32 bitmask, u32 val)
  83. {
  84. rtw_hal_write_bbreg(padapter, addr, bitmask, val);
  85. }
  86. u32 _read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask)
  87. {
  88. return rtw_hal_read_rfreg(padapter, rfpath, addr, bitmask);
  89. }
  90. void _write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask, u32 val)
  91. {
  92. rtw_hal_write_rfreg(padapter, rfpath, addr, bitmask, val);
  93. }
  94. u32 read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr)
  95. {
  96. return _read_rfreg(padapter, rfpath, addr, bRFRegOffsetMask);
  97. }
  98. void write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 val)
  99. {
  100. _write_rfreg(padapter, rfpath, addr, bRFRegOffsetMask, val);
  101. }
  102. static void _init_mp_priv_(struct mp_priv *pmp_priv)
  103. {
  104. WLAN_BSSID_EX *pnetwork;
  105. _rtw_memset(pmp_priv, 0, sizeof(struct mp_priv));
  106. pmp_priv->mode = MP_OFF;
  107. pmp_priv->channel = 1;
  108. pmp_priv->bandwidth = CHANNEL_WIDTH_20;
  109. pmp_priv->prime_channel_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
  110. pmp_priv->rateidx = RATE_1M;
  111. pmp_priv->txpoweridx = 0x2A;
  112. pmp_priv->antenna_tx = ANTENNA_A;
  113. pmp_priv->antenna_rx = ANTENNA_AB;
  114. pmp_priv->check_mp_pkt = 0;
  115. pmp_priv->tx_pktcount = 0;
  116. pmp_priv->rx_bssidpktcount = 0;
  117. pmp_priv->rx_pktcount = 0;
  118. pmp_priv->rx_crcerrpktcount = 0;
  119. pmp_priv->network_macaddr[0] = 0x00;
  120. pmp_priv->network_macaddr[1] = 0xE0;
  121. pmp_priv->network_macaddr[2] = 0x4C;
  122. pmp_priv->network_macaddr[3] = 0x87;
  123. pmp_priv->network_macaddr[4] = 0x66;
  124. pmp_priv->network_macaddr[5] = 0x55;
  125. pmp_priv->bSetRxBssid = _FALSE;
  126. pmp_priv->bRTWSmbCfg = _FALSE;
  127. pmp_priv->bloopback = _FALSE;
  128. pmp_priv->bloadefusemap = _FALSE;
  129. pnetwork = &pmp_priv->mp_network.network;
  130. _rtw_memcpy(pnetwork->MacAddress, pmp_priv->network_macaddr, ETH_ALEN);
  131. pnetwork->Ssid.SsidLength = 8;
  132. _rtw_memcpy(pnetwork->Ssid.Ssid, "mp_871x", pnetwork->Ssid.SsidLength);
  133. pmp_priv->tx.payload = 2;
  134. #ifdef CONFIG_80211N_HT
  135. pmp_priv->tx.attrib.ht_en = 1;
  136. #endif
  137. }
  138. #ifdef PLATFORM_WINDOWS
  139. #if 0
  140. void mp_wi_callback(
  141. IN NDIS_WORK_ITEM *pwk_item,
  142. IN PVOID cntx
  143. )
  144. {
  145. _adapter *padapter = (_adapter *)cntx;
  146. struct mp_priv *pmppriv = &padapter->mppriv;
  147. struct mp_wi_cntx *pmp_wi_cntx = &pmppriv->wi_cntx;
  148. /* Execute specified action. */
  149. if (pmp_wi_cntx->curractfunc != NULL) {
  150. LARGE_INTEGER cur_time;
  151. ULONGLONG start_time, end_time;
  152. NdisGetCurrentSystemTime(&cur_time); /* driver version */
  153. start_time = cur_time.QuadPart / 10; /* The return value is in microsecond */
  154. pmp_wi_cntx->curractfunc(padapter);
  155. NdisGetCurrentSystemTime(&cur_time); /* driver version */
  156. end_time = cur_time.QuadPart / 10; /* The return value is in microsecond */
  157. }
  158. NdisAcquireSpinLock(&(pmp_wi_cntx->mp_wi_lock));
  159. pmp_wi_cntx->bmp_wi_progress = _FALSE;
  160. NdisReleaseSpinLock(&(pmp_wi_cntx->mp_wi_lock));
  161. if (pmp_wi_cntx->bmpdrv_unload)
  162. NdisSetEvent(&(pmp_wi_cntx->mp_wi_evt));
  163. }
  164. #endif
  165. static int init_mp_priv_by_os(struct mp_priv *pmp_priv)
  166. {
  167. struct mp_wi_cntx *pmp_wi_cntx;
  168. if (pmp_priv == NULL)
  169. return _FAIL;
  170. pmp_priv->rx_testcnt = 0;
  171. pmp_priv->rx_testcnt1 = 0;
  172. pmp_priv->rx_testcnt2 = 0;
  173. pmp_priv->tx_testcnt = 0;
  174. pmp_priv->tx_testcnt1 = 0;
  175. pmp_wi_cntx = &pmp_priv->wi_cntx
  176. pmp_wi_cntx->bmpdrv_unload = _FALSE;
  177. pmp_wi_cntx->bmp_wi_progress = _FALSE;
  178. pmp_wi_cntx->curractfunc = NULL;
  179. return _SUCCESS;
  180. }
  181. #endif
  182. #ifdef PLATFORM_LINUX
  183. static int init_mp_priv_by_os(struct mp_priv *pmp_priv)
  184. {
  185. int i, res;
  186. struct mp_xmit_frame *pmp_xmitframe;
  187. if (pmp_priv == NULL)
  188. return _FAIL;
  189. _rtw_init_queue(&pmp_priv->free_mp_xmitqueue);
  190. pmp_priv->pallocated_mp_xmitframe_buf = NULL;
  191. pmp_priv->pallocated_mp_xmitframe_buf = rtw_zmalloc(NR_MP_XMITFRAME * sizeof(struct mp_xmit_frame) + 4);
  192. if (pmp_priv->pallocated_mp_xmitframe_buf == NULL) {
  193. res = _FAIL;
  194. goto _exit_init_mp_priv;
  195. }
  196. pmp_priv->pmp_xmtframe_buf = pmp_priv->pallocated_mp_xmitframe_buf + 4 - ((SIZE_PTR)(pmp_priv->pallocated_mp_xmitframe_buf) & 3);
  197. pmp_xmitframe = (struct mp_xmit_frame *)pmp_priv->pmp_xmtframe_buf;
  198. for (i = 0; i < NR_MP_XMITFRAME; i++) {
  199. _rtw_init_listhead(&pmp_xmitframe->list);
  200. rtw_list_insert_tail(&pmp_xmitframe->list, &pmp_priv->free_mp_xmitqueue.queue);
  201. pmp_xmitframe->pkt = NULL;
  202. pmp_xmitframe->frame_tag = MP_FRAMETAG;
  203. pmp_xmitframe->padapter = pmp_priv->papdater;
  204. pmp_xmitframe++;
  205. }
  206. pmp_priv->free_mp_xmitframe_cnt = NR_MP_XMITFRAME;
  207. res = _SUCCESS;
  208. _exit_init_mp_priv:
  209. return res;
  210. }
  211. #endif
  212. static void mp_init_xmit_attrib(struct mp_tx *pmptx, PADAPTER padapter)
  213. {
  214. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
  215. struct pkt_attrib *pattrib;
  216. /* init xmitframe attribute */
  217. pattrib = &pmptx->attrib;
  218. _rtw_memset(pattrib, 0, sizeof(struct pkt_attrib));
  219. _rtw_memset(pmptx->desc, 0, TXDESC_SIZE);
  220. pattrib->ether_type = 0x8712;
  221. #if 0
  222. _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
  223. _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
  224. #endif
  225. _rtw_memset(pattrib->dst, 0xFF, ETH_ALEN);
  226. /* pattrib->dhcp_pkt = 0;
  227. * pattrib->pktlen = 0; */
  228. pattrib->ack_policy = 0;
  229. /* pattrib->pkt_hdrlen = ETH_HLEN; */
  230. pattrib->hdrlen = WLAN_HDR_A3_LEN;
  231. pattrib->subtype = WIFI_DATA;
  232. pattrib->priority = 0;
  233. pattrib->qsel = pattrib->priority;
  234. /* do_queue_select(padapter, pattrib); */
  235. pattrib->nr_frags = 1;
  236. pattrib->encrypt = 0;
  237. pattrib->bswenc = _FALSE;
  238. pattrib->qos_en = _FALSE;
  239. pattrib->pktlen = 1500;
  240. #ifdef CONFIG_80211AC_VHT
  241. if (pHalData->rf_type == RF_1T1R)
  242. pattrib->raid = RATEID_IDX_VHT_1SS;
  243. else if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_2T4R)
  244. pattrib->raid = RATEID_IDX_VHT_2SS;
  245. else if (pHalData->rf_type == RF_3T3R)
  246. pattrib->raid = RATEID_IDX_VHT_3SS;
  247. else
  248. pattrib->raid = RATEID_IDX_BGN_40M_1SS;
  249. #endif
  250. }
  251. s32 init_mp_priv(PADAPTER padapter)
  252. {
  253. struct mp_priv *pmppriv = &padapter->mppriv;
  254. PHAL_DATA_TYPE pHalData;
  255. pHalData = GET_HAL_DATA(padapter);
  256. _init_mp_priv_(pmppriv);
  257. pmppriv->papdater = padapter;
  258. pmppriv->mp_dm = 0;
  259. pmppriv->tx.stop = 1;
  260. pmppriv->bSetTxPower = 0; /*for manually set tx power*/
  261. pmppriv->bTxBufCkFail = _FALSE;
  262. pmppriv->pktInterval = 0;
  263. pmppriv->pktLength = 1000;
  264. mp_init_xmit_attrib(&pmppriv->tx, padapter);
  265. switch (padapter->registrypriv.rf_config) {
  266. case RF_1T1R:
  267. pmppriv->antenna_tx = ANTENNA_A;
  268. pmppriv->antenna_rx = ANTENNA_A;
  269. break;
  270. case RF_1T2R:
  271. default:
  272. pmppriv->antenna_tx = ANTENNA_A;
  273. pmppriv->antenna_rx = ANTENNA_AB;
  274. break;
  275. case RF_2T2R:
  276. case RF_2T2R_GREEN:
  277. pmppriv->antenna_tx = ANTENNA_AB;
  278. pmppriv->antenna_rx = ANTENNA_AB;
  279. break;
  280. case RF_2T4R:
  281. pmppriv->antenna_tx = ANTENNA_BC;
  282. pmppriv->antenna_rx = ANTENNA_ABCD;
  283. break;
  284. }
  285. pHalData->AntennaRxPath = pmppriv->antenna_rx;
  286. pHalData->antenna_tx_path = pmppriv->antenna_tx;
  287. return _SUCCESS;
  288. }
  289. void free_mp_priv(struct mp_priv *pmp_priv)
  290. {
  291. if (pmp_priv->pallocated_mp_xmitframe_buf) {
  292. rtw_mfree(pmp_priv->pallocated_mp_xmitframe_buf, 0);
  293. pmp_priv->pallocated_mp_xmitframe_buf = NULL;
  294. }
  295. pmp_priv->pmp_xmtframe_buf = NULL;
  296. }
  297. static VOID PHY_IQCalibrate_default(
  298. IN PADAPTER pAdapter,
  299. IN BOOLEAN bReCovery
  300. )
  301. {
  302. RTW_INFO("%s\n", __func__);
  303. }
  304. static VOID PHY_LCCalibrate_default(
  305. IN PADAPTER pAdapter
  306. )
  307. {
  308. RTW_INFO("%s\n", __func__);
  309. }
  310. static VOID PHY_SetRFPathSwitch_default(
  311. IN PADAPTER pAdapter,
  312. IN BOOLEAN bMain
  313. )
  314. {
  315. RTW_INFO("%s\n", __func__);
  316. }
  317. void mpt_InitHWConfig(PADAPTER Adapter)
  318. {
  319. if (IS_HARDWARE_TYPE_8723B(Adapter)) {
  320. /* TODO: <20130114, Kordan> The following setting is only for DPDT and Fixed board type. */
  321. /* TODO: A better solution is configure it according EFUSE during the run-time. */
  322. phy_set_mac_reg(Adapter, 0x64, BIT20, 0x0); /* 0x66[4]=0 */
  323. phy_set_mac_reg(Adapter, 0x64, BIT24, 0x0); /* 0x66[8]=0 */
  324. phy_set_mac_reg(Adapter, 0x40, BIT4, 0x0); /* 0x40[4]=0 */
  325. phy_set_mac_reg(Adapter, 0x40, BIT3, 0x1); /* 0x40[3]=1 */
  326. phy_set_mac_reg(Adapter, 0x4C, BIT24, 0x1); /* 0x4C[24:23]=10 */
  327. phy_set_mac_reg(Adapter, 0x4C, BIT23, 0x0); /* 0x4C[24:23]=10 */
  328. phy_set_bb_reg(Adapter, 0x944, BIT1 | BIT0, 0x3); /* 0x944[1:0]=11 */
  329. phy_set_bb_reg(Adapter, 0x930, bMaskByte0, 0x77);/* 0x930[7:0]=77 */
  330. phy_set_mac_reg(Adapter, 0x38, BIT11, 0x1);/* 0x38[11]=1 */
  331. /* TODO: <20130206, Kordan> The default setting is wrong, hard-coded here. */
  332. phy_set_mac_reg(Adapter, 0x778, 0x3, 0x3); /* Turn off hardware PTA control (Asked by Scott) */
  333. phy_set_mac_reg(Adapter, 0x64, bMaskDWord, 0x36000000);/* Fix BT S0/S1 */
  334. phy_set_mac_reg(Adapter, 0x948, bMaskDWord, 0x0); /* Fix BT can't Tx */
  335. /* <20130522, Kordan> Turn off equalizer to improve Rx sensitivity. (Asked by EEChou) */
  336. phy_set_bb_reg(Adapter, 0xA00, BIT8, 0x0); /*0xA01[0] = 0*/
  337. } else if (IS_HARDWARE_TYPE_8821(Adapter)) {
  338. /* <20131121, VincentL> Add for 8821AU DPDT setting and fix switching antenna issue (Asked by Rock)
  339. <20131122, VincentL> Enable for all 8821A/8811AU (Asked by Alex)*/
  340. phy_set_mac_reg(Adapter, 0x4C, BIT23, 0x0); /*0x4C[23:22]=01*/
  341. phy_set_mac_reg(Adapter, 0x4C, BIT22, 0x1); /*0x4C[23:22]=01*/
  342. } else if (IS_HARDWARE_TYPE_8188ES(Adapter))
  343. phy_set_mac_reg(Adapter, 0x4C , BIT23, 0); /*select DPDT_P and DPDT_N as output pin*/
  344. #ifdef CONFIG_RTL8814A
  345. else if (IS_HARDWARE_TYPE_8814A(Adapter))
  346. PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8814A, 0x2000);
  347. #endif
  348. #ifdef CONFIG_RTL8822B
  349. else if (IS_HARDWARE_TYPE_8822B(Adapter)) {
  350. u32 tmp_reg = 0;
  351. PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8822B, 0x2000);
  352. /* fixed wifi can't 2.4g tx suggest by Szuyitasi 20160504 */
  353. phy_set_bb_reg(Adapter, 0x70, bMaskByte3, 0x0e);
  354. RTW_INFO(" 0x73 = 0x%x\n", phy_query_bb_reg(Adapter, 0x70, bMaskByte3));
  355. phy_set_bb_reg(Adapter, 0x1704, bMaskDWord, 0x0000ff00);
  356. RTW_INFO(" 0x1704 = 0x%x\n", phy_query_bb_reg(Adapter, 0x1704, bMaskDWord));
  357. phy_set_bb_reg(Adapter, 0x1700, bMaskDWord, 0xc00f0038);
  358. RTW_INFO(" 0x1700 = 0x%x\n", phy_query_bb_reg(Adapter, 0x1700, bMaskDWord));
  359. }
  360. #endif /* CONFIG_RTL8822B */
  361. #ifdef CONFIG_RTL8821C
  362. else if (IS_HARDWARE_TYPE_8821C(Adapter))
  363. PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8821C, 0x2000);
  364. #endif /* CONFIG_RTL8821C */
  365. }
  366. static void PHY_IQCalibrate(PADAPTER padapter, u8 bReCovery)
  367. {
  368. PHAL_DATA_TYPE pHalData;
  369. u8 b2ant; /* false:1ant, true:2-ant */
  370. u8 RF_Path; /* 0:S1, 1:S0 */
  371. if (IS_HARDWARE_TYPE_8723B(padapter)) {
  372. #ifdef CONFIG_RTL8723B
  373. pHalData = GET_HAL_DATA(padapter);
  374. b2ant = pHalData->EEPROMBluetoothAntNum == Ant_x2 ? _TRUE : _FALSE;
  375. phy_iq_calibrate_8723b(padapter, bReCovery, _FALSE, b2ant, pHalData->ant_path);
  376. #endif
  377. } else if (IS_HARDWARE_TYPE_8188E(padapter)) {
  378. #ifdef CONFIG_RTL8188E
  379. phy_iq_calibrate_8188e(padapter, bReCovery);
  380. #endif
  381. } else if (IS_HARDWARE_TYPE_8814A(padapter)) {
  382. #ifdef CONFIG_RTL8814A
  383. phy_iq_calibrate_8814a(&(GET_HAL_DATA(padapter)->odmpriv), bReCovery);
  384. #endif
  385. } else if (IS_HARDWARE_TYPE_8812(padapter)) {
  386. #ifdef CONFIG_RTL8812A
  387. phy_iq_calibrate_8812a(padapter, bReCovery);
  388. #endif
  389. } else if (IS_HARDWARE_TYPE_8821(padapter)) {
  390. #ifdef CONFIG_RTL8821A
  391. phy_iq_calibrate_8821a(&(GET_HAL_DATA(padapter)->odmpriv), bReCovery);
  392. #endif
  393. } else if (IS_HARDWARE_TYPE_8192E(padapter)) {
  394. #ifdef CONFIG_RTL8192E
  395. phy_iq_calibrate_8192e(padapter, bReCovery);
  396. #endif
  397. } else if (IS_HARDWARE_TYPE_8703B(padapter)) {
  398. #ifdef CONFIG_RTL8703B
  399. phy_iq_calibrate_8703b(padapter, bReCovery);
  400. #endif
  401. } else if (IS_HARDWARE_TYPE_8188F(padapter)) {
  402. #ifdef CONFIG_RTL8188F
  403. phy_iq_calibrate_8188f(padapter, bReCovery, _FALSE);
  404. #endif
  405. } else if (IS_HARDWARE_TYPE_8822B(padapter)) {
  406. #ifdef CONFIG_RTL8822B
  407. phy_iq_calibrate_8822b(&(GET_HAL_DATA(padapter)->odmpriv), bReCovery);
  408. #endif
  409. } else if (IS_HARDWARE_TYPE_8723D(padapter)) {
  410. #ifdef CONFIG_RTL8723D
  411. phy_iq_calibrate_8723d(padapter, bReCovery);
  412. #endif
  413. } else if (IS_HARDWARE_TYPE_8821C(padapter)) {
  414. #ifdef CONFIG_RTL8821C
  415. phy_iq_calibrate_8821c(&(GET_HAL_DATA(padapter)->odmpriv), bReCovery);
  416. #endif
  417. }
  418. }
  419. static void PHY_LCCalibrate(PADAPTER padapter)
  420. {
  421. if (IS_HARDWARE_TYPE_8723B(padapter)) {
  422. #ifdef CONFIG_RTL8723B
  423. phy_lc_calibrate_8723b(&(GET_HAL_DATA(padapter)->odmpriv));
  424. #endif
  425. } else if (IS_HARDWARE_TYPE_8188E(padapter)) {
  426. #ifdef CONFIG_RTL8188E
  427. phy_lc_calibrate_8188e(&(GET_HAL_DATA(padapter)->odmpriv));
  428. #endif
  429. } else if (IS_HARDWARE_TYPE_8814A(padapter)) {
  430. #ifdef CONFIG_RTL8814A
  431. phy_lc_calibrate_8814a(&(GET_HAL_DATA(padapter)->odmpriv));
  432. #endif
  433. } else if (IS_HARDWARE_TYPE_8812(padapter)) {
  434. #ifdef CONFIG_RTL8812A
  435. phy_lc_calibrate_8812a(&(GET_HAL_DATA(padapter)->odmpriv));
  436. #endif
  437. } else if (IS_HARDWARE_TYPE_8821(padapter)) {
  438. #ifdef CONFIG_RTL8821A
  439. phy_lc_calibrate_8821a(&(GET_HAL_DATA(padapter)->odmpriv));
  440. #endif
  441. } else if (IS_HARDWARE_TYPE_8192E(padapter)) {
  442. #ifdef CONFIG_RTL8192E
  443. phy_lc_calibrate_8192e(&(GET_HAL_DATA(padapter)->odmpriv));
  444. #endif
  445. } else if (IS_HARDWARE_TYPE_8703B(padapter)) {
  446. #ifdef CONFIG_RTL8703B
  447. phy_lc_calibrate_8703b(&(GET_HAL_DATA(padapter)->odmpriv));
  448. #endif
  449. } else if (IS_HARDWARE_TYPE_8188F(padapter)) {
  450. #ifdef CONFIG_RTL8188F
  451. phy_lc_calibrate_8188f(&(GET_HAL_DATA(padapter)->odmpriv));
  452. #endif
  453. } else if (IS_HARDWARE_TYPE_8822B(padapter)) {
  454. #ifdef CONFIG_RTL8822B
  455. phy_lc_calibrate_8822b(&(GET_HAL_DATA(padapter)->odmpriv));
  456. #endif
  457. } else if (IS_HARDWARE_TYPE_8723D(padapter)) {
  458. #ifdef CONFIG_RTL8723D
  459. phy_lc_calibrate_8723d(&(GET_HAL_DATA(padapter)->odmpriv));
  460. #endif
  461. } else if (IS_HARDWARE_TYPE_8821C(padapter)) {
  462. #ifdef CONFIG_RTL8821C
  463. /*phy_iq_calibrate_8821c(&(GET_HAL_DATA(padapter)->odmpriv));*/
  464. #endif
  465. }
  466. }
  467. static u8 PHY_QueryRFPathSwitch(PADAPTER padapter)
  468. {
  469. u8 bmain = 0;
  470. /*
  471. if (IS_HARDWARE_TYPE_8723B(padapter)) {
  472. #ifdef CONFIG_RTL8723B
  473. bmain = PHY_QueryRFPathSwitch_8723B(padapter);
  474. #endif
  475. } else if (IS_HARDWARE_TYPE_8188E(padapter)) {
  476. #ifdef CONFIG_RTL8188E
  477. bmain = PHY_QueryRFPathSwitch_8188E(padapter);
  478. #endif
  479. } else if (IS_HARDWARE_TYPE_8814A(padapter)) {
  480. #ifdef CONFIG_RTL8814A
  481. bmain = PHY_QueryRFPathSwitch_8814A(padapter);
  482. #endif
  483. } else if (IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter)) {
  484. #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
  485. bmain = PHY_QueryRFPathSwitch_8812A(padapter);
  486. #endif
  487. } else if (IS_HARDWARE_TYPE_8192E(padapter)) {
  488. #ifdef CONFIG_RTL8192E
  489. bmain = PHY_QueryRFPathSwitch_8192E(padapter);
  490. #endif
  491. } else if (IS_HARDWARE_TYPE_8703B(padapter)) {
  492. #ifdef CONFIG_RTL8703B
  493. bmain = PHY_QueryRFPathSwitch_8703B(padapter);
  494. #endif
  495. } else if (IS_HARDWARE_TYPE_8188F(padapter)) {
  496. #ifdef CONFIG_RTL8188F
  497. bmain = PHY_QueryRFPathSwitch_8188F(padapter);
  498. #endif
  499. } else if (IS_HARDWARE_TYPE_8822B(padapter)) {
  500. #ifdef CONFIG_RTL8822B
  501. bmain = PHY_QueryRFPathSwitch_8822B(padapter);
  502. #endif
  503. } else if (IS_HARDWARE_TYPE_8723D(padapter)) {
  504. #ifdef CONFIG_RTL8723D
  505. bmain = PHY_QueryRFPathSwitch_8723D(padapter);
  506. #endif
  507. } else
  508. */
  509. if (IS_HARDWARE_TYPE_8821C(padapter)) {
  510. #ifdef CONFIG_RTL8821C
  511. bmain = phy_query_rf_path_switch_8821c(padapter);
  512. #endif
  513. }
  514. return bmain;
  515. }
  516. static void PHY_SetRFPathSwitch(PADAPTER padapter , BOOLEAN bMain) {
  517. if (IS_HARDWARE_TYPE_8723B(padapter)) {
  518. #ifdef CONFIG_RTL8723B
  519. phy_set_rf_path_switch_8723b(padapter, bMain);
  520. #endif
  521. } else if (IS_HARDWARE_TYPE_8188E(padapter)) {
  522. #ifdef CONFIG_RTL8188E
  523. phy_set_rf_path_switch_8188e(padapter, bMain);
  524. #endif
  525. } else if (IS_HARDWARE_TYPE_8814A(padapter)) {
  526. #ifdef CONFIG_RTL8814A
  527. phy_set_rf_path_switch_8814a(padapter, bMain);
  528. #endif
  529. } else if (IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter)) {
  530. #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
  531. phy_set_rf_path_switch_8812a(padapter, bMain);
  532. #endif
  533. } else if (IS_HARDWARE_TYPE_8192E(padapter)) {
  534. #ifdef CONFIG_RTL8192E
  535. phy_set_rf_path_switch_8192e(padapter, bMain);
  536. #endif
  537. } else if (IS_HARDWARE_TYPE_8703B(padapter)) {
  538. #ifdef CONFIG_RTL8703B
  539. phy_set_rf_path_switch_8703b(padapter, bMain);
  540. #endif
  541. } else if (IS_HARDWARE_TYPE_8188F(padapter)) {
  542. #ifdef CONFIG_RTL8188F
  543. phy_set_rf_path_switch_8188f(padapter, bMain);
  544. #endif
  545. } else if (IS_HARDWARE_TYPE_8822B(padapter)) {
  546. #ifdef CONFIG_RTL8822B
  547. phy_set_rf_path_switch_8822b(padapter, bMain);
  548. #endif
  549. } else if (IS_HARDWARE_TYPE_8723D(padapter)) {
  550. #ifdef CONFIG_RTL8723D
  551. phy_set_rf_path_switch_8723d(padapter, bMain);
  552. #endif
  553. } else if (IS_HARDWARE_TYPE_8821C(padapter)) {
  554. #ifdef CONFIG_RTL8821C
  555. phy_set_rf_path_switch_8821c(padapter, bMain);
  556. #endif
  557. }
  558. }
  559. s32
  560. MPT_InitializeAdapter(
  561. IN PADAPTER pAdapter,
  562. IN u8 Channel
  563. )
  564. {
  565. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
  566. s32 rtStatus = _SUCCESS;
  567. PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.mpt_ctx;
  568. u32 ledsetting;
  569. struct mlme_priv *pmlmepriv = &pAdapter->mlmepriv;
  570. pMptCtx->bMptDrvUnload = _FALSE;
  571. pMptCtx->bMassProdTest = _FALSE;
  572. pMptCtx->bMptIndexEven = _TRUE; /* default gain index is -6.0db */
  573. pMptCtx->h2cReqNum = 0x0;
  574. /* init for BT MP */
  575. #if defined(CONFIG_RTL8723B)
  576. pMptCtx->bMPh2c_timeout = _FALSE;
  577. pMptCtx->MptH2cRspEvent = _FALSE;
  578. pMptCtx->MptBtC2hEvent = _FALSE;
  579. _rtw_init_sema(&pMptCtx->MPh2c_Sema, 0);
  580. rtw_init_timer(&pMptCtx->MPh2c_timeout_timer, pAdapter, MPh2c_timeout_handle, pAdapter);
  581. #endif
  582. mpt_InitHWConfig(pAdapter);
  583. #ifdef CONFIG_RTL8723B
  584. rtl8723b_InitAntenna_Selection(pAdapter);
  585. if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
  586. /* <20130522, Kordan> Turn off equalizer to improve Rx sensitivity. (Asked by EEChou)*/
  587. phy_set_bb_reg(pAdapter, 0xA00, BIT8, 0x0);
  588. PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); /*default use Main*/
  589. /*<20130522, Kordan> 0x51 and 0x71 should be set immediately after path switched, or they might be overwritten. */
  590. if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90))
  591. phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E);
  592. else
  593. phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E);
  594. }
  595. /*set ant to wifi side in mp mode*/
  596. rtw_write16(pAdapter, 0x870, 0x300);
  597. rtw_write16(pAdapter, 0x860, 0x110);
  598. #endif
  599. pMptCtx->bMptWorkItemInProgress = _FALSE;
  600. pMptCtx->CurrMptAct = NULL;
  601. pMptCtx->mpt_rf_path = ODM_RF_PATH_A;
  602. /* ------------------------------------------------------------------------- */
  603. /* Don't accept any packets */
  604. rtw_write32(pAdapter, REG_RCR, 0);
  605. /* ledsetting = rtw_read32(pAdapter, REG_LEDCFG0); */
  606. /* rtw_write32(pAdapter, REG_LEDCFG0, ledsetting & ~LED0DIS); */
  607. /* rtw_write32(pAdapter, REG_LEDCFG0, 0x08080); */
  608. ledsetting = rtw_read32(pAdapter, REG_LEDCFG0);
  609. PHY_LCCalibrate(pAdapter);
  610. PHY_IQCalibrate(pAdapter, _FALSE);
  611. /* dm_check_txpowertracking(&pHalData->odmpriv); */ /* trigger thermal meter */
  612. PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); /* default use Main */
  613. pMptCtx->backup0xc50 = (u1Byte)phy_query_bb_reg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0);
  614. pMptCtx->backup0xc58 = (u1Byte)phy_query_bb_reg(pAdapter, rOFDM0_XBAGCCore1, bMaskByte0);
  615. pMptCtx->backup0xc30 = (u1Byte)phy_query_bb_reg(pAdapter, rOFDM0_RxDetector1, bMaskByte0);
  616. pMptCtx->backup0x52_RF_A = (u1Byte)phy_query_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
  617. pMptCtx->backup0x52_RF_B = (u1Byte)phy_query_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0);
  618. #ifdef CONFIG_RTL8188E
  619. rtw_write32(pAdapter, REG_MACID_NO_LINK_0, 0x0);
  620. rtw_write32(pAdapter, REG_MACID_NO_LINK_1, 0x0);
  621. #endif
  622. #ifdef CONFIG_RTL8814A
  623. if (IS_HARDWARE_TYPE_8814A(pAdapter)) {
  624. pHalData->BackUp_IG_REG_4_Chnl_Section[0] = (u1Byte)phy_query_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0);
  625. pHalData->BackUp_IG_REG_4_Chnl_Section[1] = (u1Byte)phy_query_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0);
  626. pHalData->BackUp_IG_REG_4_Chnl_Section[2] = (u1Byte)phy_query_bb_reg(pAdapter, rC_IGI_Jaguar2, bMaskByte0);
  627. pHalData->BackUp_IG_REG_4_Chnl_Section[3] = (u1Byte)phy_query_bb_reg(pAdapter, rD_IGI_Jaguar2, bMaskByte0);
  628. }
  629. #endif
  630. return rtStatus;
  631. }
  632. /*-----------------------------------------------------------------------------
  633. * Function: MPT_DeInitAdapter()
  634. *
  635. * Overview: Extra DeInitialization for Mass Production Test.
  636. *
  637. * Input: PADAPTER pAdapter
  638. *
  639. * Output: NONE
  640. *
  641. * Return: NONE
  642. *
  643. * Revised History:
  644. * When Who Remark
  645. * 05/08/2007 MHC Create Version 0.
  646. * 05/18/2007 MHC Add normal driver MPHalt code.
  647. *
  648. *---------------------------------------------------------------------------*/
  649. VOID
  650. MPT_DeInitAdapter(
  651. IN PADAPTER pAdapter
  652. )
  653. {
  654. PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.mpt_ctx;
  655. pMptCtx->bMptDrvUnload = _TRUE;
  656. #if defined(CONFIG_RTL8723B)
  657. _rtw_free_sema(&(pMptCtx->MPh2c_Sema));
  658. _cancel_timer_ex(&pMptCtx->MPh2c_timeout_timer);
  659. #endif
  660. #if defined(CONFIG_RTL8723B)
  661. phy_set_bb_reg(pAdapter, 0xA01, BIT0, 1); /* /suggestion by jerry for MP Rx. */
  662. #endif
  663. #if 0 /* for Windows */
  664. PlatformFreeWorkItem(&(pMptCtx->MptWorkItem));
  665. while (pMptCtx->bMptWorkItemInProgress) {
  666. if (NdisWaitEvent(&(pMptCtx->MptWorkItemEvent), 50))
  667. break;
  668. }
  669. NdisFreeSpinLock(&(pMptCtx->MptWorkItemSpinLock));
  670. #endif
  671. }
  672. static u8 mpt_ProStartTest(PADAPTER padapter)
  673. {
  674. PMPT_CONTEXT pMptCtx = &padapter->mppriv.mpt_ctx;
  675. pMptCtx->bMassProdTest = _TRUE;
  676. pMptCtx->is_start_cont_tx = _FALSE;
  677. pMptCtx->bCckContTx = _FALSE;
  678. pMptCtx->bOfdmContTx = _FALSE;
  679. pMptCtx->bSingleCarrier = _FALSE;
  680. pMptCtx->is_carrier_suppression = _FALSE;
  681. pMptCtx->is_single_tone = _FALSE;
  682. pMptCtx->HWTxmode = PACKETS_TX;
  683. return _SUCCESS;
  684. }
  685. /*
  686. * General use
  687. */
  688. s32 SetPowerTracking(PADAPTER padapter, u8 enable)
  689. {
  690. hal_mpt_SetPowerTracking(padapter, enable);
  691. return 0;
  692. }
  693. void GetPowerTracking(PADAPTER padapter, u8 *enable)
  694. {
  695. hal_mpt_GetPowerTracking(padapter, enable);
  696. }
  697. void rtw_mp_trigger_iqk(PADAPTER padapter)
  698. {
  699. PHY_IQCalibrate(padapter, _FALSE);
  700. }
  701. void rtw_mp_trigger_lck(PADAPTER padapter)
  702. {
  703. PHY_LCCalibrate(padapter);
  704. }
  705. static void disable_dm(PADAPTER padapter)
  706. {
  707. u8 v8;
  708. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
  709. struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv;
  710. /* 3 1. disable firmware dynamic mechanism */
  711. /* disable Power Training, Rate Adaptive */
  712. v8 = rtw_read8(padapter, REG_BCN_CTRL);
  713. v8 &= ~EN_BCN_FUNCTION;
  714. rtw_write8(padapter, REG_BCN_CTRL, v8);
  715. /* 3 2. disable driver dynamic mechanism */
  716. rtw_phydm_func_disable_all(padapter);
  717. /* enable APK, LCK and IQK but disable power tracking */
  718. pDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE;
  719. rtw_phydm_func_set(padapter, ODM_RF_CALIBRATION);
  720. /* #ifdef CONFIG_BT_COEXIST */
  721. /* rtw_btcoex_Switch(padapter, 0); */ /* remove for BT MP Down. */
  722. /* #endif */
  723. }
  724. void MPT_PwrCtlDM(PADAPTER padapter, u32 bstart)
  725. {
  726. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
  727. struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv;
  728. if (bstart == 1) {
  729. RTW_INFO("in MPT_PwrCtlDM start\n");
  730. rtw_phydm_func_set(padapter, ODM_RF_TX_PWR_TRACK);
  731. pDM_Odm->rf_calibrate_info.txpowertrack_control = _TRUE;
  732. padapter->mppriv.mp_dm = 1;
  733. } else {
  734. RTW_INFO("in MPT_PwrCtlDM stop\n");
  735. rtw_phydm_func_clr(padapter, ODM_RF_TX_PWR_TRACK);
  736. pDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE;
  737. padapter->mppriv.mp_dm = 0;
  738. {
  739. struct _TXPWRTRACK_CFG c;
  740. u1Byte chnl = 0 ;
  741. _rtw_memset(&c, 0, sizeof(struct _TXPWRTRACK_CFG));
  742. configure_txpower_track(pDM_Odm, &c);
  743. odm_clear_txpowertracking_state(pDM_Odm);
  744. if (*c.odm_tx_pwr_track_set_pwr) {
  745. if (pDM_Odm->support_ic_type == ODM_RTL8188F)
  746. (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, chnl);
  747. else if (pDM_Odm->support_ic_type == ODM_RTL8723D) {
  748. (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, ODM_RF_PATH_A, chnl);
  749. SetTxPower(padapter);
  750. } else {
  751. (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, ODM_RF_PATH_A, chnl);
  752. (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, ODM_RF_PATH_B, chnl);
  753. }
  754. }
  755. }
  756. }
  757. }
  758. u32 mp_join(PADAPTER padapter, u8 mode)
  759. {
  760. WLAN_BSSID_EX bssid;
  761. struct sta_info *psta;
  762. u32 length;
  763. u8 val8, join_type;
  764. _irqL irqL;
  765. s32 res = _SUCCESS;
  766. struct mp_priv *pmppriv = &padapter->mppriv;
  767. struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
  768. struct wlan_network *tgt_network = &pmlmepriv->cur_network;
  769. struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
  770. struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
  771. WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));
  772. #ifdef CONFIG_IOCTL_CFG80211
  773. struct wireless_dev *pwdev = padapter->rtw_wdev;
  774. #endif /* #ifdef CONFIG_IOCTL_CFG80211 */
  775. /* 1. initialize a new WLAN_BSSID_EX */
  776. _rtw_memset(&bssid, 0, sizeof(WLAN_BSSID_EX));
  777. RTW_INFO("%s ,pmppriv->network_macaddr=%x %x %x %x %x %x\n", __func__,
  778. pmppriv->network_macaddr[0], pmppriv->network_macaddr[1], pmppriv->network_macaddr[2], pmppriv->network_macaddr[3], pmppriv->network_macaddr[4],
  779. pmppriv->network_macaddr[5]);
  780. _rtw_memcpy(bssid.MacAddress, pmppriv->network_macaddr, ETH_ALEN);
  781. if (mode == WIFI_FW_ADHOC_STATE) {
  782. bssid.Ssid.SsidLength = strlen("mp_pseudo_adhoc");
  783. _rtw_memcpy(bssid.Ssid.Ssid, (u8 *)"mp_pseudo_adhoc", bssid.Ssid.SsidLength);
  784. bssid.InfrastructureMode = Ndis802_11IBSS;
  785. bssid.NetworkTypeInUse = Ndis802_11DS;
  786. bssid.IELength = 0;
  787. bssid.Configuration.DSConfig = pmppriv->channel;
  788. } else if (mode == WIFI_FW_STATION_STATE) {
  789. bssid.Ssid.SsidLength = strlen("mp_pseudo_STATION");
  790. _rtw_memcpy(bssid.Ssid.Ssid, (u8 *)"mp_pseudo_STATION", bssid.Ssid.SsidLength);
  791. bssid.InfrastructureMode = Ndis802_11Infrastructure;
  792. bssid.NetworkTypeInUse = Ndis802_11DS;
  793. bssid.IELength = 0;
  794. }
  795. length = get_WLAN_BSSID_EX_sz(&bssid);
  796. if (length % 4)
  797. bssid.Length = ((length >> 2) + 1) << 2; /* round up to multiple of 4 bytes. */
  798. else
  799. bssid.Length = length;
  800. _enter_critical_bh(&pmlmepriv->lock, &irqL);
  801. if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE)
  802. goto end_of_mp_start_test;
  803. /* init mp_start_test status */
  804. if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {
  805. rtw_disassoc_cmd(padapter, 500, 0);
  806. rtw_indicate_disconnect(padapter, 0, _FALSE);
  807. rtw_free_assoc_resources(padapter, 1);
  808. }
  809. pmppriv->prev_fw_state = get_fwstate(pmlmepriv);
  810. /*pmlmepriv->fw_state = WIFI_MP_STATE;*/
  811. init_fwstate(pmlmepriv, WIFI_MP_STATE);
  812. set_fwstate(pmlmepriv, _FW_UNDER_LINKING);
  813. /* 3 2. create a new psta for mp driver */
  814. /* clear psta in the cur_network, if any */
  815. psta = rtw_get_stainfo(&padapter->stapriv, tgt_network->network.MacAddress);
  816. if (psta)
  817. rtw_free_stainfo(padapter, psta);
  818. psta = rtw_alloc_stainfo(&padapter->stapriv, bssid.MacAddress);
  819. if (psta == NULL) {
  820. /*pmlmepriv->fw_state = pmppriv->prev_fw_state;*/
  821. init_fwstate(pmlmepriv, pmppriv->prev_fw_state);
  822. res = _FAIL;
  823. goto end_of_mp_start_test;
  824. }
  825. if (mode == WIFI_FW_ADHOC_STATE)
  826. set_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
  827. else
  828. set_fwstate(pmlmepriv, WIFI_STATION_STATE);
  829. /* 3 3. join psudo AdHoc */
  830. tgt_network->join_res = 1;
  831. tgt_network->aid = psta->aid = 1;
  832. _rtw_memcpy(&padapter->registrypriv.dev_network, &bssid, length);
  833. rtw_update_registrypriv_dev_network(padapter);
  834. _rtw_memcpy(&tgt_network->network, &padapter->registrypriv.dev_network, padapter->registrypriv.dev_network.Length);
  835. _rtw_memcpy(pnetwork, &padapter->registrypriv.dev_network, padapter->registrypriv.dev_network.Length);
  836. rtw_indicate_connect(padapter);
  837. _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
  838. set_fwstate(pmlmepriv, _FW_LINKED);
  839. end_of_mp_start_test:
  840. _exit_critical_bh(&pmlmepriv->lock, &irqL);
  841. if (1) { /* (res == _SUCCESS) */
  842. /* set MSR to WIFI_FW_ADHOC_STATE */
  843. if (mode == WIFI_FW_ADHOC_STATE) {
  844. /* set msr to WIFI_FW_ADHOC_STATE */
  845. pmlmeinfo->state = WIFI_FW_ADHOC_STATE;
  846. Set_MSR(padapter, (pmlmeinfo->state & 0x3));
  847. rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, padapter->registrypriv.dev_network.MacAddress);
  848. join_type = 0;
  849. rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
  850. report_join_res(padapter, 1);
  851. pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS;
  852. } else {
  853. Set_MSR(padapter, WIFI_FW_STATION_STATE);
  854. RTW_INFO("%s , pmppriv->network_macaddr =%x %x %x %x %x %x\n", __func__,
  855. pmppriv->network_macaddr[0], pmppriv->network_macaddr[1], pmppriv->network_macaddr[2], pmppriv->network_macaddr[3], pmppriv->network_macaddr[4],
  856. pmppriv->network_macaddr[5]);
  857. rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmppriv->network_macaddr);
  858. }
  859. }
  860. return res;
  861. }
  862. /* This function initializes the DUT to the MP test mode */
  863. s32 mp_start_test(PADAPTER padapter)
  864. {
  865. struct mp_priv *pmppriv = &padapter->mppriv;
  866. s32 res = _SUCCESS;
  867. padapter->registrypriv.mp_mode = 1;
  868. /* 3 disable dynamic mechanism */
  869. disable_dm(padapter);
  870. #ifdef CONFIG_RTL8814A
  871. rtl8814_InitHalDm(padapter);
  872. #endif /* CONFIG_RTL8814A */
  873. #ifdef CONFIG_RTL8822B
  874. rtl8822b_phy_init_haldm(padapter);
  875. #endif /* CONFIG_RTL8822B */
  876. #ifdef CONFIG_RTL8821C
  877. rtl8821c_phy_init_haldm(padapter);
  878. #endif /* CONFIG_RTL8821C */
  879. #ifdef CONFIG_RTL8812A
  880. rtl8812_InitHalDm(padapter);
  881. #endif /* CONFIG_RTL8812A */
  882. #ifdef CONFIG_RTL8723B
  883. rtl8723b_InitHalDm(padapter);
  884. #endif /* CONFIG_RTL8723B */
  885. #ifdef CONFIG_RTL8703B
  886. rtl8703b_InitHalDm(padapter);
  887. #endif /* CONFIG_RTL8703B */
  888. #ifdef CONFIG_RTL8192E
  889. rtl8192e_InitHalDm(padapter);
  890. #endif
  891. #ifdef CONFIG_RTL8188F
  892. rtl8188f_InitHalDm(padapter);
  893. #endif
  894. #ifdef CONFIG_RTL8188E
  895. rtl8188e_InitHalDm(padapter);
  896. #endif
  897. #ifdef CONFIG_RTL8723D
  898. rtl8723d_InitHalDm(padapter);
  899. #endif /* CONFIG_RTL8723D */
  900. /* 3 0. update mp_priv */
  901. if (!RF_TYPE_VALID(padapter->registrypriv.rf_config)) {
  902. /* switch (phal->rf_type) { */
  903. switch (GET_RF_TYPE(padapter)) {
  904. case RF_1T1R:
  905. pmppriv->antenna_tx = ANTENNA_A;
  906. pmppriv->antenna_rx = ANTENNA_A;
  907. break;
  908. case RF_1T2R:
  909. default:
  910. pmppriv->antenna_tx = ANTENNA_A;
  911. pmppriv->antenna_rx = ANTENNA_AB;
  912. break;
  913. case RF_2T2R:
  914. case RF_2T2R_GREEN:
  915. pmppriv->antenna_tx = ANTENNA_AB;
  916. pmppriv->antenna_rx = ANTENNA_AB;
  917. break;
  918. case RF_2T4R:
  919. pmppriv->antenna_tx = ANTENNA_AB;
  920. pmppriv->antenna_rx = ANTENNA_ABCD;
  921. break;
  922. }
  923. }
  924. mpt_ProStartTest(padapter);
  925. mp_join(padapter, WIFI_FW_ADHOC_STATE);
  926. return res;
  927. }
  928. /* ------------------------------------------------------------------------------
  929. * This function change the DUT from the MP test mode into normal mode */
  930. void mp_stop_test(PADAPTER padapter)
  931. {
  932. struct mp_priv *pmppriv = &padapter->mppriv;
  933. struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
  934. struct wlan_network *tgt_network = &pmlmepriv->cur_network;
  935. struct sta_info *psta;
  936. _irqL irqL;
  937. if (pmppriv->mode == MP_ON) {
  938. pmppriv->bSetTxPower = 0;
  939. _enter_critical_bh(&pmlmepriv->lock, &irqL);
  940. if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _FALSE)
  941. goto end_of_mp_stop_test;
  942. /* 3 1. disconnect psudo AdHoc */
  943. rtw_indicate_disconnect(padapter, 0, _FALSE);
  944. /* 3 2. clear psta used in mp test mode.
  945. * rtw_free_assoc_resources(padapter, 1); */
  946. psta = rtw_get_stainfo(&padapter->stapriv, tgt_network->network.MacAddress);
  947. if (psta)
  948. rtw_free_stainfo(padapter, psta);
  949. /* 3 3. return to normal state (default:station mode) */
  950. /*pmlmepriv->fw_state = pmppriv->prev_fw_state; */ /* WIFI_STATION_STATE;*/
  951. init_fwstate(pmlmepriv, pmppriv->prev_fw_state);
  952. /* flush the cur_network */
  953. _rtw_memset(tgt_network, 0, sizeof(struct wlan_network));
  954. _clr_fwstate_(pmlmepriv, WIFI_MP_STATE);
  955. end_of_mp_stop_test:
  956. _exit_critical_bh(&pmlmepriv->lock, &irqL);
  957. #ifdef CONFIG_RTL8812A
  958. rtl8812_InitHalDm(padapter);
  959. #endif
  960. #ifdef CONFIG_RTL8723B
  961. rtl8723b_InitHalDm(padapter);
  962. #endif
  963. #ifdef CONFIG_RTL8703B
  964. rtl8703b_InitHalDm(padapter);
  965. #endif
  966. #ifdef CONFIG_RTL8192E
  967. rtl8192e_InitHalDm(padapter);
  968. #endif
  969. #ifdef CONFIG_RTL8188F
  970. rtl8188f_InitHalDm(padapter);
  971. #endif
  972. #ifdef CONFIG_RTL8723D
  973. rtl8723d_InitHalDm(padapter);
  974. #endif
  975. }
  976. }
  977. /*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/
  978. #if 0
  979. /* #ifdef CONFIG_USB_HCI */
  980. static VOID mpt_AdjustRFRegByRateByChan92CU(PADAPTER pAdapter, u8 RateIdx, u8 Channel, u8 BandWidthID)
  981. {
  982. u8 eRFPath;
  983. u32 rfReg0x26;
  984. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
  985. if (RateIdx < MPT_RATE_6M) /* CCK rate,for 88cu */
  986. rfReg0x26 = 0xf400;
  987. else if ((RateIdx >= MPT_RATE_6M) && (RateIdx <= MPT_RATE_54M)) {/* OFDM rate,for 88cu */
  988. if ((4 == Channel) || (8 == Channel) || (12 == Channel))
  989. rfReg0x26 = 0xf000;
  990. else if ((5 == Channel) || (7 == Channel) || (13 == Channel) || (14 == Channel))
  991. rfReg0x26 = 0xf400;
  992. else
  993. rfReg0x26 = 0x4f200;
  994. } else if ((RateIdx >= MPT_RATE_MCS0) && (RateIdx <= MPT_RATE_MCS15)) {
  995. /* MCS 20M ,for 88cu */ /* MCS40M rate,for 88cu */
  996. if (CHANNEL_WIDTH_20 == BandWidthID) {
  997. if ((4 == Channel) || (8 == Channel))
  998. rfReg0x26 = 0xf000;
  999. else if ((5 == Channel) || (7 == Channel) || (13 == Channel) || (14 == Channel))
  1000. rfReg0x26 = 0xf400;
  1001. else
  1002. rfReg0x26 = 0x4f200;
  1003. } else {
  1004. if ((4 == Channel) || (8 == Channel))
  1005. rfReg0x26 = 0xf000;
  1006. else if ((5 == Channel) || (7 == Channel))
  1007. rfReg0x26 = 0xf400;
  1008. else
  1009. rfReg0x26 = 0x4f200;
  1010. }
  1011. }
  1012. for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++)
  1013. write_rfreg(pAdapter, eRFPath, RF_SYN_G2, rfReg0x26);
  1014. }
  1015. #endif
  1016. /*-----------------------------------------------------------------------------
  1017. * Function: mpt_SwitchRfSetting
  1018. *
  1019. * Overview: Change RF Setting when we siwthc channel/rate/BW for MP.
  1020. *
  1021. * Input: IN PADAPTER pAdapter
  1022. *
  1023. * Output: NONE
  1024. *
  1025. * Return: NONE
  1026. *
  1027. * Revised History:
  1028. * When Who Remark
  1029. * 01/08/2009 MHC Suggestion from SD3 Willis for 92S series.
  1030. * 01/09/2009 MHC Add CCK modification for 40MHZ. Suggestion from SD3.
  1031. *
  1032. *---------------------------------------------------------------------------*/
  1033. static void mpt_SwitchRfSetting(PADAPTER pAdapter)
  1034. {
  1035. hal_mpt_SwitchRfSetting(pAdapter);
  1036. }
  1037. /*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/
  1038. /*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/
  1039. static void MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
  1040. {
  1041. hal_mpt_CCKTxPowerAdjust(Adapter, bInCH14);
  1042. }
  1043. /*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/
  1044. /*
  1045. * SetChannel
  1046. * Description
  1047. * Use H2C command to change channel,
  1048. * not only modify rf register, but also other setting need to be done.
  1049. */
  1050. void SetChannel(PADAPTER pAdapter)
  1051. {
  1052. hal_mpt_SetChannel(pAdapter);
  1053. }
  1054. /*
  1055. * Notice
  1056. * Switch bandwitdth may change center frequency(channel)
  1057. */
  1058. void SetBandwidth(PADAPTER pAdapter)
  1059. {
  1060. hal_mpt_SetBandwidth(pAdapter);
  1061. }
  1062. void SetAntenna(PADAPTER pAdapter)
  1063. {
  1064. hal_mpt_SetAntenna(pAdapter);
  1065. }
  1066. int SetTxPower(PADAPTER pAdapter)
  1067. {
  1068. hal_mpt_SetTxPower(pAdapter);
  1069. return _TRUE;
  1070. }
  1071. void SetTxAGCOffset(PADAPTER pAdapter, u32 ulTxAGCOffset)
  1072. {
  1073. u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D, tmpAGC;
  1074. TxAGCOffset_B = (ulTxAGCOffset & 0x000000ff);
  1075. TxAGCOffset_C = ((ulTxAGCOffset & 0x0000ff00) >> 8);
  1076. TxAGCOffset_D = ((ulTxAGCOffset & 0x00ff0000) >> 16);
  1077. tmpAGC = (TxAGCOffset_D << 8 | TxAGCOffset_C << 4 | TxAGCOffset_B);
  1078. write_bbreg(pAdapter, rFPGA0_TxGainStage,
  1079. (bXBTxAGC | bXCTxAGC | bXDTxAGC), tmpAGC);
  1080. }
  1081. void SetDataRate(PADAPTER pAdapter)
  1082. {
  1083. hal_mpt_SetDataRate(pAdapter);
  1084. }
  1085. void MP_PHY_SetRFPathSwitch(PADAPTER pAdapter , BOOLEAN bMain)
  1086. {
  1087. PHY_SetRFPathSwitch(pAdapter, bMain);
  1088. }
  1089. u8 MP_PHY_QueryRFPathSwitch(PADAPTER pAdapter)
  1090. {
  1091. return PHY_QueryRFPathSwitch(pAdapter);
  1092. }
  1093. s32 SetThermalMeter(PADAPTER pAdapter, u8 target_ther)
  1094. {
  1095. return hal_mpt_SetThermalMeter(pAdapter, target_ther);
  1096. }
  1097. static void TriggerRFThermalMeter(PADAPTER pAdapter)
  1098. {
  1099. hal_mpt_TriggerRFThermalMeter(pAdapter);
  1100. }
  1101. static u8 ReadRFThermalMeter(PADAPTER pAdapter)
  1102. {
  1103. return hal_mpt_ReadRFThermalMeter(pAdapter);
  1104. }
  1105. void GetThermalMeter(PADAPTER pAdapter, u8 *value)
  1106. {
  1107. hal_mpt_GetThermalMeter(pAdapter, value);
  1108. }
  1109. void SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
  1110. {
  1111. PhySetTxPowerLevel(pAdapter);
  1112. hal_mpt_SetSingleCarrierTx(pAdapter, bStart);
  1113. }
  1114. void SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
  1115. {
  1116. PhySetTxPowerLevel(pAdapter);
  1117. hal_mpt_SetSingleToneTx(pAdapter, bStart);
  1118. }
  1119. void SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
  1120. {
  1121. PhySetTxPowerLevel(pAdapter);
  1122. hal_mpt_SetCarrierSuppressionTx(pAdapter, bStart);
  1123. }
  1124. void SetContinuousTx(PADAPTER pAdapter, u8 bStart)
  1125. {
  1126. PhySetTxPowerLevel(pAdapter);
  1127. hal_mpt_SetContinuousTx(pAdapter, bStart);
  1128. }
  1129. void PhySetTxPowerLevel(PADAPTER pAdapter)
  1130. {
  1131. struct mp_priv *pmp_priv = &pAdapter->mppriv;
  1132. if (pmp_priv->bSetTxPower == 0) /* for NO manually set power index */
  1133. rtw_hal_set_tx_power_level(pAdapter, pmp_priv->channel);
  1134. }
  1135. /* ------------------------------------------------------------------------------ */
  1136. static void dump_mpframe(PADAPTER padapter, struct xmit_frame *pmpframe)
  1137. {
  1138. rtw_hal_mgnt_xmit(padapter, pmpframe);
  1139. }
  1140. static struct xmit_frame *alloc_mp_xmitframe(struct xmit_priv *pxmitpriv)
  1141. {
  1142. struct xmit_frame *pmpframe;
  1143. struct xmit_buf *pxmitbuf;
  1144. pmpframe = rtw_alloc_xmitframe(pxmitpriv);
  1145. if (pmpframe == NULL)
  1146. return NULL;
  1147. pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
  1148. if (pxmitbuf == NULL) {
  1149. rtw_free_xmitframe(pxmitpriv, pmpframe);
  1150. return NULL;
  1151. }
  1152. pmpframe->frame_tag = MP_FRAMETAG;
  1153. pmpframe->pxmitbuf = pxmitbuf;
  1154. pmpframe->buf_addr = pxmitbuf->pbuf;
  1155. pxmitbuf->priv_data = pmpframe;
  1156. return pmpframe;
  1157. }
  1158. static thread_return mp_xmit_packet_thread(thread_context context)
  1159. {
  1160. struct xmit_frame *pxmitframe;
  1161. struct mp_tx *pmptx;
  1162. struct mp_priv *pmp_priv;
  1163. struct xmit_priv *pxmitpriv;
  1164. PADAPTER padapter;
  1165. pmp_priv = (struct mp_priv *)context;
  1166. pmptx = &pmp_priv->tx;
  1167. padapter = pmp_priv->papdater;
  1168. pxmitpriv = &(padapter->xmitpriv);
  1169. thread_enter("RTW_MP_THREAD");
  1170. RTW_INFO("%s:pkTx Start\n", __func__);
  1171. while (1) {
  1172. pxmitframe = alloc_mp_xmitframe(pxmitpriv);
  1173. if (pxmitframe == NULL) {
  1174. if (pmptx->stop ||
  1175. RTW_CANNOT_RUN(padapter))
  1176. goto exit;
  1177. else {
  1178. rtw_usleep_os(10);
  1179. continue;
  1180. }
  1181. }
  1182. _rtw_memcpy((u8 *)(pxmitframe->buf_addr + TXDESC_OFFSET), pmptx->buf, pmptx->write_size);
  1183. _rtw_memcpy(&(pxmitframe->attrib), &(pmptx->attrib), sizeof(struct pkt_attrib));
  1184. rtw_usleep_os(padapter->mppriv.pktInterval);
  1185. dump_mpframe(padapter, pxmitframe);
  1186. pmptx->sended++;
  1187. pmp_priv->tx_pktcount++;
  1188. if (pmptx->stop ||
  1189. RTW_CANNOT_RUN(padapter))
  1190. goto exit;
  1191. if ((pmptx->count != 0) &&
  1192. (pmptx->count == pmptx->sended))
  1193. goto exit;
  1194. flush_signals_thread();
  1195. }
  1196. exit:
  1197. /* RTW_INFO("%s:pkTx Exit\n", __func__); */
  1198. rtw_mfree(pmptx->pallocated_buf, pmptx->buf_size);
  1199. pmptx->pallocated_buf = NULL;
  1200. pmptx->stop = 1;
  1201. thread_exit(NULL);
  1202. return 0;
  1203. }
  1204. void fill_txdesc_for_mp(PADAPTER padapter, u8 *ptxdesc)
  1205. {
  1206. struct mp_priv *pmp_priv = &padapter->mppriv;
  1207. _rtw_memcpy(ptxdesc, pmp_priv->tx.desc, TXDESC_SIZE);
  1208. }
  1209. #if defined(CONFIG_RTL8188E)
  1210. void fill_tx_desc_8188e(PADAPTER padapter)
  1211. {
  1212. struct mp_priv *pmp_priv = &padapter->mppriv;
  1213. struct tx_desc *desc = (struct tx_desc *)&(pmp_priv->tx.desc);
  1214. struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
  1215. u32 pkt_size = pattrib->last_txcmdsz;
  1216. s32 bmcast = IS_MCAST(pattrib->ra);
  1217. /* offset 0 */
  1218. #if !defined(CONFIG_RTL8188E_SDIO) && !defined(CONFIG_PCI_HCI)
  1219. desc->txdw0 |= cpu_to_le32(OWN | FSG | LSG);
  1220. desc->txdw0 |= cpu_to_le32(pkt_size & 0x0000FFFF); /* packet size */
  1221. desc->txdw0 |= cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ) << OFFSET_SHT) & 0x00FF0000); /* 32 bytes for TX Desc */
  1222. if (bmcast)
  1223. desc->txdw0 |= cpu_to_le32(BMC); /* broadcast packet */
  1224. desc->txdw1 |= cpu_to_le32((0x01 << 26) & 0xff000000);
  1225. #endif
  1226. desc->txdw1 |= cpu_to_le32((pattrib->mac_id) & 0x3F); /* CAM_ID(MAC_ID) */
  1227. desc->txdw1 |= cpu_to_le32((pattrib->qsel << QSEL_SHT) & 0x00001F00); /* Queue Select, TID */
  1228. desc->txdw1 |= cpu_to_le32((pattrib->raid << RATE_ID_SHT) & 0x000F0000); /* Rate Adaptive ID */
  1229. /* offset 8 */
  1230. /* desc->txdw2 |= cpu_to_le32(AGG_BK); */ /* AGG BK */
  1231. desc->txdw3 |= cpu_to_le32((pattrib->seqnum << 16) & 0x0fff0000);
  1232. desc->txdw4 |= cpu_to_le32(HW_SSN);
  1233. desc->txdw4 |= cpu_to_le32(USERATE);
  1234. desc->txdw4 |= cpu_to_le32(DISDATAFB);
  1235. if (pmp_priv->preamble) {
  1236. if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M)
  1237. desc->txdw4 |= cpu_to_le32(DATA_SHORT); /* CCK Short Preamble */
  1238. }
  1239. if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
  1240. desc->txdw4 |= cpu_to_le32(DATA_BW);
  1241. /* offset 20 */
  1242. desc->txdw5 |= cpu_to_le32(pmp_priv->rateidx & 0x0000001F);
  1243. if (pmp_priv->preamble) {
  1244. if (HwRateToMPTRate(pmp_priv->rateidx) > MPT_RATE_54M)
  1245. desc->txdw5 |= cpu_to_le32(SGI); /* MCS Short Guard Interval */
  1246. }
  1247. desc->txdw5 |= cpu_to_le32(RTY_LMT_EN); /* retry limit enable */
  1248. desc->txdw5 |= cpu_to_le32(0x00180000); /* DATA/RTS Rate Fallback Limit */
  1249. }
  1250. #endif
  1251. #if defined(CONFIG_RTL8814A)
  1252. void fill_tx_desc_8814a(PADAPTER padapter)
  1253. {
  1254. struct mp_priv *pmp_priv = &padapter->mppriv;
  1255. u8 *pDesc = (u8 *)&(pmp_priv->tx.desc);
  1256. struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
  1257. u32 pkt_size = pattrib->last_txcmdsz;
  1258. s32 bmcast = IS_MCAST(pattrib->ra);
  1259. u8 data_rate, pwr_status, offset;
  1260. /* SET_TX_DESC_FIRST_SEG_8814A(pDesc, 1); */
  1261. SET_TX_DESC_LAST_SEG_8814A(pDesc, 1);
  1262. /* SET_TX_DESC_OWN_(pDesc, 1); */
  1263. SET_TX_DESC_PKT_SIZE_8814A(pDesc, pkt_size);
  1264. offset = TXDESC_SIZE + OFFSET_SZ;
  1265. SET_TX_DESC_OFFSET_8814A(pDesc, offset);
  1266. #if defined(CONFIG_PCI_HCI)
  1267. SET_TX_DESC_PKT_OFFSET_8814A(pDesc, 0); /* 8814AE pkt_offset is 0 */
  1268. #else
  1269. SET_TX_DESC_PKT_OFFSET_8814A(pDesc, 1);
  1270. #endif
  1271. if (bmcast)
  1272. SET_TX_DESC_BMC_8814A(pDesc, 1);
  1273. SET_TX_DESC_MACID_8814A(pDesc, pattrib->mac_id);
  1274. SET_TX_DESC_RATE_ID_8814A(pDesc, pattrib->raid);
  1275. /* SET_TX_DESC_RATE_ID_8812(pDesc, RATEID_IDX_G); */
  1276. SET_TX_DESC_QUEUE_SEL_8814A(pDesc, pattrib->qsel);
  1277. /* SET_TX_DESC_QUEUE_SEL_8812(pDesc, QSLT_MGNT); */
  1278. if (pmp_priv->preamble)
  1279. SET_TX_DESC_DATA_SHORT_8814A(pDesc, 1);
  1280. if (!pattrib->qos_en) {
  1281. SET_TX_DESC_HWSEQ_EN_8814A(pDesc, 1); /* Hw set sequence number */
  1282. } else
  1283. SET_TX_DESC_SEQ_8814A(pDesc, pattrib->seqnum);
  1284. if (pmp_priv->bandwidth <= CHANNEL_WIDTH_160)
  1285. SET_TX_DESC_DATA_BW_8814A(pDesc, pmp_priv->bandwidth);
  1286. else {
  1287. RTW_INFO("%s:Err: unknown bandwidth %d, use 20M\n", __func__, pmp_priv->bandwidth);
  1288. SET_TX_DESC_DATA_BW_8814A(pDesc, CHANNEL_WIDTH_20);
  1289. }
  1290. SET_TX_DESC_DISABLE_FB_8814A(pDesc, 1);
  1291. SET_TX_DESC_USE_RATE_8814A(pDesc, 1);
  1292. SET_TX_DESC_TX_RATE_8814A(pDesc, pmp_priv->rateidx);
  1293. }
  1294. #endif
  1295. #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
  1296. void fill_tx_desc_8812a(PADAPTER padapter)
  1297. {
  1298. struct mp_priv *pmp_priv = &padapter->mppriv;
  1299. u8 *pDesc = (u8 *)&(pmp_priv->tx.desc);
  1300. struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
  1301. u32 pkt_size = pattrib->last_txcmdsz;
  1302. s32 bmcast = IS_MCAST(pattrib->ra);
  1303. u8 data_rate, pwr_status, offset;
  1304. SET_TX_DESC_FIRST_SEG_8812(pDesc, 1);
  1305. SET_TX_DESC_LAST_SEG_8812(pDesc, 1);
  1306. SET_TX_DESC_OWN_8812(pDesc, 1);
  1307. SET_TX_DESC_PKT_SIZE_8812(pDesc, pkt_size);
  1308. offset = TXDESC_SIZE + OFFSET_SZ;
  1309. SET_TX_DESC_OFFSET_8812(pDesc, offset);
  1310. #if defined(CONFIG_PCI_HCI)
  1311. SET_TX_DESC_PKT_OFFSET_8812(pDesc, 0);
  1312. #else
  1313. SET_TX_DESC_PKT_OFFSET_8812(pDesc, 1);
  1314. #endif
  1315. if (bmcast)
  1316. SET_TX_DESC_BMC_8812(pDesc, 1);
  1317. SET_TX_DESC_MACID_8812(pDesc, pattrib->mac_id);
  1318. SET_TX_DESC_RATE_ID_8812(pDesc, pattrib->raid);
  1319. /* SET_TX_DESC_RATE_ID_8812(pDesc, RATEID_IDX_G); */
  1320. SET_TX_DESC_QUEUE_SEL_8812(pDesc, pattrib->qsel);
  1321. /* SET_TX_DESC_QUEUE_SEL_8812(pDesc, QSLT_MGNT); */
  1322. if (!pattrib->qos_en) {
  1323. SET_TX_DESC_HWSEQ_EN_8812(pDesc, 1); /* Hw set sequence number */
  1324. } else
  1325. SET_TX_DESC_SEQ_8812(pDesc, pattrib->seqnum);
  1326. if (pmp_priv->bandwidth <= CHANNEL_WIDTH_160)
  1327. SET_TX_DESC_DATA_BW_8812(pDesc, pmp_priv->bandwidth);
  1328. else {
  1329. RTW_INFO("%s:Err: unknown bandwidth %d, use 20M\n", __func__, pmp_priv->bandwidth);
  1330. SET_TX_DESC_DATA_BW_8812(pDesc, CHANNEL_WIDTH_20);
  1331. }
  1332. SET_TX_DESC_DISABLE_FB_8812(pDesc, 1);
  1333. SET_TX_DESC_USE_RATE_8812(pDesc, 1);
  1334. SET_TX_DESC_TX_RATE_8812(pDesc, pmp_priv->rateidx);
  1335. }
  1336. #endif
  1337. #if defined(CONFIG_RTL8192E)
  1338. void fill_tx_desc_8192e(PADAPTER padapter)
  1339. {
  1340. struct mp_priv *pmp_priv = &padapter->mppriv;
  1341. u8 *pDesc = (u8 *)&(pmp_priv->tx.desc);
  1342. struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
  1343. u32 pkt_size = pattrib->last_txcmdsz;
  1344. s32 bmcast = IS_MCAST(pattrib->ra);
  1345. u8 data_rate, pwr_status, offset;
  1346. SET_TX_DESC_PKT_SIZE_92E(pDesc, pkt_size);
  1347. offset = TXDESC_SIZE + OFFSET_SZ;
  1348. SET_TX_DESC_OFFSET_92E(pDesc, offset);
  1349. #if defined(CONFIG_PCI_HCI) /* 8192EE */
  1350. SET_TX_DESC_PKT_OFFSET_92E(pDesc, 0); /* 8192EE pkt_offset is 0 */
  1351. #else /* 8192EU 8192ES */
  1352. SET_TX_DESC_PKT_OFFSET_92E(pDesc, 1);
  1353. #endif
  1354. if (bmcast)
  1355. SET_TX_DESC_BMC_92E(pDesc, 1);
  1356. SET_TX_DESC_MACID_92E(pDesc, pattrib->mac_id);
  1357. SET_TX_DESC_RATE_ID_92E(pDesc, pattrib->raid);
  1358. SET_TX_DESC_QUEUE_SEL_92E(pDesc, pattrib->qsel);
  1359. /* SET_TX_DESC_QUEUE_SEL_8812(pDesc, QSLT_MGNT); */
  1360. if (!pattrib->qos_en) {
  1361. SET_TX_DESC_EN_HWSEQ_92E(pDesc, 1);/* Hw set sequence number */
  1362. SET_TX_DESC_HWSEQ_SEL_92E(pDesc, pattrib->hw_ssn_sel);
  1363. } else
  1364. SET_TX_DESC_SEQ_92E(pDesc, pattrib->seqnum);
  1365. if ((pmp_priv->bandwidth == CHANNEL_WIDTH_20) || (pmp_priv->bandwidth == CHANNEL_WIDTH_40))
  1366. SET_TX_DESC_DATA_BW_92E(pDesc, pmp_priv->bandwidth);
  1367. else {
  1368. RTW_INFO("%s:Err: unknown bandwidth %d, use 20M\n", __func__, pmp_priv->bandwidth);
  1369. SET_TX_DESC_DATA_BW_92E(pDesc, CHANNEL_WIDTH_20);
  1370. }
  1371. /* SET_TX_DESC_DATA_SC_92E(pDesc, SCMapping_92E(padapter,pattrib)); */
  1372. SET_TX_DESC_DISABLE_FB_92E(pDesc, 1);
  1373. SET_TX_DESC_USE_RATE_92E(pDesc, 1);
  1374. SET_TX_DESC_TX_RATE_92E(pDesc, pmp_priv->rateidx);
  1375. }
  1376. #endif
  1377. #if defined(CONFIG_RTL8723B)
  1378. void fill_tx_desc_8723b(PADAPTER padapter)
  1379. {
  1380. struct mp_priv *pmp_priv = &padapter->mppriv;
  1381. struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
  1382. u8 *ptxdesc = pmp_priv->tx.desc;
  1383. SET_TX_DESC_AGG_BREAK_8723B(ptxdesc, 1);
  1384. SET_TX_DESC_MACID_8723B(ptxdesc, pattrib->mac_id);
  1385. SET_TX_DESC_QUEUE_SEL_8723B(ptxdesc, pattrib->qsel);
  1386. SET_TX_DESC_RATE_ID_8723B(ptxdesc, pattrib->raid);
  1387. SET_TX_DESC_SEQ_8723B(ptxdesc, pattrib->seqnum);
  1388. SET_TX_DESC_HWSEQ_EN_8723B(ptxdesc, 1);
  1389. SET_TX_DESC_USE_RATE_8723B(ptxdesc, 1);
  1390. SET_TX_DESC_DISABLE_FB_8723B(ptxdesc, 1);
  1391. if (pmp_priv->preamble) {
  1392. if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M)
  1393. SET_TX_DESC_DATA_SHORT_8723B(ptxdesc, 1);
  1394. }
  1395. if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
  1396. SET_TX_DESC_DATA_BW_8723B(ptxdesc, 1);
  1397. SET_TX_DESC_TX_RATE_8723B(ptxdesc, pmp_priv->rateidx);
  1398. SET_TX_DESC_DATA_RATE_FB_LIMIT_8723B(ptxdesc, 0x1F);
  1399. SET_TX_DESC_RTS_RATE_FB_LIMIT_8723B(ptxdesc, 0xF);
  1400. }
  1401. #endif
  1402. #if defined(CONFIG_RTL8703B)
  1403. void fill_tx_desc_8703b(PADAPTER padapter)
  1404. {
  1405. struct mp_priv *pmp_priv = &padapter->mppriv;
  1406. struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
  1407. u8 *ptxdesc = pmp_priv->tx.desc;
  1408. SET_TX_DESC_AGG_BREAK_8703B(ptxdesc, 1);
  1409. SET_TX_DESC_MACID_8703B(ptxdesc, pattrib->mac_id);
  1410. SET_TX_DESC_QUEUE_SEL_8703B(ptxdesc, pattrib->qsel);
  1411. SET_TX_DESC_RATE_ID_8703B(ptxdesc, pattrib->raid);
  1412. SET_TX_DESC_SEQ_8703B(ptxdesc, pattrib->seqnum);
  1413. SET_TX_DESC_HWSEQ_EN_8703B(ptxdesc, 1);
  1414. SET_TX_DESC_USE_RATE_8703B(ptxdesc, 1);
  1415. SET_TX_DESC_DISABLE_FB_8703B(ptxdesc, 1);
  1416. if (pmp_priv->preamble) {
  1417. if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M)
  1418. SET_TX_DESC_DATA_SHORT_8703B(ptxdesc, 1);
  1419. }
  1420. if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
  1421. SET_TX_DESC_DATA_BW_8703B(ptxdesc, 1);
  1422. SET_TX_DESC_TX_RATE_8703B(ptxdesc, pmp_priv->rateidx);
  1423. SET_TX_DESC_DATA_RATE_FB_LIMIT_8703B(ptxdesc, 0x1F);
  1424. SET_TX_DESC_RTS_RATE_FB_LIMIT_8703B(ptxdesc, 0xF);
  1425. }
  1426. #endif
  1427. #if defined(CONFIG_RTL8188F)
  1428. void fill_tx_desc_8188f(PADAPTER padapter)
  1429. {
  1430. struct mp_priv *pmp_priv = &padapter->mppriv;
  1431. struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
  1432. u8 *ptxdesc = pmp_priv->tx.desc;
  1433. SET_TX_DESC_AGG_BREAK_8188F(ptxdesc, 1);
  1434. SET_TX_DESC_MACID_8188F(ptxdesc, pattrib->mac_id);
  1435. SET_TX_DESC_QUEUE_SEL_8188F(ptxdesc, pattrib->qsel);
  1436. SET_TX_DESC_RATE_ID_8188F(ptxdesc, pattrib->raid);
  1437. SET_TX_DESC_SEQ_8188F(ptxdesc, pattrib->seqnum);
  1438. SET_TX_DESC_HWSEQ_EN_8188F(ptxdesc, 1);
  1439. SET_TX_DESC_USE_RATE_8188F(ptxdesc, 1);
  1440. SET_TX_DESC_DISABLE_FB_8188F(ptxdesc, 1);
  1441. if (pmp_priv->preamble)
  1442. if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M)
  1443. SET_TX_DESC_DATA_SHORT_8188F(ptxdesc, 1);
  1444. if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
  1445. SET_TX_DESC_DATA_BW_8188F(ptxdesc, 1);
  1446. SET_TX_DESC_TX_RATE_8188F(ptxdesc, pmp_priv->rateidx);
  1447. SET_TX_DESC_DATA_RATE_FB_LIMIT_8188F(ptxdesc, 0x1F);
  1448. SET_TX_DESC_RTS_RATE_FB_LIMIT_8188F(ptxdesc, 0xF);
  1449. }
  1450. #endif
  1451. #if defined(CONFIG_RTL8723D)
  1452. void fill_tx_desc_8723d(PADAPTER padapter)
  1453. {
  1454. struct mp_priv *pmp_priv = &padapter->mppriv;
  1455. struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
  1456. u8 *ptxdesc = pmp_priv->tx.desc;
  1457. SET_TX_DESC_BK_8723D(ptxdesc, 1);
  1458. SET_TX_DESC_MACID_8723D(ptxdesc, pattrib->mac_id);
  1459. SET_TX_DESC_QUEUE_SEL_8723D(ptxdesc, pattrib->qsel);
  1460. SET_TX_DESC_RATE_ID_8723D(ptxdesc, pattrib->raid);
  1461. SET_TX_DESC_SEQ_8723D(ptxdesc, pattrib->seqnum);
  1462. SET_TX_DESC_HWSEQ_EN_8723D(ptxdesc, 1);
  1463. SET_TX_DESC_USE_RATE_8723D(ptxdesc, 1);
  1464. SET_TX_DESC_DISABLE_FB_8723D(ptxdesc, 1);
  1465. if (pmp_priv->preamble) {
  1466. if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M)
  1467. SET_TX_DESC_DATA_SHORT_8723D(ptxdesc, 1);
  1468. }
  1469. if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
  1470. SET_TX_DESC_DATA_BW_8723D(ptxdesc, 1);
  1471. SET_TX_DESC_TX_RATE_8723D(ptxdesc, pmp_priv->rateidx);
  1472. SET_TX_DESC_DATA_RATE_FB_LIMIT_8723D(ptxdesc, 0x1F);
  1473. SET_TX_DESC_RTS_RATE_FB_LIMIT_8723D(ptxdesc, 0xF);
  1474. }
  1475. #endif
  1476. static void Rtw_MPSetMacTxEDCA(PADAPTER padapter)
  1477. {
  1478. rtw_write32(padapter, 0x508 , 0x00a422); /* Disable EDCA BE Txop for MP pkt tx adjust Packet interval */
  1479. /* RTW_INFO("%s:write 0x508~~~~~~ 0x%x\n", __func__,rtw_read32(padapter, 0x508)); */
  1480. phy_set_mac_reg(padapter, 0x458 , bMaskDWord , 0x0);
  1481. /*RTW_INFO("%s()!!!!! 0x460 = 0x%x\n" ,__func__, phy_query_bb_reg(padapter, 0x460, bMaskDWord));*/
  1482. phy_set_mac_reg(padapter, 0x460 , bMaskLWord , 0x0); /* fast EDCA queue packet interval & time out value*/
  1483. /*phy_set_mac_reg(padapter, ODM_EDCA_VO_PARAM ,bMaskLWord , 0x431C);*/
  1484. /*phy_set_mac_reg(padapter, ODM_EDCA_BE_PARAM ,bMaskLWord , 0x431C);*/
  1485. /*phy_set_mac_reg(padapter, ODM_EDCA_BK_PARAM ,bMaskLWord , 0x431C);*/
  1486. RTW_INFO("%s()!!!!! 0x460 = 0x%x\n" , __func__, phy_query_bb_reg(padapter, 0x460, bMaskDWord));
  1487. }
  1488. void SetPacketTx(PADAPTER padapter)
  1489. {
  1490. u8 *ptr, *pkt_start, *pkt_end, *fctrl;
  1491. u32 pkt_size, offset, startPlace, i;
  1492. struct rtw_ieee80211_hdr *hdr;
  1493. u8 payload;
  1494. s32 bmcast;
  1495. struct pkt_attrib *pattrib;
  1496. struct mp_priv *pmp_priv;
  1497. pmp_priv = &padapter->mppriv;
  1498. if (pmp_priv->tx.stop)
  1499. return;
  1500. pmp_priv->tx.sended = 0;
  1501. pmp_priv->tx.stop = 0;
  1502. pmp_priv->tx_pktcount = 0;
  1503. /* 3 1. update_attrib() */
  1504. pattrib = &pmp_priv->tx.attrib;
  1505. _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
  1506. _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
  1507. _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);
  1508. bmcast = IS_MCAST(pattrib->ra);
  1509. if (bmcast) {
  1510. pattrib->mac_id = 1;
  1511. pattrib->psta = rtw_get_bcmc_stainfo(padapter);
  1512. } else {
  1513. pattrib->mac_id = 0;
  1514. pattrib->psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv));
  1515. }
  1516. pattrib->mbssid = 0;
  1517. pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->pktlen;
  1518. /* 3 2. allocate xmit buffer */
  1519. pkt_size = pattrib->last_txcmdsz;
  1520. if (pmp_priv->tx.pallocated_buf)
  1521. rtw_mfree(pmp_priv->tx.pallocated_buf, pmp_priv->tx.buf_size);
  1522. pmp_priv->tx.write_size = pkt_size;
  1523. pmp_priv->tx.buf_size = pkt_size + XMITBUF_ALIGN_SZ;
  1524. pmp_priv->tx.pallocated_buf = rtw_zmalloc(pmp_priv->tx.buf_size);
  1525. if (pmp_priv->tx.pallocated_buf == NULL) {
  1526. RTW_INFO("%s: malloc(%d) fail!!\n", __func__, pmp_priv->tx.buf_size);
  1527. return;
  1528. }
  1529. pmp_priv->tx.buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pmp_priv->tx.pallocated_buf), XMITBUF_ALIGN_SZ);
  1530. ptr = pmp_priv->tx.buf;
  1531. _rtw_memset(pmp_priv->tx.desc, 0, TXDESC_SIZE);
  1532. pkt_start = ptr;
  1533. pkt_end = pkt_start + pkt_size;
  1534. /* 3 3. init TX descriptor */
  1535. #if defined(CONFIG_RTL8188E)
  1536. if (IS_HARDWARE_TYPE_8188E(padapter))
  1537. fill_tx_desc_8188e(padapter);
  1538. #endif
  1539. #if defined(CONFIG_RTL8814A)
  1540. if (IS_HARDWARE_TYPE_8814A(padapter))
  1541. fill_tx_desc_8814a(padapter);
  1542. #endif /* defined(CONFIG_RTL8814A) */
  1543. #if defined(CONFIG_RTL8822B)
  1544. if (IS_HARDWARE_TYPE_8822B(padapter))
  1545. rtl8822b_prepare_mp_txdesc(padapter, pmp_priv);
  1546. #endif /* CONFIG_RTL8822B */
  1547. #if defined(CONFIG_RTL8821C)
  1548. if (IS_HARDWARE_TYPE_8821C(padapter))
  1549. rtl8821c_prepare_mp_txdesc(padapter, pmp_priv);
  1550. #endif /* CONFIG_RTL8821C */
  1551. #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
  1552. if (IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter))
  1553. fill_tx_desc_8812a(padapter);
  1554. #endif
  1555. #if defined(CONFIG_RTL8192E)
  1556. if (IS_HARDWARE_TYPE_8192E(padapter))
  1557. fill_tx_desc_8192e(padapter);
  1558. #endif
  1559. #if defined(CONFIG_RTL8723B)
  1560. if (IS_HARDWARE_TYPE_8723B(padapter))
  1561. fill_tx_desc_8723b(padapter);
  1562. #endif
  1563. #if defined(CONFIG_RTL8703B)
  1564. if (IS_HARDWARE_TYPE_8703B(padapter))
  1565. fill_tx_desc_8703b(padapter);
  1566. #endif
  1567. #if defined(CONFIG_RTL8188F)
  1568. if (IS_HARDWARE_TYPE_8188F(padapter))
  1569. fill_tx_desc_8188f(padapter);
  1570. #endif
  1571. #if defined(CONFIG_RTL8723D)
  1572. if (IS_HARDWARE_TYPE_8723D(padapter))
  1573. fill_tx_desc_8723d(padapter);
  1574. #endif
  1575. /* 3 4. make wlan header, make_wlanhdr() */
  1576. hdr = (struct rtw_ieee80211_hdr *)pkt_start;
  1577. set_frame_sub_type(&hdr->frame_ctl, pattrib->subtype);
  1578. _rtw_memcpy(hdr->addr1, pattrib->dst, ETH_ALEN); /* DA */
  1579. _rtw_memcpy(hdr->addr2, pattrib->src, ETH_ALEN); /* SA */
  1580. _rtw_memcpy(hdr->addr3, get_bssid(&padapter->mlmepriv), ETH_ALEN); /* RA, BSSID */
  1581. /* 3 5. make payload */
  1582. ptr = pkt_start + pattrib->hdrlen;
  1583. switch (pmp_priv->tx.payload) {
  1584. case 0:
  1585. payload = 0x00;
  1586. break;
  1587. case 1:
  1588. payload = 0x5a;
  1589. break;
  1590. case 2:
  1591. payload = 0xa5;
  1592. break;
  1593. case 3:
  1594. payload = 0xff;
  1595. break;
  1596. default:
  1597. payload = 0x00;
  1598. break;
  1599. }
  1600. pmp_priv->TXradomBuffer = rtw_zmalloc(4096);
  1601. if (pmp_priv->TXradomBuffer == NULL) {
  1602. RTW_INFO("mp create random buffer fail!\n");
  1603. goto exit;
  1604. }
  1605. for (i = 0; i < 4096; i++)
  1606. pmp_priv->TXradomBuffer[i] = rtw_random32() % 0xFF;
  1607. /* startPlace = (u32)(rtw_random32() % 3450); */
  1608. _rtw_memcpy(ptr, pmp_priv->TXradomBuffer, pkt_end - ptr);
  1609. /* _rtw_memset(ptr, payload, pkt_end - ptr); */
  1610. rtw_mfree(pmp_priv->TXradomBuffer, 4096);
  1611. /* 3 6. start thread */
  1612. #ifdef PLATFORM_LINUX
  1613. pmp_priv->tx.PktTxThread = kthread_run(mp_xmit_packet_thread, pmp_priv, "RTW_MP_THREAD");
  1614. if (IS_ERR(pmp_priv->tx.PktTxThread))
  1615. RTW_INFO("Create PktTx Thread Fail !!!!!\n");
  1616. #endif
  1617. #ifdef PLATFORM_FREEBSD
  1618. {
  1619. struct proc *p;
  1620. struct thread *td;
  1621. pmp_priv->tx.PktTxThread = kproc_kthread_add(mp_xmit_packet_thread, pmp_priv,
  1622. &p, &td, RFHIGHPID, 0, "MPXmitThread", "MPXmitThread");
  1623. if (pmp_priv->tx.PktTxThread < 0)
  1624. RTW_INFO("Create PktTx Thread Fail !!!!!\n");
  1625. }
  1626. #endif
  1627. Rtw_MPSetMacTxEDCA(padapter);
  1628. exit:
  1629. return;
  1630. }
  1631. void SetPacketRx(PADAPTER pAdapter, u8 bStartRx, u8 bAB)
  1632. {
  1633. PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
  1634. struct mp_priv *pmppriv = &pAdapter->mppriv;
  1635. if (bStartRx) {
  1636. #ifdef CONFIG_RTL8723B
  1637. phy_set_mac_reg(pAdapter, 0xe70, BIT23 | BIT22, 0x3); /* Power on adc (in RX_WAIT_CCA state) */
  1638. write_bbreg(pAdapter, 0xa01, BIT0, bDisable);/* improve Rx performance by jerry */
  1639. #endif
  1640. pHalData->ReceiveConfig = RCR_AAP | RCR_APM | RCR_AM | RCR_AMF | RCR_HTC_LOC_CTRL;
  1641. pHalData->ReceiveConfig |= RCR_ACRC32;
  1642. pHalData->ReceiveConfig |= RCR_APP_PHYST_RXFF | RCR_APP_ICV | RCR_APP_MIC;
  1643. if (pmppriv->bSetRxBssid == _TRUE) {
  1644. RTW_INFO("%s: pmppriv->network_macaddr=" MAC_FMT "\n", __func__,
  1645. MAC_ARG(pmppriv->network_macaddr));
  1646. pHalData->ReceiveConfig = 0;
  1647. pHalData->ReceiveConfig |= RCR_CBSSID_DATA | RCR_CBSSID_BCN |RCR_APM | RCR_AM | RCR_AB |RCR_AMF;
  1648. #if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
  1649. write_bbreg(pAdapter, 0x550, BIT3, bEnable);
  1650. #endif
  1651. rtw_write16(pAdapter, REG_RXFLTMAP0, 0xFFEF); /* REG_RXFLTMAP0 (RX Filter Map Group 0) */
  1652. } else {
  1653. pHalData->ReceiveConfig |= RCR_ADF;
  1654. /* Accept all data frames */
  1655. rtw_write16(pAdapter, REG_RXFLTMAP2, 0xFFFF);
  1656. }
  1657. if (bAB)
  1658. pHalData->ReceiveConfig |= RCR_AB;
  1659. } else {
  1660. #ifdef CONFIG_RTL8723B
  1661. phy_set_mac_reg(pAdapter, 0xe70, BIT23 | BIT22, 0x00); /* Power off adc (in RX_WAIT_CCA state)*/
  1662. write_bbreg(pAdapter, 0xa01, BIT0, bEnable);/* improve Rx performance by jerry */
  1663. #endif
  1664. pHalData->ReceiveConfig = 0;
  1665. rtw_write16(pAdapter, REG_RXFLTMAP0, 0xFFFF); /* REG_RXFLTMAP0 (RX Filter Map Group 0) */
  1666. }
  1667. rtw_write32(pAdapter, REG_RCR, pHalData->ReceiveConfig);
  1668. }
  1669. void ResetPhyRxPktCount(PADAPTER pAdapter)
  1670. {
  1671. u32 i, phyrx_set = 0;
  1672. for (i = 0; i <= 0xF; i++) {
  1673. phyrx_set = 0;
  1674. phyrx_set |= _RXERR_RPT_SEL(i); /* select */
  1675. phyrx_set |= RXERR_RPT_RST; /* set counter to zero */
  1676. rtw_write32(pAdapter, REG_RXERR_RPT, phyrx_set);
  1677. }
  1678. }
  1679. static u32 GetPhyRxPktCounts(PADAPTER pAdapter, u32 selbit)
  1680. {
  1681. /* selection */
  1682. u32 phyrx_set = 0, count = 0;
  1683. phyrx_set = _RXERR_RPT_SEL(selbit & 0xF);
  1684. rtw_write32(pAdapter, REG_RXERR_RPT, phyrx_set);
  1685. /* Read packet count */
  1686. count = rtw_read32(pAdapter, REG_RXERR_RPT) & RXERR_COUNTER_MASK;
  1687. return count;
  1688. }
  1689. u32 GetPhyRxPktReceived(PADAPTER pAdapter)
  1690. {
  1691. u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0;
  1692. OFDM_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_OFDM_MPDU_OK);
  1693. CCK_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_CCK_MPDU_OK);
  1694. HT_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_HT_MPDU_OK);
  1695. return OFDM_cnt + CCK_cnt + HT_cnt;
  1696. }
  1697. u32 GetPhyRxPktCRC32Error(PADAPTER pAdapter)
  1698. {
  1699. u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0;
  1700. OFDM_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_OFDM_MPDU_FAIL);
  1701. CCK_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_CCK_MPDU_FAIL);
  1702. HT_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_HT_MPDU_FAIL);
  1703. return OFDM_cnt + CCK_cnt + HT_cnt;
  1704. }
  1705. /* reg 0x808[9:0]: FFT data x
  1706. * reg 0x808[22]: 0 --> 1 to get 1 FFT data y
  1707. * reg 0x8B4[15:0]: FFT data y report */
  1708. static u32 rtw_GetPSDData(PADAPTER pAdapter, u32 point)
  1709. {
  1710. u32 psd_val = 0;
  1711. #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
  1712. u16 psd_reg = 0x910;
  1713. u16 psd_regL = 0xF44;
  1714. #else
  1715. u16 psd_reg = 0x808;
  1716. u16 psd_regL = 0x8B4;
  1717. #endif
  1718. psd_val = rtw_read32(pAdapter, psd_reg);
  1719. psd_val &= 0xFFBFFC00;
  1720. psd_val |= point;
  1721. rtw_write32(pAdapter, psd_reg, psd_val);
  1722. rtw_mdelay_os(1);
  1723. psd_val |= 0x00400000;
  1724. rtw_write32(pAdapter, psd_reg, psd_val);
  1725. rtw_mdelay_os(1);
  1726. psd_val = rtw_read32(pAdapter, psd_regL);
  1727. psd_val &= 0x0000FFFF;
  1728. return psd_val;
  1729. }
  1730. /*
  1731. * pts start_point_min stop_point_max
  1732. * 128 64 64 + 128 = 192
  1733. * 256 128 128 + 256 = 384
  1734. * 512 256 256 + 512 = 768
  1735. * 1024 512 512 + 1024 = 1536
  1736. *
  1737. */
  1738. u32 mp_query_psd(PADAPTER pAdapter, u8 *data)
  1739. {
  1740. u32 i, psd_pts = 0, psd_start = 0, psd_stop = 0;
  1741. u32 psd_data = 0;
  1742. #ifdef PLATFORM_LINUX
  1743. if (!netif_running(pAdapter->pnetdev)) {
  1744. return 0;
  1745. }
  1746. #endif
  1747. if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
  1748. return 0;
  1749. }
  1750. if (strlen(data) == 0) { /* default value */
  1751. psd_pts = 128;
  1752. psd_start = 64;
  1753. psd_stop = 128;
  1754. } else
  1755. sscanf(data, "pts=%d,start=%d,stop=%d", &psd_pts, &psd_start, &psd_stop);
  1756. data[0] = '\0';
  1757. i = psd_start;
  1758. while (i < psd_stop) {
  1759. if (i >= psd_pts)
  1760. psd_data = rtw_GetPSDData(pAdapter, i - psd_pts);
  1761. else
  1762. psd_data = rtw_GetPSDData(pAdapter, i);
  1763. sprintf(data, "%s%x ", data, psd_data);
  1764. i++;
  1765. }
  1766. #ifdef CONFIG_LONG_DELAY_ISSUE
  1767. rtw_msleep_os(100);
  1768. #else
  1769. rtw_mdelay_os(100);
  1770. #endif
  1771. return strlen(data) + 1;
  1772. }
  1773. #if 0
  1774. void _rtw_mp_xmit_priv(struct xmit_priv *pxmitpriv)
  1775. {
  1776. int i, res;
  1777. _adapter *padapter = pxmitpriv->adapter;
  1778. struct xmit_frame *pxmitframe = (struct xmit_frame *) pxmitpriv->pxmit_frame_buf;
  1779. struct xmit_buf *pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmitbuf;
  1780. u32 max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ;
  1781. u32 num_xmit_extbuf = NR_XMIT_EXTBUFF;
  1782. if (padapter->registrypriv.mp_mode == 0) {
  1783. max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ;
  1784. num_xmit_extbuf = NR_XMIT_EXTBUFF;
  1785. } else {
  1786. max_xmit_extbuf_size = 6000;
  1787. num_xmit_extbuf = 8;
  1788. }
  1789. pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf;
  1790. for (i = 0; i < num_xmit_extbuf; i++) {
  1791. rtw_os_xmit_resource_free(padapter, pxmitbuf, (max_xmit_extbuf_size + XMITBUF_ALIGN_SZ), _FALSE);
  1792. pxmitbuf++;
  1793. }
  1794. if (pxmitpriv->pallocated_xmit_extbuf)
  1795. rtw_vmfree(pxmitpriv->pallocated_xmit_extbuf, num_xmit_extbuf * sizeof(struct xmit_buf) + 4);
  1796. if (padapter->registrypriv.mp_mode == 0) {
  1797. max_xmit_extbuf_size = 6000;
  1798. num_xmit_extbuf = 8;
  1799. } else {
  1800. max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ;
  1801. num_xmit_extbuf = NR_XMIT_EXTBUFF;
  1802. }
  1803. /* Init xmit extension buff */
  1804. _rtw_init_queue(&pxmitpriv->free_xmit_extbuf_queue);
  1805. pxmitpriv->pallocated_xmit_extbuf = rtw_zvmalloc(num_xmit_extbuf * sizeof(struct xmit_buf) + 4);
  1806. if (pxmitpriv->pallocated_xmit_extbuf == NULL) {
  1807. res = _FAIL;
  1808. goto exit;
  1809. }
  1810. pxmitpriv->pxmit_extbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_xmit_extbuf), 4);
  1811. pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf;
  1812. for (i = 0; i < num_xmit_extbuf; i++) {
  1813. _rtw_init_listhead(&pxmitbuf->list);
  1814. pxmitbuf->priv_data = NULL;
  1815. pxmitbuf->padapter = padapter;
  1816. pxmitbuf->buf_tag = XMITBUF_MGNT;
  1817. res = rtw_os_xmit_resource_alloc(padapter, pxmitbuf, max_xmit_extbuf_size + XMITBUF_ALIGN_SZ, _TRUE);
  1818. if (res == _FAIL) {
  1819. res = _FAIL;
  1820. goto exit;
  1821. }
  1822. #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
  1823. pxmitbuf->phead = pxmitbuf->pbuf;
  1824. pxmitbuf->pend = pxmitbuf->pbuf + max_xmit_extbuf_size;
  1825. pxmitbuf->len = 0;
  1826. pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;
  1827. #endif
  1828. rtw_list_insert_tail(&pxmitbuf->list, &(pxmitpriv->free_xmit_extbuf_queue.queue));
  1829. #ifdef DBG_XMIT_BUF_EXT
  1830. pxmitbuf->no = i;
  1831. #endif
  1832. pxmitbuf++;
  1833. }
  1834. pxmitpriv->free_xmit_extbuf_cnt = num_xmit_extbuf;
  1835. exit:
  1836. ;
  1837. }
  1838. #endif
  1839. u8
  1840. mpt_to_mgnt_rate(
  1841. IN ULONG MptRateIdx
  1842. )
  1843. {
  1844. /* Mapped to MGN_XXX defined in MgntGen.h */
  1845. switch (MptRateIdx) {
  1846. /* CCK rate. */
  1847. case MPT_RATE_1M:
  1848. return MGN_1M;
  1849. case MPT_RATE_2M:
  1850. return MGN_2M;
  1851. case MPT_RATE_55M:
  1852. return MGN_5_5M;
  1853. case MPT_RATE_11M:
  1854. return MGN_11M;
  1855. /* OFDM rate. */
  1856. case MPT_RATE_6M:
  1857. return MGN_6M;
  1858. case MPT_RATE_9M:
  1859. return MGN_9M;
  1860. case MPT_RATE_12M:
  1861. return MGN_12M;
  1862. case MPT_RATE_18M:
  1863. return MGN_18M;
  1864. case MPT_RATE_24M:
  1865. return MGN_24M;
  1866. case MPT_RATE_36M:
  1867. return MGN_36M;
  1868. case MPT_RATE_48M:
  1869. return MGN_48M;
  1870. case MPT_RATE_54M:
  1871. return MGN_54M;
  1872. /* HT rate. */
  1873. case MPT_RATE_MCS0:
  1874. return MGN_MCS0;
  1875. case MPT_RATE_MCS1:
  1876. return MGN_MCS1;
  1877. case MPT_RATE_MCS2:
  1878. return MGN_MCS2;
  1879. case MPT_RATE_MCS3:
  1880. return MGN_MCS3;
  1881. case MPT_RATE_MCS4:
  1882. return MGN_MCS4;
  1883. case MPT_RATE_MCS5:
  1884. return MGN_MCS5;
  1885. case MPT_RATE_MCS6:
  1886. return MGN_MCS6;
  1887. case MPT_RATE_MCS7:
  1888. return MGN_MCS7;
  1889. case MPT_RATE_MCS8:
  1890. return MGN_MCS8;
  1891. case MPT_RATE_MCS9:
  1892. return MGN_MCS9;
  1893. case MPT_RATE_MCS10:
  1894. return MGN_MCS10;
  1895. case MPT_RATE_MCS11:
  1896. return MGN_MCS11;
  1897. case MPT_RATE_MCS12:
  1898. return MGN_MCS12;
  1899. case MPT_RATE_MCS13:
  1900. return MGN_MCS13;
  1901. case MPT_RATE_MCS14:
  1902. return MGN_MCS14;
  1903. case MPT_RATE_MCS15:
  1904. return MGN_MCS15;
  1905. case MPT_RATE_MCS16:
  1906. return MGN_MCS16;
  1907. case MPT_RATE_MCS17:
  1908. return MGN_MCS17;
  1909. case MPT_RATE_MCS18:
  1910. return MGN_MCS18;
  1911. case MPT_RATE_MCS19:
  1912. return MGN_MCS19;
  1913. case MPT_RATE_MCS20:
  1914. return MGN_MCS20;
  1915. case MPT_RATE_MCS21:
  1916. return MGN_MCS21;
  1917. case MPT_RATE_MCS22:
  1918. return MGN_MCS22;
  1919. case MPT_RATE_MCS23:
  1920. return MGN_MCS23;
  1921. case MPT_RATE_MCS24:
  1922. return MGN_MCS24;
  1923. case MPT_RATE_MCS25:
  1924. return MGN_MCS25;
  1925. case MPT_RATE_MCS26:
  1926. return MGN_MCS26;
  1927. case MPT_RATE_MCS27:
  1928. return MGN_MCS27;
  1929. case MPT_RATE_MCS28:
  1930. return MGN_MCS28;
  1931. case MPT_RATE_MCS29:
  1932. return MGN_MCS29;
  1933. case MPT_RATE_MCS30:
  1934. return MGN_MCS30;
  1935. case MPT_RATE_MCS31:
  1936. return MGN_MCS31;
  1937. /* VHT rate. */
  1938. case MPT_RATE_VHT1SS_MCS0:
  1939. return MGN_VHT1SS_MCS0;
  1940. case MPT_RATE_VHT1SS_MCS1:
  1941. return MGN_VHT1SS_MCS1;
  1942. case MPT_RATE_VHT1SS_MCS2:
  1943. return MGN_VHT1SS_MCS2;
  1944. case MPT_RATE_VHT1SS_MCS3:
  1945. return MGN_VHT1SS_MCS3;
  1946. case MPT_RATE_VHT1SS_MCS4:
  1947. return MGN_VHT1SS_MCS4;
  1948. case MPT_RATE_VHT1SS_MCS5:
  1949. return MGN_VHT1SS_MCS5;
  1950. case MPT_RATE_VHT1SS_MCS6:
  1951. return MGN_VHT1SS_MCS6;
  1952. case MPT_RATE_VHT1SS_MCS7:
  1953. return MGN_VHT1SS_MCS7;
  1954. case MPT_RATE_VHT1SS_MCS8:
  1955. return MGN_VHT1SS_MCS8;
  1956. case MPT_RATE_VHT1SS_MCS9:
  1957. return MGN_VHT1SS_MCS9;
  1958. case MPT_RATE_VHT2SS_MCS0:
  1959. return MGN_VHT2SS_MCS0;
  1960. case MPT_RATE_VHT2SS_MCS1:
  1961. return MGN_VHT2SS_MCS1;
  1962. case MPT_RATE_VHT2SS_MCS2:
  1963. return MGN_VHT2SS_MCS2;
  1964. case MPT_RATE_VHT2SS_MCS3:
  1965. return MGN_VHT2SS_MCS3;
  1966. case MPT_RATE_VHT2SS_MCS4:
  1967. return MGN_VHT2SS_MCS4;
  1968. case MPT_RATE_VHT2SS_MCS5:
  1969. return MGN_VHT2SS_MCS5;
  1970. case MPT_RATE_VHT2SS_MCS6:
  1971. return MGN_VHT2SS_MCS6;
  1972. case MPT_RATE_VHT2SS_MCS7:
  1973. return MGN_VHT2SS_MCS7;
  1974. case MPT_RATE_VHT2SS_MCS8:
  1975. return MGN_VHT2SS_MCS8;
  1976. case MPT_RATE_VHT2SS_MCS9:
  1977. return MGN_VHT2SS_MCS9;
  1978. case MPT_RATE_VHT3SS_MCS0:
  1979. return MGN_VHT3SS_MCS0;
  1980. case MPT_RATE_VHT3SS_MCS1:
  1981. return MGN_VHT3SS_MCS1;
  1982. case MPT_RATE_VHT3SS_MCS2:
  1983. return MGN_VHT3SS_MCS2;
  1984. case MPT_RATE_VHT3SS_MCS3:
  1985. return MGN_VHT3SS_MCS3;
  1986. case MPT_RATE_VHT3SS_MCS4:
  1987. return MGN_VHT3SS_MCS4;
  1988. case MPT_RATE_VHT3SS_MCS5:
  1989. return MGN_VHT3SS_MCS5;
  1990. case MPT_RATE_VHT3SS_MCS6:
  1991. return MGN_VHT3SS_MCS6;
  1992. case MPT_RATE_VHT3SS_MCS7:
  1993. return MGN_VHT3SS_MCS7;
  1994. case MPT_RATE_VHT3SS_MCS8:
  1995. return MGN_VHT3SS_MCS8;
  1996. case MPT_RATE_VHT3SS_MCS9:
  1997. return MGN_VHT3SS_MCS9;
  1998. case MPT_RATE_VHT4SS_MCS0:
  1999. return MGN_VHT4SS_MCS0;
  2000. case MPT_RATE_VHT4SS_MCS1:
  2001. return MGN_VHT4SS_MCS1;
  2002. case MPT_RATE_VHT4SS_MCS2:
  2003. return MGN_VHT4SS_MCS2;
  2004. case MPT_RATE_VHT4SS_MCS3:
  2005. return MGN_VHT4SS_MCS3;
  2006. case MPT_RATE_VHT4SS_MCS4:
  2007. return MGN_VHT4SS_MCS4;
  2008. case MPT_RATE_VHT4SS_MCS5:
  2009. return MGN_VHT4SS_MCS5;
  2010. case MPT_RATE_VHT4SS_MCS6:
  2011. return MGN_VHT4SS_MCS6;
  2012. case MPT_RATE_VHT4SS_MCS7:
  2013. return MGN_VHT4SS_MCS7;
  2014. case MPT_RATE_VHT4SS_MCS8:
  2015. return MGN_VHT4SS_MCS8;
  2016. case MPT_RATE_VHT4SS_MCS9:
  2017. return MGN_VHT4SS_MCS9;
  2018. case MPT_RATE_LAST: /* fully automatiMGN_VHT2SS_MCS1; */
  2019. default:
  2020. RTW_INFO("<===mpt_to_mgnt_rate(), Invalid Rate: %d!!\n", MptRateIdx);
  2021. return 0x0;
  2022. }
  2023. }
  2024. u8 HwRateToMPTRate(u8 rate)
  2025. {
  2026. u8 ret_rate = MGN_1M;
  2027. switch (rate) {
  2028. case DESC_RATE1M:
  2029. ret_rate = MPT_RATE_1M;
  2030. break;
  2031. case DESC_RATE2M:
  2032. ret_rate = MPT_RATE_2M;
  2033. break;
  2034. case DESC_RATE5_5M:
  2035. ret_rate = MPT_RATE_55M;
  2036. break;
  2037. case DESC_RATE11M:
  2038. ret_rate = MPT_RATE_11M;
  2039. break;
  2040. case DESC_RATE6M:
  2041. ret_rate = MPT_RATE_6M;
  2042. break;
  2043. case DESC_RATE9M:
  2044. ret_rate = MPT_RATE_9M;
  2045. break;
  2046. case DESC_RATE12M:
  2047. ret_rate = MPT_RATE_12M;
  2048. break;
  2049. case DESC_RATE18M:
  2050. ret_rate = MPT_RATE_18M;
  2051. break;
  2052. case DESC_RATE24M:
  2053. ret_rate = MPT_RATE_24M;
  2054. break;
  2055. case DESC_RATE36M:
  2056. ret_rate = MPT_RATE_36M;
  2057. break;
  2058. case DESC_RATE48M:
  2059. ret_rate = MPT_RATE_48M;
  2060. break;
  2061. case DESC_RATE54M:
  2062. ret_rate = MPT_RATE_54M;
  2063. break;
  2064. case DESC_RATEMCS0:
  2065. ret_rate = MPT_RATE_MCS0;
  2066. break;
  2067. case DESC_RATEMCS1:
  2068. ret_rate = MPT_RATE_MCS1;
  2069. break;
  2070. case DESC_RATEMCS2:
  2071. ret_rate = MPT_RATE_MCS2;
  2072. break;
  2073. case DESC_RATEMCS3:
  2074. ret_rate = MPT_RATE_MCS3;
  2075. break;
  2076. case DESC_RATEMCS4:
  2077. ret_rate = MPT_RATE_MCS4;
  2078. break;
  2079. case DESC_RATEMCS5:
  2080. ret_rate = MPT_RATE_MCS5;
  2081. break;
  2082. case DESC_RATEMCS6:
  2083. ret_rate = MPT_RATE_MCS6;
  2084. break;
  2085. case DESC_RATEMCS7:
  2086. ret_rate = MPT_RATE_MCS7;
  2087. break;
  2088. case DESC_RATEMCS8:
  2089. ret_rate = MPT_RATE_MCS8;
  2090. break;
  2091. case DESC_RATEMCS9:
  2092. ret_rate = MPT_RATE_MCS9;
  2093. break;
  2094. case DESC_RATEMCS10:
  2095. ret_rate = MPT_RATE_MCS10;
  2096. break;
  2097. case DESC_RATEMCS11:
  2098. ret_rate = MPT_RATE_MCS11;
  2099. break;
  2100. case DESC_RATEMCS12:
  2101. ret_rate = MPT_RATE_MCS12;
  2102. break;
  2103. case DESC_RATEMCS13:
  2104. ret_rate = MPT_RATE_MCS13;
  2105. break;
  2106. case DESC_RATEMCS14:
  2107. ret_rate = MPT_RATE_MCS14;
  2108. break;
  2109. case DESC_RATEMCS15:
  2110. ret_rate = MPT_RATE_MCS15;
  2111. break;
  2112. case DESC_RATEMCS16:
  2113. ret_rate = MPT_RATE_MCS16;
  2114. break;
  2115. case DESC_RATEMCS17:
  2116. ret_rate = MPT_RATE_MCS17;
  2117. break;
  2118. case DESC_RATEMCS18:
  2119. ret_rate = MPT_RATE_MCS18;
  2120. break;
  2121. case DESC_RATEMCS19:
  2122. ret_rate = MPT_RATE_MCS19;
  2123. break;
  2124. case DESC_RATEMCS20:
  2125. ret_rate = MPT_RATE_MCS20;
  2126. break;
  2127. case DESC_RATEMCS21:
  2128. ret_rate = MPT_RATE_MCS21;
  2129. break;
  2130. case DESC_RATEMCS22:
  2131. ret_rate = MPT_RATE_MCS22;
  2132. break;
  2133. case DESC_RATEMCS23:
  2134. ret_rate = MPT_RATE_MCS23;
  2135. break;
  2136. case DESC_RATEMCS24:
  2137. ret_rate = MPT_RATE_MCS24;
  2138. break;
  2139. case DESC_RATEMCS25:
  2140. ret_rate = MPT_RATE_MCS25;
  2141. break;
  2142. case DESC_RATEMCS26:
  2143. ret_rate = MPT_RATE_MCS26;
  2144. break;
  2145. case DESC_RATEMCS27:
  2146. ret_rate = MPT_RATE_MCS27;
  2147. break;
  2148. case DESC_RATEMCS28:
  2149. ret_rate = MPT_RATE_MCS28;
  2150. break;
  2151. case DESC_RATEMCS29:
  2152. ret_rate = MPT_RATE_MCS29;
  2153. break;
  2154. case DESC_RATEMCS30:
  2155. ret_rate = MPT_RATE_MCS30;
  2156. break;
  2157. case DESC_RATEMCS31:
  2158. ret_rate = MPT_RATE_MCS31;
  2159. break;
  2160. case DESC_RATEVHTSS1MCS0:
  2161. ret_rate = MPT_RATE_VHT1SS_MCS0;
  2162. break;
  2163. case DESC_RATEVHTSS1MCS1:
  2164. ret_rate = MPT_RATE_VHT1SS_MCS1;
  2165. break;
  2166. case DESC_RATEVHTSS1MCS2:
  2167. ret_rate = MPT_RATE_VHT1SS_MCS2;
  2168. break;
  2169. case DESC_RATEVHTSS1MCS3:
  2170. ret_rate = MPT_RATE_VHT1SS_MCS3;
  2171. break;
  2172. case DESC_RATEVHTSS1MCS4:
  2173. ret_rate = MPT_RATE_VHT1SS_MCS4;
  2174. break;
  2175. case DESC_RATEVHTSS1MCS5:
  2176. ret_rate = MPT_RATE_VHT1SS_MCS5;
  2177. break;
  2178. case DESC_RATEVHTSS1MCS6:
  2179. ret_rate = MPT_RATE_VHT1SS_MCS6;
  2180. break;
  2181. case DESC_RATEVHTSS1MCS7:
  2182. ret_rate = MPT_RATE_VHT1SS_MCS7;
  2183. break;
  2184. case DESC_RATEVHTSS1MCS8:
  2185. ret_rate = MPT_RATE_VHT1SS_MCS8;
  2186. break;
  2187. case DESC_RATEVHTSS1MCS9:
  2188. ret_rate = MPT_RATE_VHT1SS_MCS9;
  2189. break;
  2190. case DESC_RATEVHTSS2MCS0:
  2191. ret_rate = MPT_RATE_VHT2SS_MCS0;
  2192. break;
  2193. case DESC_RATEVHTSS2MCS1:
  2194. ret_rate = MPT_RATE_VHT2SS_MCS1;
  2195. break;
  2196. case DESC_RATEVHTSS2MCS2:
  2197. ret_rate = MPT_RATE_VHT2SS_MCS2;
  2198. break;
  2199. case DESC_RATEVHTSS2MCS3:
  2200. ret_rate = MPT_RATE_VHT2SS_MCS3;
  2201. break;
  2202. case DESC_RATEVHTSS2MCS4:
  2203. ret_rate = MPT_RATE_VHT2SS_MCS4;
  2204. break;
  2205. case DESC_RATEVHTSS2MCS5:
  2206. ret_rate = MPT_RATE_VHT2SS_MCS5;
  2207. break;
  2208. case DESC_RATEVHTSS2MCS6:
  2209. ret_rate = MPT_RATE_VHT2SS_MCS6;
  2210. break;
  2211. case DESC_RATEVHTSS2MCS7:
  2212. ret_rate = MPT_RATE_VHT2SS_MCS7;
  2213. break;
  2214. case DESC_RATEVHTSS2MCS8:
  2215. ret_rate = MPT_RATE_VHT2SS_MCS8;
  2216. break;
  2217. case DESC_RATEVHTSS2MCS9:
  2218. ret_rate = MPT_RATE_VHT2SS_MCS9;
  2219. break;
  2220. case DESC_RATEVHTSS3MCS0:
  2221. ret_rate = MPT_RATE_VHT3SS_MCS0;
  2222. break;
  2223. case DESC_RATEVHTSS3MCS1:
  2224. ret_rate = MPT_RATE_VHT3SS_MCS1;
  2225. break;
  2226. case DESC_RATEVHTSS3MCS2:
  2227. ret_rate = MPT_RATE_VHT3SS_MCS2;
  2228. break;
  2229. case DESC_RATEVHTSS3MCS3:
  2230. ret_rate = MPT_RATE_VHT3SS_MCS3;
  2231. break;
  2232. case DESC_RATEVHTSS3MCS4:
  2233. ret_rate = MPT_RATE_VHT3SS_MCS4;
  2234. break;
  2235. case DESC_RATEVHTSS3MCS5:
  2236. ret_rate = MPT_RATE_VHT3SS_MCS5;
  2237. break;
  2238. case DESC_RATEVHTSS3MCS6:
  2239. ret_rate = MPT_RATE_VHT3SS_MCS6;
  2240. break;
  2241. case DESC_RATEVHTSS3MCS7:
  2242. ret_rate = MPT_RATE_VHT3SS_MCS7;
  2243. break;
  2244. case DESC_RATEVHTSS3MCS8:
  2245. ret_rate = MPT_RATE_VHT3SS_MCS8;
  2246. break;
  2247. case DESC_RATEVHTSS3MCS9:
  2248. ret_rate = MPT_RATE_VHT3SS_MCS9;
  2249. break;
  2250. case DESC_RATEVHTSS4MCS0:
  2251. ret_rate = MPT_RATE_VHT4SS_MCS0;
  2252. break;
  2253. case DESC_RATEVHTSS4MCS1:
  2254. ret_rate = MPT_RATE_VHT4SS_MCS1;
  2255. break;
  2256. case DESC_RATEVHTSS4MCS2:
  2257. ret_rate = MPT_RATE_VHT4SS_MCS2;
  2258. break;
  2259. case DESC_RATEVHTSS4MCS3:
  2260. ret_rate = MPT_RATE_VHT4SS_MCS3;
  2261. break;
  2262. case DESC_RATEVHTSS4MCS4:
  2263. ret_rate = MPT_RATE_VHT4SS_MCS4;
  2264. break;
  2265. case DESC_RATEVHTSS4MCS5:
  2266. ret_rate = MPT_RATE_VHT4SS_MCS5;
  2267. break;
  2268. case DESC_RATEVHTSS4MCS6:
  2269. ret_rate = MPT_RATE_VHT4SS_MCS6;
  2270. break;
  2271. case DESC_RATEVHTSS4MCS7:
  2272. ret_rate = MPT_RATE_VHT4SS_MCS7;
  2273. break;
  2274. case DESC_RATEVHTSS4MCS8:
  2275. ret_rate = MPT_RATE_VHT4SS_MCS8;
  2276. break;
  2277. case DESC_RATEVHTSS4MCS9:
  2278. ret_rate = MPT_RATE_VHT4SS_MCS9;
  2279. break;
  2280. default:
  2281. RTW_INFO("hw_rate_to_m_rate(): Non supported Rate [%x]!!!\n", rate);
  2282. break;
  2283. }
  2284. return ret_rate;
  2285. }
  2286. u8 rtw_mpRateParseFunc(PADAPTER pAdapter, u8 *targetStr)
  2287. {
  2288. u16 i = 0;
  2289. u8 *rateindex_Array[] = { "1M", "2M", "5.5M", "11M", "6M", "9M", "12M", "18M", "24M", "36M", "48M", "54M",
  2290. "HTMCS0", "HTMCS1", "HTMCS2", "HTMCS3", "HTMCS4", "HTMCS5", "HTMCS6", "HTMCS7",
  2291. "HTMCS8", "HTMCS9", "HTMCS10", "HTMCS11", "HTMCS12", "HTMCS13", "HTMCS14", "HTMCS15",
  2292. "HTMCS16", "HTMCS17", "HTMCS18", "HTMCS19", "HTMCS20", "HTMCS21", "HTMCS22", "HTMCS23",
  2293. "HTMCS24", "HTMCS25", "HTMCS26", "HTMCS27", "HTMCS28", "HTMCS29", "HTMCS30", "HTMCS31",
  2294. "VHT1MCS0", "VHT1MCS1", "VHT1MCS2", "VHT1MCS3", "VHT1MCS4", "VHT1MCS5", "VHT1MCS6", "VHT1MCS7", "VHT1MCS8", "VHT1MCS9",
  2295. "VHT2MCS0", "VHT2MCS1", "VHT2MCS2", "VHT2MCS3", "VHT2MCS4", "VHT2MCS5", "VHT2MCS6", "VHT2MCS7", "VHT2MCS8", "VHT2MCS9",
  2296. "VHT3MCS0", "VHT3MCS1", "VHT3MCS2", "VHT3MCS3", "VHT3MCS4", "VHT3MCS5", "VHT3MCS6", "VHT3MCS7", "VHT3MCS8", "VHT3MCS9",
  2297. "VHT4MCS0", "VHT4MCS1", "VHT4MCS2", "VHT4MCS3", "VHT4MCS4", "VHT4MCS5", "VHT4MCS6", "VHT4MCS7", "VHT4MCS8", "VHT4MCS9"
  2298. };
  2299. for (i = 0; i <= 83; i++) {
  2300. if (strcmp(targetStr, rateindex_Array[i]) == 0) {
  2301. RTW_INFO("%s , index = %d\n", __func__ , i);
  2302. return i;
  2303. }
  2304. }
  2305. printk("%s ,please input a Data RATE String as:", __func__);
  2306. for (i = 0; i <= 83; i++) {
  2307. printk("%s ", rateindex_Array[i]);
  2308. if (i % 10 == 0)
  2309. printk("\n");
  2310. }
  2311. return _FAIL;
  2312. }
  2313. ULONG mpt_ProQueryCalTxPower(
  2314. PADAPTER pAdapter,
  2315. u8 RfPath
  2316. )
  2317. {
  2318. HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
  2319. PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
  2320. ULONG TxPower = 1;
  2321. u1Byte rate = 0;
  2322. struct txpwr_idx_comp tic;
  2323. u8 mgn_rate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
  2324. TxPower = rtw_hal_get_tx_power_index(pAdapter, RfPath, mgn_rate, pHalData->current_channel_bw, pHalData->current_channel, &tic);
  2325. RTW_INFO("bw=%d, ch=%d, rate=%d, txPower:%u = %u + (%d=%d:%d) + (%d) + (%d)\n",
  2326. pHalData->current_channel_bw, pHalData->current_channel, mgn_rate
  2327. , TxPower, tic.base, (tic.by_rate > tic.limit ? tic.limit : tic.by_rate), tic.by_rate, tic.limit, tic.tpt, tic.ebias);
  2328. pAdapter->mppriv.txpoweridx = (u8)TxPower;
  2329. pMptCtx->TxPwrLevel[ODM_RF_PATH_A] = (u8)TxPower;
  2330. pMptCtx->TxPwrLevel[ODM_RF_PATH_B] = (u8)TxPower;
  2331. pMptCtx->TxPwrLevel[ODM_RF_PATH_C] = (u8)TxPower;
  2332. pMptCtx->TxPwrLevel[ODM_RF_PATH_D] = (u8)TxPower;
  2333. hal_mpt_SetTxPower(pAdapter);
  2334. return TxPower;
  2335. }
  2336. #ifdef CONFIG_MP_VHT_HW_TX_MODE
  2337. static inline void dump_buf(u8 *buf, u32 len)
  2338. {
  2339. u32 i;
  2340. RTW_INFO("-----------------Len %d----------------\n", len);
  2341. for (i = 0; i < len; i++)
  2342. RTW_INFO("%2.2x-", *(buf + i));
  2343. RTW_INFO("\n");
  2344. }
  2345. void ByteToBit(
  2346. UCHAR *out,
  2347. bool *in,
  2348. UCHAR in_size)
  2349. {
  2350. UCHAR i = 0, j = 0;
  2351. for (i = 0; i < in_size; i++) {
  2352. for (j = 0; j < 8; j++) {
  2353. if (in[8 * i + j])
  2354. out[i] |= (1 << j);
  2355. }
  2356. }
  2357. }
  2358. void CRC16_generator(
  2359. bool *out,
  2360. bool *in,
  2361. UCHAR in_size
  2362. )
  2363. {
  2364. UCHAR i = 0;
  2365. bool temp = 0, reg[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};
  2366. for (i = 0; i < in_size; i++) {/* take one's complement and bit reverse*/
  2367. temp = in[i] ^ reg[15];
  2368. reg[15] = reg[14];
  2369. reg[14] = reg[13];
  2370. reg[13] = reg[12];
  2371. reg[12] = reg[11];
  2372. reg[11] = reg[10];
  2373. reg[10] = reg[9];
  2374. reg[9] = reg[8];
  2375. reg[8] = reg[7];
  2376. reg[7] = reg[6];
  2377. reg[6] = reg[5];
  2378. reg[5] = reg[4];
  2379. reg[4] = reg[3];
  2380. reg[3] = reg[2];
  2381. reg[2] = reg[1];
  2382. reg[1] = reg[0];
  2383. reg[12] = reg[12] ^ temp;
  2384. reg[5] = reg[5] ^ temp;
  2385. reg[0] = temp;
  2386. }
  2387. for (i = 0; i < 16; i++) /* take one's complement and bit reverse*/
  2388. out[i] = 1 - reg[15 - i];
  2389. }
  2390. /*========================================
  2391. SFD SIGNAL SERVICE LENGTH CRC
  2392. 16 bit 8 bit 8 bit 16 bit 16 bit
  2393. ========================================*/
  2394. void CCK_generator(
  2395. PRT_PMAC_TX_INFO pPMacTxInfo,
  2396. PRT_PMAC_PKT_INFO pPMacPktInfo
  2397. )
  2398. {
  2399. double ratio = 0;
  2400. bool crc16_in[32] = {0}, crc16_out[16] = {0};
  2401. bool LengthExtBit;
  2402. double LengthExact;
  2403. double LengthPSDU;
  2404. UCHAR i;
  2405. UINT PacketLength = pPMacTxInfo->PacketLength;
  2406. if (pPMacTxInfo->bSPreamble)
  2407. pPMacTxInfo->SFD = 0x05CF;
  2408. else
  2409. pPMacTxInfo->SFD = 0xF3A0;
  2410. switch (pPMacPktInfo->MCS) {
  2411. case 0:
  2412. pPMacTxInfo->SignalField = 0xA;
  2413. ratio = 8;
  2414. /*CRC16_in(1,0:7)=[0 1 0 1 0 0 0 0]*/
  2415. crc16_in[1] = crc16_in[3] = 1;
  2416. break;
  2417. case 1:
  2418. pPMacTxInfo->SignalField = 0x14;
  2419. ratio = 4;
  2420. /*CRC16_in(1,0:7)=[0 0 1 0 1 0 0 0];*/
  2421. crc16_in[2] = crc16_in[4] = 1;
  2422. break;
  2423. case 2:
  2424. pPMacTxInfo->SignalField = 0x37;
  2425. ratio = 8.0 / 5.5;
  2426. /*CRC16_in(1,0:7)=[1 1 1 0 1 1 0 0];*/
  2427. crc16_in[0] = crc16_in[1] = crc16_in[2] = crc16_in[4] = crc16_in[5] = 1;
  2428. break;
  2429. case 3:
  2430. pPMacTxInfo->SignalField = 0x6E;
  2431. ratio = 8.0 / 11.0;
  2432. /*CRC16_in(1,0:7)=[0 1 1 1 0 1 1 0];*/
  2433. crc16_in[1] = crc16_in[2] = crc16_in[3] = crc16_in[5] = crc16_in[6] = 1;
  2434. break;
  2435. }
  2436. LengthExact = PacketLength * ratio;
  2437. LengthPSDU = ceil(LengthExact);
  2438. if ((pPMacPktInfo->MCS == 3) &&
  2439. ((LengthPSDU - LengthExact) >= 0.727 || (LengthPSDU - LengthExact) <= -0.727))
  2440. LengthExtBit = 1;
  2441. else
  2442. LengthExtBit = 0;
  2443. pPMacTxInfo->LENGTH = (UINT)LengthPSDU;
  2444. /* CRC16_in(1,16:31) = LengthPSDU[0:15]*/
  2445. for (i = 0; i < 16; i++)
  2446. crc16_in[i + 16] = (pPMacTxInfo->LENGTH >> i) & 0x1;
  2447. if (LengthExtBit == 0) {
  2448. pPMacTxInfo->ServiceField = 0x0;
  2449. /* CRC16_in(1,8:15) = [0 0 0 0 0 0 0 0];*/
  2450. } else {
  2451. pPMacTxInfo->ServiceField = 0x80;
  2452. /*CRC16_in(1,8:15)=[0 0 0 0 0 0 0 1];*/
  2453. crc16_in[15] = 1;
  2454. }
  2455. CRC16_generator(crc16_out, crc16_in, 32);
  2456. _rtw_memset(pPMacTxInfo->CRC16, 0, 2);
  2457. ByteToBit(pPMacTxInfo->CRC16, crc16_out, 2);
  2458. }
  2459. void PMAC_Get_Pkt_Param(
  2460. PRT_PMAC_TX_INFO pPMacTxInfo,
  2461. PRT_PMAC_PKT_INFO pPMacPktInfo)
  2462. {
  2463. UCHAR TX_RATE_HEX = 0, MCS = 0;
  2464. UCHAR TX_RATE = pPMacTxInfo->TX_RATE;
  2465. /* TX_RATE & Nss */
  2466. if (MPT_IS_2SS_RATE(TX_RATE))
  2467. pPMacPktInfo->Nss = 2;
  2468. else if (MPT_IS_3SS_RATE(TX_RATE))
  2469. pPMacPktInfo->Nss = 3;
  2470. else if (MPT_IS_4SS_RATE(TX_RATE))
  2471. pPMacPktInfo->Nss = 4;
  2472. else
  2473. pPMacPktInfo->Nss = 1;
  2474. RTW_INFO("PMacTxInfo.Nss =%d\n", pPMacPktInfo->Nss);
  2475. /* MCS & TX_RATE_HEX*/
  2476. if (MPT_IS_CCK_RATE(TX_RATE)) {
  2477. switch (TX_RATE) {
  2478. case MPT_RATE_1M:
  2479. TX_RATE_HEX = MCS = 0;
  2480. break;
  2481. case MPT_RATE_2M:
  2482. TX_RATE_HEX = MCS = 1;
  2483. break;
  2484. case MPT_RATE_55M:
  2485. TX_RATE_HEX = MCS = 2;
  2486. break;
  2487. case MPT_RATE_11M:
  2488. TX_RATE_HEX = MCS = 3;
  2489. break;
  2490. }
  2491. } else if (MPT_IS_OFDM_RATE(TX_RATE)) {
  2492. MCS = TX_RATE - MPT_RATE_6M;
  2493. TX_RATE_HEX = MCS + 4;
  2494. } else if (MPT_IS_HT_RATE(TX_RATE)) {
  2495. MCS = TX_RATE - MPT_RATE_MCS0;
  2496. TX_RATE_HEX = MCS + 12;
  2497. } else if (MPT_IS_VHT_RATE(TX_RATE)) {
  2498. TX_RATE_HEX = TX_RATE - MPT_RATE_VHT1SS_MCS0 + 44;
  2499. if (MPT_IS_VHT_2S_RATE(TX_RATE))
  2500. MCS = TX_RATE - MPT_RATE_VHT2SS_MCS0;
  2501. else if (MPT_IS_VHT_3S_RATE(TX_RATE))
  2502. MCS = TX_RATE - MPT_RATE_VHT3SS_MCS0;
  2503. else if (MPT_IS_VHT_4S_RATE(TX_RATE))
  2504. MCS = TX_RATE - MPT_RATE_VHT4SS_MCS0;
  2505. else
  2506. MCS = TX_RATE - MPT_RATE_VHT1SS_MCS0;
  2507. }
  2508. pPMacPktInfo->MCS = MCS;
  2509. pPMacTxInfo->TX_RATE_HEX = TX_RATE_HEX;
  2510. RTW_INFO(" MCS=%d, TX_RATE_HEX =0x%x\n", MCS, pPMacTxInfo->TX_RATE_HEX);
  2511. /* mSTBC & Nsts*/
  2512. pPMacPktInfo->Nsts = pPMacPktInfo->Nss;
  2513. if (pPMacTxInfo->bSTBC) {
  2514. if (pPMacPktInfo->Nss == 1) {
  2515. pPMacTxInfo->m_STBC = 2;
  2516. pPMacPktInfo->Nsts = pPMacPktInfo->Nss * 2;
  2517. } else
  2518. pPMacTxInfo->m_STBC = 1;
  2519. } else
  2520. pPMacTxInfo->m_STBC = 1;
  2521. }
  2522. UINT LDPC_parameter_generator(
  2523. UINT N_pld_int,
  2524. UINT N_CBPSS,
  2525. UINT N_SS,
  2526. UINT R,
  2527. UINT m_STBC,
  2528. UINT N_TCB_int
  2529. )
  2530. {
  2531. double CR = 0.;
  2532. double N_pld = (double)N_pld_int;
  2533. double N_TCB = (double)N_TCB_int;
  2534. double N_CW = 0., N_shrt = 0., N_spcw = 0., N_fshrt = 0.;
  2535. double L_LDPC = 0., K_LDPC = 0., L_LDPC_info = 0.;
  2536. double N_punc = 0., N_ppcw = 0., N_fpunc = 0., N_rep = 0., N_rpcw = 0., N_frep = 0.;
  2537. double R_eff = 0.;
  2538. UINT VHTSIGA2B3 = 0;/* extra symbol from VHT-SIG-A2 Bit 3*/
  2539. if (R == 0)
  2540. CR = 0.5;
  2541. else if (R == 1)
  2542. CR = 2. / 3.;
  2543. else if (R == 2)
  2544. CR = 3. / 4.;
  2545. else if (R == 3)
  2546. CR = 5. / 6.;
  2547. if (N_TCB <= 648.) {
  2548. N_CW = 1.;
  2549. if (N_TCB >= N_pld + 912.*(1. - CR))
  2550. L_LDPC = 1296.;
  2551. else
  2552. L_LDPC = 648.;
  2553. } else if (N_TCB <= 1296.) {
  2554. N_CW = 1.;
  2555. if (N_TCB >= (double)N_pld + 1464.*(1. - CR))
  2556. L_LDPC = 1944.;
  2557. else
  2558. L_LDPC = 1296.;
  2559. } else if (N_TCB <= 1944.) {
  2560. N_CW = 1.;
  2561. L_LDPC = 1944.;
  2562. } else if (N_TCB <= 2592.) {
  2563. N_CW = 2.;
  2564. if (N_TCB >= N_pld + 2916.*(1. - CR))
  2565. L_LDPC = 1944.;
  2566. else
  2567. L_LDPC = 1296.;
  2568. } else {
  2569. N_CW = ceil(N_pld / 1944. / CR);
  2570. L_LDPC = 1944.;
  2571. }
  2572. /* Number of information bits per CW*/
  2573. K_LDPC = L_LDPC * CR;
  2574. /* Number of shortening bits max(0, (N_CW * L_LDPC * R) - N_pld)*/
  2575. N_shrt = (N_CW * K_LDPC - N_pld) > 0. ? (N_CW * K_LDPC - N_pld) : 0.;
  2576. /* Number of shortening bits per CW N_spcw = rtfloor(N_shrt/N_CW)*/
  2577. N_spcw = rtfloor(N_shrt / N_CW);
  2578. /* The first N_fshrt CWs shorten 1 bit more*/
  2579. N_fshrt = (double)((int)N_shrt % (int)N_CW);
  2580. /* Number of data bits for the last N_CW-N_fshrt CWs*/
  2581. L_LDPC_info = K_LDPC - N_spcw;
  2582. /* Number of puncturing bits*/
  2583. N_punc = (N_CW * L_LDPC - N_TCB - N_shrt) > 0. ? (N_CW * L_LDPC - N_TCB - N_shrt) : 0.;
  2584. if (((N_punc > .1 * N_CW * L_LDPC * (1. - CR)) && (N_shrt < 1.2 * N_punc * CR / (1. - CR))) ||
  2585. (N_punc > 0.3 * N_CW * L_LDPC * (1. - CR))) {
  2586. /*cout << "*** N_TCB and N_punc are Recomputed ***" << endl;*/
  2587. VHTSIGA2B3 = 1;
  2588. N_TCB += (double)N_CBPSS * N_SS * m_STBC;
  2589. N_punc = (N_CW * L_LDPC - N_TCB - N_shrt) > 0. ? (N_CW * L_LDPC - N_TCB - N_shrt) : 0.;
  2590. } else
  2591. VHTSIGA2B3 = 0;
  2592. return VHTSIGA2B3;
  2593. } /* function end of LDPC_parameter_generator */
  2594. /*========================================
  2595. Data field of PPDU
  2596. Get N_sym and SIGA2BB3
  2597. ========================================*/
  2598. void PMAC_Nsym_generator(
  2599. PRT_PMAC_TX_INFO pPMacTxInfo,
  2600. PRT_PMAC_PKT_INFO pPMacPktInfo)
  2601. {
  2602. UINT SIGA2B3 = 0;
  2603. UCHAR TX_RATE = pPMacTxInfo->TX_RATE;
  2604. UINT R, R_list[10] = {0, 0, 2, 0, 2, 1, 2, 3, 2, 3};
  2605. double CR = 0;
  2606. UINT N_SD, N_BPSC_list[10] = {1, 2, 2, 4, 4, 6, 6, 6, 8, 8};
  2607. UINT N_BPSC = 0, N_CBPS = 0, N_DBPS = 0, N_ES = 0, N_SYM = 0, N_pld = 0, N_TCB = 0;
  2608. int D_R = 0;
  2609. RTW_INFO("TX_RATE = %d\n", TX_RATE);
  2610. /* N_SD*/
  2611. if (pPMacTxInfo->BandWidth == 0)
  2612. N_SD = 52;
  2613. else if (pPMacTxInfo->BandWidth == 1)
  2614. N_SD = 108;
  2615. else
  2616. N_SD = 234;
  2617. if (MPT_IS_HT_RATE(TX_RATE)) {
  2618. UCHAR MCS_temp;
  2619. if (pPMacPktInfo->MCS > 23)
  2620. MCS_temp = pPMacPktInfo->MCS - 24;
  2621. else if (pPMacPktInfo->MCS > 15)
  2622. MCS_temp = pPMacPktInfo->MCS - 16;
  2623. else if (pPMacPktInfo->MCS > 7)
  2624. MCS_temp = pPMacPktInfo->MCS - 8;
  2625. else
  2626. MCS_temp = pPMacPktInfo->MCS;
  2627. R = R_list[MCS_temp];
  2628. switch (R) {
  2629. case 0:
  2630. CR = .5;
  2631. break;
  2632. case 1:
  2633. CR = 2. / 3.;
  2634. break;
  2635. case 2:
  2636. CR = 3. / 4.;
  2637. break;
  2638. case 3:
  2639. CR = 5. / 6.;
  2640. break;
  2641. }
  2642. N_BPSC = N_BPSC_list[MCS_temp];
  2643. N_CBPS = N_BPSC * N_SD * pPMacPktInfo->Nss;
  2644. N_DBPS = (UINT)((double)N_CBPS * CR);
  2645. if (pPMacTxInfo->bLDPC == FALSE) {
  2646. N_ES = (UINT)ceil((double)(N_DBPS * pPMacPktInfo->Nss) / 4. / 300.);
  2647. RTW_INFO("N_ES = %d\n", N_ES);
  2648. /* N_SYM = m_STBC* (8*length+16+6*N_ES) / (m_STBC*N_DBPS)*/
  2649. N_SYM = pPMacTxInfo->m_STBC * (UINT)ceil((double)(pPMacTxInfo->PacketLength * 8 + 16 + N_ES * 6) /
  2650. (double)(N_DBPS * pPMacTxInfo->m_STBC));
  2651. } else {
  2652. N_ES = 1;
  2653. /* N_pld = length * 8 + 16*/
  2654. N_pld = pPMacTxInfo->PacketLength * 8 + 16;
  2655. RTW_INFO("N_pld = %d\n", N_pld);
  2656. N_SYM = pPMacTxInfo->m_STBC * (UINT)ceil((double)(N_pld) /
  2657. (double)(N_DBPS * pPMacTxInfo->m_STBC));
  2658. RTW_INFO("N_SYM = %d\n", N_SYM);
  2659. /* N_avbits = N_CBPS *m_STBC *(N_pld/N_CBPS*R*m_STBC)*/
  2660. N_TCB = N_CBPS * N_SYM;
  2661. RTW_INFO("N_TCB = %d\n", N_TCB);
  2662. SIGA2B3 = LDPC_parameter_generator(N_pld, N_CBPS, pPMacPktInfo->Nss, R, pPMacTxInfo->m_STBC, N_TCB);
  2663. RTW_INFO("SIGA2B3 = %d\n", SIGA2B3);
  2664. N_SYM = N_SYM + SIGA2B3 * pPMacTxInfo->m_STBC;
  2665. RTW_INFO("N_SYM = %d\n", N_SYM);
  2666. }
  2667. } else if (MPT_IS_VHT_RATE(TX_RATE)) {
  2668. R = R_list[pPMacPktInfo->MCS];
  2669. switch (R) {
  2670. case 0:
  2671. CR = .5;
  2672. break;
  2673. case 1:
  2674. CR = 2. / 3.;
  2675. break;
  2676. case 2:
  2677. CR = 3. / 4.;
  2678. break;
  2679. case 3:
  2680. CR = 5. / 6.;
  2681. break;
  2682. }
  2683. N_BPSC = N_BPSC_list[pPMacPktInfo->MCS];
  2684. N_CBPS = N_BPSC * N_SD * pPMacPktInfo->Nss;
  2685. N_DBPS = (UINT)((double)N_CBPS * CR);
  2686. if (pPMacTxInfo->bLDPC == FALSE) {
  2687. if (pPMacTxInfo->bSGI)
  2688. N_ES = (UINT)ceil((double)(N_DBPS) / 3.6 / 600.);
  2689. else
  2690. N_ES = (UINT)ceil((double)(N_DBPS) / 4. / 600.);
  2691. /* N_SYM = m_STBC* (8*length+16+6*N_ES) / (m_STBC*N_DBPS)*/
  2692. N_SYM = pPMacTxInfo->m_STBC * (UINT)ceil((double)(pPMacTxInfo->PacketLength * 8 + 16 + N_ES * 6) / (double)(N_DBPS * pPMacTxInfo->m_STBC));
  2693. SIGA2B3 = 0;
  2694. } else {
  2695. N_ES = 1;
  2696. /* N_SYM = m_STBC* (8*length+N_service) / (m_STBC*N_DBPS)*/
  2697. N_SYM = pPMacTxInfo->m_STBC * (UINT)ceil((double)(pPMacTxInfo->PacketLength * 8 + 16) / (double)(N_DBPS * pPMacTxInfo->m_STBC));
  2698. /* N_avbits = N_sys_init * N_CBPS*/
  2699. N_TCB = N_CBPS * N_SYM;
  2700. /* N_pld = N_sys_init * N_DBPS*/
  2701. N_pld = N_SYM * N_DBPS;
  2702. SIGA2B3 = LDPC_parameter_generator(N_pld, N_CBPS, pPMacPktInfo->Nss, R, pPMacTxInfo->m_STBC, N_TCB);
  2703. N_SYM = N_SYM + SIGA2B3 * pPMacTxInfo->m_STBC;
  2704. }
  2705. switch (R) {
  2706. case 0:
  2707. D_R = 2;
  2708. break;
  2709. case 1:
  2710. D_R = 3;
  2711. break;
  2712. case 2:
  2713. D_R = 4;
  2714. break;
  2715. case 3:
  2716. D_R = 6;
  2717. break;
  2718. }
  2719. if (((N_CBPS / N_ES) % D_R) != 0) {
  2720. RTW_INFO("MCS= %d is not supported when Nss=%d and BW= %d !!\n", pPMacPktInfo->MCS, pPMacPktInfo->Nss, pPMacTxInfo->BandWidth);
  2721. return;
  2722. }
  2723. RTW_INFO("MCS= %d Nss=%d and BW= %d !!\n", pPMacPktInfo->MCS, pPMacPktInfo->Nss, pPMacTxInfo->BandWidth);
  2724. }
  2725. pPMacPktInfo->N_sym = N_SYM;
  2726. pPMacPktInfo->SIGA2B3 = SIGA2B3;
  2727. }
  2728. /*========================================
  2729. L-SIG Rate R Length P Tail
  2730. 4b 1b 12b 1b 6b
  2731. ========================================*/
  2732. void L_SIG_generator(
  2733. UINT N_SYM, /* Max: 750*/
  2734. PRT_PMAC_TX_INFO pPMacTxInfo,
  2735. PRT_PMAC_PKT_INFO pPMacPktInfo)
  2736. {
  2737. u8 sig_bi[24] = {0}; /* 24 BIT*/
  2738. UINT mode, LENGTH;
  2739. int i;
  2740. if (MPT_IS_OFDM_RATE(pPMacTxInfo->TX_RATE)) {
  2741. mode = pPMacPktInfo->MCS;
  2742. LENGTH = pPMacTxInfo->PacketLength;
  2743. } else {
  2744. UCHAR N_LTF;
  2745. double T_data;
  2746. UINT OFDM_symbol;
  2747. mode = 0;
  2748. /* Table 20-13 Num of HT-DLTFs request*/
  2749. if (pPMacPktInfo->Nsts <= 2)
  2750. N_LTF = pPMacPktInfo->Nsts;
  2751. else
  2752. N_LTF = 4;
  2753. if (pPMacTxInfo->bSGI)
  2754. T_data = 3.6;
  2755. else
  2756. T_data = 4.0;
  2757. /*(L-SIG, HT-SIG, HT-STF, HT-LTF....HT-LTF, Data)*/
  2758. if (MPT_IS_VHT_RATE(pPMacTxInfo->TX_RATE))
  2759. OFDM_symbol = (UINT)ceil((double)(8 + 4 + N_LTF * 4 + N_SYM * T_data + 4) / 4.);
  2760. else
  2761. OFDM_symbol = (UINT)ceil((double)(8 + 4 + N_LTF * 4 + N_SYM * T_data) / 4.);
  2762. RTW_INFO("%s , OFDM_symbol =%d\n", __func__, OFDM_symbol);
  2763. LENGTH = OFDM_symbol * 3 - 3;
  2764. RTW_INFO("%s , LENGTH =%d\n", __func__, LENGTH);
  2765. }
  2766. /* Rate Field*/
  2767. switch (mode) {
  2768. case 0:
  2769. sig_bi[0] = 1;
  2770. sig_bi[1] = 1;
  2771. sig_bi[2] = 0;
  2772. sig_bi[3] = 1;
  2773. break;
  2774. case 1:
  2775. sig_bi[0] = 1;
  2776. sig_bi[1] = 1;
  2777. sig_bi[2] = 1;
  2778. sig_bi[3] = 1;
  2779. break;
  2780. case 2:
  2781. sig_bi[0] = 0;
  2782. sig_bi[1] = 1;
  2783. sig_bi[2] = 0;
  2784. sig_bi[3] = 1;
  2785. break;
  2786. case 3:
  2787. sig_bi[0] = 0;
  2788. sig_bi[1] = 1;
  2789. sig_bi[2] = 1;
  2790. sig_bi[3] = 1;
  2791. break;
  2792. case 4:
  2793. sig_bi[0] = 1;
  2794. sig_bi[1] = 0;
  2795. sig_bi[2] = 0;
  2796. sig_bi[3] = 1;
  2797. break;
  2798. case 5:
  2799. sig_bi[0] = 1;
  2800. sig_bi[1] = 0;
  2801. sig_bi[2] = 1;
  2802. sig_bi[3] = 1;
  2803. break;
  2804. case 6:
  2805. sig_bi[0] = 0;
  2806. sig_bi[1] = 0;
  2807. sig_bi[2] = 0;
  2808. sig_bi[3] = 1;
  2809. break;
  2810. case 7:
  2811. sig_bi[0] = 0;
  2812. sig_bi[1] = 0;
  2813. sig_bi[2] = 1;
  2814. sig_bi[3] = 1;
  2815. break;
  2816. }
  2817. /*Reserved bit*/
  2818. sig_bi[4] = 0;
  2819. /* Length Field*/
  2820. for (i = 0; i < 12; i++)
  2821. sig_bi[i + 5] = (LENGTH >> i) & 1;
  2822. /* Parity Bit*/
  2823. sig_bi[17] = 0;
  2824. for (i = 0; i < 17; i++)
  2825. sig_bi[17] = sig_bi[17] + sig_bi[i];
  2826. sig_bi[17] %= 2;
  2827. /* Tail Field*/
  2828. for (i = 18; i < 24; i++)
  2829. sig_bi[i] = 0;
  2830. /* dump_buf(sig_bi,24);*/
  2831. _rtw_memset(pPMacTxInfo->LSIG, 0, 3);
  2832. ByteToBit(pPMacTxInfo->LSIG, (bool *)sig_bi, 3);
  2833. }
  2834. void CRC8_generator(
  2835. bool *out,
  2836. bool *in,
  2837. UCHAR in_size
  2838. )
  2839. {
  2840. UCHAR i = 0;
  2841. bool temp = 0, reg[] = {1, 1, 1, 1, 1, 1, 1, 1};
  2842. for (i = 0; i < in_size; i++) { /* take one's complement and bit reverse*/
  2843. temp = in[i] ^ reg[7];
  2844. reg[7] = reg[6];
  2845. reg[6] = reg[5];
  2846. reg[5] = reg[4];
  2847. reg[4] = reg[3];
  2848. reg[3] = reg[2];
  2849. reg[2] = reg[1] ^ temp;
  2850. reg[1] = reg[0] ^ temp;
  2851. reg[0] = temp;
  2852. }
  2853. for (i = 0; i < 8; i++)/* take one's complement and bit reverse*/
  2854. out[i] = reg[7 - i] ^ 1;
  2855. }
  2856. /*/================================================================================
  2857. HT-SIG1 MCS CW Length 24BIT + 24BIT
  2858. 7b 1b 16b
  2859. HT-SIG2 Smoothing Not sounding Rsvd AGG STBC FEC SGI N_ELTF CRC Tail
  2860. 1b 1b 1b 1b 2b 1b 1b 2b 8b 6b
  2861. ================================================================================*/
  2862. void HT_SIG_generator(
  2863. PRT_PMAC_TX_INFO pPMacTxInfo,
  2864. PRT_PMAC_PKT_INFO pPMacPktInfo
  2865. )
  2866. {
  2867. UINT i;
  2868. bool sig_bi[48] = {0}, crc8[8] = {0};
  2869. /* MCS Field*/
  2870. for (i = 0; i < 7; i++)
  2871. sig_bi[i] = (pPMacPktInfo->MCS >> i) & 0x1;
  2872. /* Packet BW Setting*/
  2873. sig_bi[7] = pPMacTxInfo->BandWidth;
  2874. /* HT-Length Field*/
  2875. for (i = 0; i < 16; i++)
  2876. sig_bi[i + 8] = (pPMacTxInfo->PacketLength >> i) & 0x1;
  2877. /* Smoothing; 1->allow smoothing*/
  2878. sig_bi[24] = 1;
  2879. /*Not Sounding*/
  2880. sig_bi[25] = 1 - pPMacTxInfo->NDP_sound;
  2881. /*Reserved bit*/
  2882. sig_bi[26] = 1;
  2883. /*/Aggregate*/
  2884. sig_bi[27] = 0;
  2885. /*STBC Field*/
  2886. if (pPMacTxInfo->bSTBC) {
  2887. sig_bi[28] = 1;
  2888. sig_bi[29] = 0;
  2889. } else {
  2890. sig_bi[28] = 0;
  2891. sig_bi[29] = 0;
  2892. }
  2893. /*Advance Coding, 0: BCC, 1: LDPC*/
  2894. sig_bi[30] = pPMacTxInfo->bLDPC;
  2895. /* Short GI*/
  2896. sig_bi[31] = pPMacTxInfo->bSGI;
  2897. /* N_ELTFs*/
  2898. if (pPMacTxInfo->NDP_sound == FALSE) {
  2899. sig_bi[32] = 0;
  2900. sig_bi[33] = 0;
  2901. } else {
  2902. int N_ELTF = pPMacTxInfo->Ntx - pPMacPktInfo->Nss;
  2903. for (i = 0; i < 2; i++)
  2904. sig_bi[32 + i] = (N_ELTF >> i) % 2;
  2905. }
  2906. /* CRC-8*/
  2907. CRC8_generator(crc8, sig_bi, 34);
  2908. for (i = 0; i < 8; i++)
  2909. sig_bi[34 + i] = crc8[i];
  2910. /*Tail*/
  2911. for (i = 42; i < 48; i++)
  2912. sig_bi[i] = 0;
  2913. _rtw_memset(pPMacTxInfo->HT_SIG, 0, 6);
  2914. ByteToBit(pPMacTxInfo->HT_SIG, sig_bi, 6);
  2915. }
  2916. /*======================================================================================
  2917. VHT-SIG-A1
  2918. BW Reserved STBC G_ID SU_Nsts P_AID TXOP_PS_NOT_ALLOW Reserved
  2919. 2b 1b 1b 6b 3b 9b 1b 2b 1b
  2920. VHT-SIG-A2
  2921. SGI SGI_Nsym SU/MU coding LDPC_Extra SU_NCS Beamformed Reserved CRC Tail
  2922. 1b 1b 1b 1b 4b 1b 1b 8b 6b
  2923. ======================================================================================*/
  2924. void VHT_SIG_A_generator(
  2925. PRT_PMAC_TX_INFO pPMacTxInfo,
  2926. PRT_PMAC_PKT_INFO pPMacPktInfo)
  2927. {
  2928. UINT i;
  2929. bool sig_bi[48], crc8[8];
  2930. _rtw_memset(sig_bi, 0, 48);
  2931. _rtw_memset(crc8, 0, 8);
  2932. /* BW Setting*/
  2933. for (i = 0; i < 2; i++)
  2934. sig_bi[i] = (pPMacTxInfo->BandWidth >> i) & 0x1;
  2935. /* Reserved Bit*/
  2936. sig_bi[2] = 1;
  2937. /*STBC Field*/
  2938. sig_bi[3] = pPMacTxInfo->bSTBC;
  2939. /*Group ID: Single User->A value of 0 or 63 indicates an SU PPDU. */
  2940. for (i = 0; i < 6; i++)
  2941. sig_bi[4 + i] = 0;
  2942. /* N_STS/Partial AID*/
  2943. for (i = 0; i < 12; i++) {
  2944. if (i < 3)
  2945. sig_bi[10 + i] = ((pPMacPktInfo->Nsts - 1) >> i) & 0x1;
  2946. else
  2947. sig_bi[10 + i] = 0;
  2948. }
  2949. /*TXOP_PS_NOT_ALLPWED*/
  2950. sig_bi[22] = 0;
  2951. /*Reserved Bits*/
  2952. sig_bi[23] = 1;
  2953. /*Short GI*/
  2954. sig_bi[24] = pPMacTxInfo->bSGI;
  2955. if (pPMacTxInfo->bSGI > 0 && (pPMacPktInfo->N_sym % 10) == 9)
  2956. sig_bi[25] = 1;
  2957. else
  2958. sig_bi[25] = 0;
  2959. /* SU/MU[0] Coding*/
  2960. sig_bi[26] = pPMacTxInfo->bLDPC; /* 0:BCC, 1:LDPC */
  2961. sig_bi[27] = pPMacPktInfo->SIGA2B3; /*/ Record Extra OFDM Symols is added or not when LDPC is used*/
  2962. /*SU MCS/MU[1-3] Coding*/
  2963. for (i = 0; i < 4; i++)
  2964. sig_bi[28 + i] = (pPMacPktInfo->MCS >> i) & 0x1;
  2965. /*SU Beamform */
  2966. sig_bi[32] = 0; /*packet.TXBF_en;*/
  2967. /*Reserved Bit*/
  2968. sig_bi[33] = 1;
  2969. /*CRC-8*/
  2970. CRC8_generator(crc8, sig_bi, 34);
  2971. for (i = 0; i < 8; i++)
  2972. sig_bi[34 + i] = crc8[i];
  2973. /*Tail*/
  2974. for (i = 42; i < 48; i++)
  2975. sig_bi[i] = 0;
  2976. _rtw_memset(pPMacTxInfo->VHT_SIG_A, 0, 6);
  2977. ByteToBit(pPMacTxInfo->VHT_SIG_A, sig_bi, 6);
  2978. }
  2979. /*======================================================================================
  2980. VHT-SIG-B
  2981. Length Resesrved Trail
  2982. 17/19/21 BIT 3/2/2 BIT 6b
  2983. ======================================================================================*/
  2984. void VHT_SIG_B_generator(
  2985. PRT_PMAC_TX_INFO pPMacTxInfo)
  2986. {
  2987. bool sig_bi[32], crc8_bi[8];
  2988. UINT i, len, res, tail = 6, total_len, crc8_in_len;
  2989. UINT sigb_len;
  2990. _rtw_memset(sig_bi, 0, 32);
  2991. _rtw_memset(crc8_bi, 0, 8);
  2992. /*Sounding Packet*/
  2993. if (pPMacTxInfo->NDP_sound == 1) {
  2994. if (pPMacTxInfo->BandWidth == 0) {
  2995. bool sigb_temp[26] = {0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0};
  2996. _rtw_memcpy(sig_bi, sigb_temp, 26);
  2997. } else if (pPMacTxInfo->BandWidth == 1) {
  2998. bool sigb_temp[27] = {1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0};
  2999. _rtw_memcpy(sig_bi, sigb_temp, 27);
  3000. } else if (pPMacTxInfo->BandWidth == 2) {
  3001. bool sigb_temp[29] = {0, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0};
  3002. _rtw_memcpy(sig_bi, sigb_temp, 29);
  3003. }
  3004. } else { /* Not NDP Sounding*/
  3005. bool *sigb_temp[29] = {0};
  3006. if (pPMacTxInfo->BandWidth == 0) {
  3007. len = 17;
  3008. res = 3;
  3009. } else if (pPMacTxInfo->BandWidth == 1) {
  3010. len = 19;
  3011. res = 2;
  3012. } else if (pPMacTxInfo->BandWidth == 2) {
  3013. len = 21;
  3014. res = 2;
  3015. } else {
  3016. len = 21;
  3017. res = 2;
  3018. }
  3019. total_len = len + res + tail;
  3020. crc8_in_len = len + res;
  3021. /*Length Field*/
  3022. sigb_len = (pPMacTxInfo->PacketLength + 3) >> 2;
  3023. for (i = 0; i < len; i++)
  3024. sig_bi[i] = (sigb_len >> i) & 0x1;
  3025. /*Reserved Field*/
  3026. for (i = 0; i < res; i++)
  3027. sig_bi[len + i] = 1;
  3028. /* CRC-8*/
  3029. CRC8_generator(crc8_bi, sig_bi, crc8_in_len);
  3030. /* Tail */
  3031. for (i = 0; i < tail; i++)
  3032. sig_bi[len + res + i] = 0;
  3033. }
  3034. _rtw_memset(pPMacTxInfo->VHT_SIG_B, 0, 4);
  3035. ByteToBit(pPMacTxInfo->VHT_SIG_B, sig_bi, 4);
  3036. pPMacTxInfo->VHT_SIG_B_CRC = 0;
  3037. ByteToBit(&(pPMacTxInfo->VHT_SIG_B_CRC), crc8_bi, 1);
  3038. }
  3039. /*=======================
  3040. VHT Delimiter
  3041. =======================*/
  3042. void VHT_Delimiter_generator(
  3043. PRT_PMAC_TX_INFO pPMacTxInfo
  3044. )
  3045. {
  3046. bool sig_bi[32] = {0}, crc8[8] = {0};
  3047. UINT crc8_in_len = 16;
  3048. UINT PacketLength = pPMacTxInfo->PacketLength;
  3049. int j;
  3050. /* Delimiter[0]: EOF*/
  3051. sig_bi[0] = 1;
  3052. /* Delimiter[1]: Reserved*/
  3053. sig_bi[1] = 0;
  3054. /* Delimiter[3:2]: MPDU Length High*/
  3055. sig_bi[2] = ((PacketLength - 4) >> 12) % 2;
  3056. sig_bi[3] = ((PacketLength - 4) >> 13) % 2;
  3057. /* Delimiter[15:4]: MPDU Length Low*/
  3058. for (j = 4; j < 16; j++)
  3059. sig_bi[j] = ((PacketLength - 4) >> (j - 4)) % 2;
  3060. CRC8_generator(crc8, sig_bi, crc8_in_len);
  3061. for (j = 16; j < 24; j++) /* Delimiter[23:16]: CRC 8*/
  3062. sig_bi[j] = crc8[j - 16];
  3063. for (j = 24; j < 32; j++) /* Delimiter[31:24]: Signature ('4E' in Hex, 78 in Dec)*/
  3064. sig_bi[j] = (78 >> (j - 24)) % 2;
  3065. _rtw_memset(pPMacTxInfo->VHT_Delimiter, 0, 4);
  3066. ByteToBit(pPMacTxInfo->VHT_Delimiter, sig_bi, 4);
  3067. }
  3068. #endif
  3069. #endif