hal_intf.c 39 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. *
  19. ******************************************************************************/
  20. #define _HAL_INTF_C_
  21. #include <drv_types.h>
  22. #include <hal_data.h>
  23. const u32 _chip_type_to_odm_ic_type[] = {
  24. 0,
  25. ODM_RTL8188E,
  26. ODM_RTL8192E,
  27. ODM_RTL8812,
  28. ODM_RTL8821,
  29. ODM_RTL8723B,
  30. ODM_RTL8814A,
  31. ODM_RTL8703B,
  32. ODM_RTL8188F,
  33. ODM_RTL8822B,
  34. ODM_RTL8723D,
  35. ODM_RTL8821C,
  36. 0,
  37. };
  38. void rtw_hal_chip_configure(_adapter *padapter)
  39. {
  40. padapter->hal_func.intf_chip_configure(padapter);
  41. }
  42. /*
  43. * Description:
  44. * Read chip internal ROM data
  45. *
  46. * Return:
  47. * _SUCCESS success
  48. * _FAIL fail
  49. */
  50. u8 rtw_hal_read_chip_info(_adapter *padapter)
  51. {
  52. u8 rtn = _SUCCESS;
  53. u8 hci_type = rtw_get_intf_type(padapter);
  54. u32 start = rtw_get_current_time();
  55. /* before access eFuse, make sure card enable has been called */
  56. if ((hci_type == RTW_SDIO || hci_type == RTW_GSPI)
  57. && !rtw_is_hw_init_completed(padapter))
  58. rtw_hal_power_on(padapter);
  59. rtn = padapter->hal_func.read_adapter_info(padapter);
  60. if ((hci_type == RTW_SDIO || hci_type == RTW_GSPI)
  61. && !rtw_is_hw_init_completed(padapter))
  62. rtw_hal_power_off(padapter);
  63. RTW_INFO("%s in %d ms\n", __func__, rtw_get_passing_time_ms(start));
  64. return rtn;
  65. }
  66. void rtw_hal_read_chip_version(_adapter *padapter)
  67. {
  68. padapter->hal_func.read_chip_version(padapter);
  69. rtw_odm_init_ic_type(padapter);
  70. }
  71. void rtw_hal_def_value_init(_adapter *padapter)
  72. {
  73. if (is_primary_adapter(padapter)) {
  74. padapter->hal_func.init_default_value(padapter);
  75. rtw_init_hal_com_default_value(padapter);
  76. {
  77. struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
  78. struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
  79. /* hal_spec is ready here */
  80. dvobj->macid_ctl.num = rtw_min(hal_spec->macid_num, MACID_NUM_SW_LIMIT);
  81. dvobj->cam_ctl.sec_cap = hal_spec->sec_cap;
  82. dvobj->cam_ctl.num = rtw_min(hal_spec->sec_cam_ent_num, SEC_CAM_ENT_NUM_SW_LIMIT);
  83. }
  84. }
  85. }
  86. u8 rtw_hal_data_init(_adapter *padapter)
  87. {
  88. if (is_primary_adapter(padapter)) {
  89. padapter->hal_data_sz = sizeof(HAL_DATA_TYPE);
  90. padapter->HalData = rtw_zvmalloc(padapter->hal_data_sz);
  91. if (padapter->HalData == NULL) {
  92. RTW_INFO("cant not alloc memory for HAL DATA\n");
  93. return _FAIL;
  94. }
  95. }
  96. return _SUCCESS;
  97. }
  98. void rtw_hal_data_deinit(_adapter *padapter)
  99. {
  100. if (is_primary_adapter(padapter)) {
  101. if (padapter->HalData) {
  102. #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
  103. phy_free_filebuf(padapter);
  104. #endif
  105. rtw_vmfree(padapter->HalData, padapter->hal_data_sz);
  106. padapter->HalData = NULL;
  107. padapter->hal_data_sz = 0;
  108. }
  109. }
  110. }
  111. void rtw_hal_free_data(_adapter *padapter)
  112. {
  113. /* free HAL Data */
  114. rtw_hal_data_deinit(padapter);
  115. }
  116. void rtw_hal_dm_init(_adapter *padapter)
  117. {
  118. if (is_primary_adapter(padapter)) {
  119. PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
  120. padapter->hal_func.dm_init(padapter);
  121. _rtw_spinlock_init(&pHalData->IQKSpinLock);
  122. phy_load_tx_power_ext_info(padapter, 1);
  123. }
  124. }
  125. void rtw_hal_dm_deinit(_adapter *padapter)
  126. {
  127. if (is_primary_adapter(padapter)) {
  128. PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
  129. padapter->hal_func.dm_deinit(padapter);
  130. _rtw_spinlock_free(&pHalData->IQKSpinLock);
  131. }
  132. }
  133. void rtw_hal_sw_led_init(_adapter *padapter)
  134. {
  135. if (padapter->hal_func.InitSwLeds)
  136. padapter->hal_func.InitSwLeds(padapter);
  137. }
  138. void rtw_hal_sw_led_deinit(_adapter *padapter)
  139. {
  140. if (padapter->hal_func.DeInitSwLeds)
  141. padapter->hal_func.DeInitSwLeds(padapter);
  142. }
  143. u32 rtw_hal_power_on(_adapter *padapter)
  144. {
  145. u32 ret = 0;
  146. ret = padapter->hal_func.hal_power_on(padapter);
  147. #ifdef CONFIG_BT_COEXIST
  148. if (ret == _SUCCESS)
  149. rtw_btcoex_PowerOnSetting(padapter);
  150. #endif
  151. return ret;
  152. }
  153. void rtw_hal_power_off(_adapter *padapter)
  154. {
  155. struct macid_ctl_t *macid_ctl = &padapter->dvobj->macid_ctl;
  156. _rtw_memset(macid_ctl->h2c_msr, 0, MACID_NUM_SW_LIMIT);
  157. #ifdef CONFIG_BT_COEXIST
  158. rtw_btcoex_PowerOffSetting(padapter);
  159. #endif
  160. padapter->hal_func.hal_power_off(padapter);
  161. }
  162. void rtw_hal_init_opmode(_adapter *padapter)
  163. {
  164. NDIS_802_11_NETWORK_INFRASTRUCTURE networkType = Ndis802_11InfrastructureMax;
  165. struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
  166. sint fw_state;
  167. fw_state = get_fwstate(pmlmepriv);
  168. if (fw_state & WIFI_ADHOC_STATE)
  169. networkType = Ndis802_11IBSS;
  170. else if (fw_state & WIFI_STATION_STATE)
  171. networkType = Ndis802_11Infrastructure;
  172. else if (fw_state & WIFI_AP_STATE)
  173. networkType = Ndis802_11APMode;
  174. else
  175. return;
  176. rtw_setopmode_cmd(padapter, networkType, _FALSE);
  177. }
  178. uint rtw_hal_init(_adapter *padapter)
  179. {
  180. uint status = _SUCCESS;
  181. struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
  182. PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
  183. int i;
  184. status = padapter->hal_func.hal_init(padapter);
  185. if (status == _SUCCESS) {
  186. pHalData->hw_init_completed = _TRUE;
  187. rtw_restore_mac_addr(padapter);
  188. if (padapter->registrypriv.notch_filter == 1)
  189. rtw_hal_notch_filter(padapter, 1);
  190. for (i = 0; i < dvobj->iface_nums; i++)
  191. rtw_sec_restore_wep_key(dvobj->padapters[i]);
  192. rtw_led_control(padapter, LED_CTL_POWER_ON);
  193. init_hw_mlme_ext(padapter);
  194. rtw_hal_init_opmode(padapter);
  195. #ifdef CONFIG_RF_POWER_TRIM
  196. rtw_bb_rf_gain_offset(padapter);
  197. #endif /*CONFIG_RF_POWER_TRIM*/
  198. } else {
  199. pHalData->hw_init_completed = _FALSE;
  200. RTW_INFO("rtw_hal_init: hal_init fail\n");
  201. }
  202. return status;
  203. }
  204. uint rtw_hal_deinit(_adapter *padapter)
  205. {
  206. uint status = _SUCCESS;
  207. struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
  208. PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
  209. int i;
  210. status = padapter->hal_func.hal_deinit(padapter);
  211. if (status == _SUCCESS) {
  212. rtw_led_control(padapter, LED_CTL_POWER_OFF);
  213. pHalData->hw_init_completed = _FALSE;
  214. } else
  215. RTW_INFO("\n rtw_hal_deinit: hal_init fail\n");
  216. return status;
  217. }
  218. void rtw_hal_set_hwreg(_adapter *padapter, u8 variable, u8 *val)
  219. {
  220. padapter->hal_func.set_hw_reg_handler(padapter, variable, val);
  221. }
  222. void rtw_hal_get_hwreg(_adapter *padapter, u8 variable, u8 *val)
  223. {
  224. padapter->hal_func.GetHwRegHandler(padapter, variable, val);
  225. }
  226. u8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue)
  227. {
  228. return padapter->hal_func.SetHalDefVarHandler(padapter, eVariable, pValue);
  229. }
  230. u8 rtw_hal_get_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue)
  231. {
  232. return padapter->hal_func.get_hal_def_var_handler(padapter, eVariable, pValue);
  233. }
  234. void rtw_hal_set_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1, BOOLEAN bSet)
  235. {
  236. padapter->hal_func.SetHalODMVarHandler(padapter, eVariable, pValue1, bSet);
  237. }
  238. void rtw_hal_get_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1, PVOID pValue2)
  239. {
  240. padapter->hal_func.GetHalODMVarHandler(padapter, eVariable, pValue1, pValue2);
  241. }
  242. /* FOR SDIO & PCIE */
  243. void rtw_hal_enable_interrupt(_adapter *padapter)
  244. {
  245. #if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI)
  246. padapter->hal_func.enable_interrupt(padapter);
  247. #endif /* #if defined(CONFIG_PCI_HCI) || defined (CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) */
  248. }
  249. /* FOR SDIO & PCIE */
  250. void rtw_hal_disable_interrupt(_adapter *padapter)
  251. {
  252. #if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI)
  253. padapter->hal_func.disable_interrupt(padapter);
  254. #endif /* #if defined(CONFIG_PCI_HCI) || defined (CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) */
  255. }
  256. u8 rtw_hal_check_ips_status(_adapter *padapter)
  257. {
  258. u8 val = _FALSE;
  259. if (padapter->hal_func.check_ips_status)
  260. val = padapter->hal_func.check_ips_status(padapter);
  261. else
  262. RTW_INFO("%s: hal_func.check_ips_status is NULL!\n", __FUNCTION__);
  263. return val;
  264. }
  265. s32 rtw_hal_fw_dl(_adapter *padapter, u8 wowlan)
  266. {
  267. return padapter->hal_func.fw_dl(padapter, wowlan);
  268. }
  269. #ifdef RTW_HALMAC
  270. s32 rtw_hal_fw_mem_dl(_adapter *padapter, enum fw_mem mem)
  271. {
  272. u32 dlfw_start_time = rtw_get_current_time();
  273. struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
  274. struct debug_priv *pdbgpriv = &dvobj->drv_dbg;
  275. s32 rst = _FALSE;
  276. rst = padapter->hal_func.fw_mem_dl(padapter, mem);
  277. RTW_INFO("%s in %dms\n", __func__, rtw_get_passing_time_ms(dlfw_start_time));
  278. if (rst == _FALSE)
  279. pdbgpriv->dbg_fw_mem_dl_error_cnt++;
  280. if (1)
  281. RTW_INFO("%s dbg_fw_mem_dl_error_cnt:%d\n", __func__, pdbgpriv->dbg_fw_mem_dl_error_cnt);
  282. return rst;
  283. }
  284. #endif
  285. #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
  286. void rtw_hal_clear_interrupt(_adapter *padapter)
  287. {
  288. #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
  289. padapter->hal_func.clear_interrupt(padapter);
  290. #endif
  291. }
  292. #endif
  293. #if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
  294. u32 rtw_hal_inirp_init(_adapter *padapter)
  295. {
  296. if (is_primary_adapter(padapter))
  297. return padapter->hal_func.inirp_init(padapter);
  298. return _SUCCESS;
  299. }
  300. u32 rtw_hal_inirp_deinit(_adapter *padapter)
  301. {
  302. if (is_primary_adapter(padapter))
  303. return padapter->hal_func.inirp_deinit(padapter);
  304. return _SUCCESS;
  305. }
  306. #endif /* #if defined(CONFIG_USB_HCI) || defined (CONFIG_PCI_HCI) */
  307. #if defined(CONFIG_PCI_HCI)
  308. void rtw_hal_irp_reset(_adapter *padapter)
  309. {
  310. padapter->hal_func.irp_reset(GET_PRIMARY_ADAPTER(padapter));
  311. }
  312. void rtw_hal_pci_dbi_write(_adapter *padapter, u16 addr, u8 data)
  313. {
  314. u16 cmd[2];
  315. cmd[0] = addr;
  316. cmd[1] = data;
  317. padapter->hal_func.set_hw_reg_handler(padapter, HW_VAR_DBI, (u8 *) cmd);
  318. }
  319. u8 rtw_hal_pci_dbi_read(_adapter *padapter, u16 addr)
  320. {
  321. padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_DBI, (u8 *)(&addr));
  322. return (u8)addr;
  323. }
  324. void rtw_hal_pci_mdio_write(_adapter *padapter, u8 addr, u16 data)
  325. {
  326. u16 cmd[2];
  327. cmd[0] = (u16)addr;
  328. cmd[1] = data;
  329. padapter->hal_func.set_hw_reg_handler(padapter, HW_VAR_MDIO, (u8 *) cmd);
  330. }
  331. u16 rtw_hal_pci_mdio_read(_adapter *padapter, u8 addr)
  332. {
  333. padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_MDIO, &addr);
  334. return (u8)addr;
  335. }
  336. u8 rtw_hal_pci_l1off_nic_support(_adapter *padapter)
  337. {
  338. u8 l1off;
  339. padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_L1OFF_NIC_SUPPORT, &l1off);
  340. return l1off;
  341. }
  342. u8 rtw_hal_pci_l1off_capability(_adapter *padapter)
  343. {
  344. u8 l1off;
  345. padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_L1OFF_CAPABILITY, &l1off);
  346. return l1off;
  347. }
  348. #endif /* #if defined(CONFIG_PCI_HCI) */
  349. /* for USB Auto-suspend */
  350. u8 rtw_hal_intf_ps_func(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val)
  351. {
  352. if (padapter->hal_func.interface_ps_func)
  353. return padapter->hal_func.interface_ps_func(padapter, efunc_id, val);
  354. return _FAIL;
  355. }
  356. s32 rtw_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe)
  357. {
  358. return padapter->hal_func.hal_xmitframe_enqueue(padapter, pxmitframe);
  359. }
  360. s32 rtw_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe)
  361. {
  362. return padapter->hal_func.hal_xmit(padapter, pxmitframe);
  363. }
  364. /*
  365. * [IMPORTANT] This function would be run in interrupt context.
  366. */
  367. s32 rtw_hal_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe)
  368. {
  369. s32 ret = _FAIL;
  370. u8 *pframe, subtype;
  371. struct rtw_ieee80211_hdr *pwlanhdr;
  372. struct sta_info *psta;
  373. struct sta_priv *pstapriv = &padapter->stapriv;
  374. update_mgntframe_attrib_addr(padapter, pmgntframe);
  375. pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
  376. subtype = get_frame_sub_type(pframe); /* bit(7)~bit(2) */
  377. /* pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; */
  378. /* _rtw_memcpy(pmgntframe->attrib.ra, pwlanhdr->addr1, ETH_ALEN); */
  379. #ifdef CONFIG_IEEE80211W
  380. if (padapter->securitypriv.binstallBIPkey == _TRUE && (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC ||
  381. subtype == WIFI_ACTION)) {
  382. if (IS_MCAST(pmgntframe->attrib.ra) && pmgntframe->attrib.key_type != IEEE80211W_NO_KEY) {
  383. pmgntframe->attrib.encrypt = _BIP_;
  384. /* pmgntframe->attrib.bswenc = _TRUE; */
  385. } else if (pmgntframe->attrib.key_type != IEEE80211W_NO_KEY) {
  386. psta = rtw_get_stainfo(pstapriv, pmgntframe->attrib.ra);
  387. if (psta && psta->bpairwise_key_installed == _TRUE) {
  388. pmgntframe->attrib.encrypt = _AES_;
  389. pmgntframe->attrib.bswenc = _TRUE;
  390. } else {
  391. RTW_INFO("%s, %d, bpairwise_key_installed is FALSE\n", __func__, __LINE__);
  392. goto no_mgmt_coalesce;
  393. }
  394. }
  395. RTW_INFO("encrypt=%d, bswenc=%d\n", pmgntframe->attrib.encrypt, pmgntframe->attrib.bswenc);
  396. rtw_mgmt_xmitframe_coalesce(padapter, pmgntframe->pkt, pmgntframe);
  397. }
  398. #endif /* CONFIG_IEEE80211W */
  399. no_mgmt_coalesce:
  400. ret = padapter->hal_func.mgnt_xmit(padapter, pmgntframe);
  401. return ret;
  402. }
  403. s32 rtw_hal_init_xmit_priv(_adapter *padapter)
  404. {
  405. return padapter->hal_func.init_xmit_priv(padapter);
  406. }
  407. void rtw_hal_free_xmit_priv(_adapter *padapter)
  408. {
  409. padapter->hal_func.free_xmit_priv(padapter);
  410. }
  411. s32 rtw_hal_init_recv_priv(_adapter *padapter)
  412. {
  413. return padapter->hal_func.init_recv_priv(padapter);
  414. }
  415. void rtw_hal_free_recv_priv(_adapter *padapter)
  416. {
  417. padapter->hal_func.free_recv_priv(padapter);
  418. }
  419. void rtw_update_ramask(_adapter *padapter, struct sta_info *psta, u32 mac_id, u8 rssi_level, u8 is_update_bw)
  420. {
  421. struct macid_cfg h2c_macid_cfg;
  422. struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
  423. struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
  424. struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
  425. struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
  426. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
  427. u8 disable_cck_rate = FALSE, MimoPs_enable = FALSE;
  428. u32 ratr_bitmap_msb = 0, ratr_bitmap_lsb = 0;
  429. u64 mask = 0, rate_bitmap = 0;
  430. u8 bw, short_gi;
  431. if (psta == NULL) {
  432. RTW_ERR(FUNC_ADPT_FMT" macid:%u, sta is NULL\n", FUNC_ADPT_ARG(padapter), mac_id);
  433. rtw_warn_on(1);
  434. return;
  435. }
  436. _rtw_memset(&h2c_macid_cfg, 0, sizeof(struct macid_cfg));
  437. bw = rtw_get_tx_bw_mode(padapter, psta);
  438. short_gi = query_ra_short_GI(psta, bw);
  439. ratr_bitmap_msb = (u32)(psta->ra_mask >> 32);
  440. ratr_bitmap_lsb = (u32)(psta->ra_mask);
  441. phydm_update_hal_ra_mask(&hal_data->odmpriv, psta->wireless_mode, hal_data->rf_type, bw, MimoPs_enable, disable_cck_rate, &ratr_bitmap_msb, &ratr_bitmap_lsb, rssi_level);
  442. mask = (((u64)ratr_bitmap_msb) << 32) | ((u64)ratr_bitmap_lsb);
  443. #ifdef CONFIG_BT_COEXIST
  444. if (hal_data->EEPROMBluetoothCoexist == 1) {
  445. rate_bitmap = rtw_btcoex_GetRaMask(padapter);
  446. mask &= ~rate_bitmap;
  447. }
  448. #endif /* CONFIG_BT_COEXIST */
  449. #ifdef CONFIG_CMCC_TEST
  450. #ifdef CONFIG_BT_COEXIST
  451. if (pmlmeext->cur_wireless_mode & WIRELESS_11G) {
  452. if (mac_id == 0) {
  453. RTW_INFO("CMCC_BT update raid entry, mask=0x%x\n", mask);
  454. /*mask &=0xffffffc0; //disable CCK & <12M OFDM rate for 11G mode for CMCC */
  455. mask &= 0xffffff00; /*disable CCK & <24M OFDM rate for 11G mode for CMCC */
  456. RTW_INFO("CMCC_BT update raid entry, mask=0x%x\n", mask);
  457. }
  458. }
  459. #endif
  460. #endif
  461. /*set correct initial date rate for each mac_id */
  462. hal_data->INIDATA_RATE[mac_id] = psta->init_rate;
  463. RTW_INFO("%s => mac_id:%d, networkType:0x%02x, mask:0x%016llx\n\t ==> rssi_level:%d, rate_bitmap:0x%016llx, shortGIrate=%d\n\t ==> bw:%d, ignore_bw:0x%d\n",
  464. __func__, mac_id, psta->wireless_mode, mask, rssi_level, rate_bitmap, short_gi, bw, (!is_update_bw));
  465. rtw_macid_ctl_set_bw(macid_ctl, mac_id, bw);
  466. rtw_macid_ctl_set_vht_en(macid_ctl, mac_id, is_supported_vht(psta->wireless_mode));
  467. rtw_macid_ctl_set_rate_bmp0(macid_ctl, mac_id, mask);
  468. rtw_macid_ctl_set_rate_bmp1(macid_ctl, mac_id, mask >> 32);
  469. rtw_update_tx_rate_bmp(adapter_to_dvobj(padapter));
  470. h2c_macid_cfg.mac_id = mac_id;
  471. h2c_macid_cfg.rate_id = psta->raid;
  472. h2c_macid_cfg.bandwidth = bw;
  473. h2c_macid_cfg.ignore_bw = (!is_update_bw);
  474. h2c_macid_cfg.short_gi = short_gi;
  475. h2c_macid_cfg.ra_mask = mask;
  476. padapter->hal_func.update_ra_mask_handler(padapter, psta, &h2c_macid_cfg);
  477. }
  478. void rtw_hal_update_ra_mask(struct sta_info *psta, u8 rssi_level, u8 is_update_bw)
  479. {
  480. _adapter *padapter;
  481. struct mlme_priv *pmlmepriv;
  482. if (!psta)
  483. return;
  484. padapter = psta->padapter;
  485. pmlmepriv = &(padapter->mlmepriv);
  486. if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
  487. add_RATid(padapter, psta, rssi_level, is_update_bw);
  488. else {
  489. psta->raid = rtw_hal_networktype_to_raid(padapter, psta);
  490. rtw_update_ramask(padapter, psta, psta->mac_id, rssi_level, is_update_bw);
  491. }
  492. }
  493. /* Start specifical interface thread */
  494. void rtw_hal_start_thread(_adapter *padapter)
  495. {
  496. #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
  497. #ifndef CONFIG_SDIO_TX_TASKLET
  498. padapter->hal_func.run_thread(padapter);
  499. #endif
  500. #endif
  501. }
  502. /* Start specifical interface thread */
  503. void rtw_hal_stop_thread(_adapter *padapter)
  504. {
  505. #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
  506. #ifndef CONFIG_SDIO_TX_TASKLET
  507. padapter->hal_func.cancel_thread(padapter);
  508. #endif
  509. #endif
  510. }
  511. u32 rtw_hal_read_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask)
  512. {
  513. u32 data = 0;
  514. if (padapter->hal_func.read_bbreg)
  515. data = padapter->hal_func.read_bbreg(padapter, RegAddr, BitMask);
  516. return data;
  517. }
  518. void rtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data)
  519. {
  520. if (padapter->hal_func.write_bbreg)
  521. padapter->hal_func.write_bbreg(padapter, RegAddr, BitMask, Data);
  522. }
  523. u32 rtw_hal_read_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask)
  524. {
  525. u32 data = 0;
  526. if (padapter->hal_func.read_rfreg) {
  527. data = padapter->hal_func.read_rfreg(padapter, eRFPath, RegAddr, BitMask);
  528. if (match_rf_read_sniff_ranges(eRFPath, RegAddr, BitMask)) {
  529. RTW_INFO("DBG_IO rtw_hal_read_rfreg(%u, 0x%04x, 0x%08x) read:0x%08x(0x%08x)\n"
  530. , eRFPath, RegAddr, BitMask, (data << PHY_CalculateBitShift(BitMask)), data);
  531. }
  532. }
  533. return data;
  534. }
  535. void rtw_hal_write_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
  536. {
  537. if (padapter->hal_func.write_rfreg) {
  538. if (match_rf_write_sniff_ranges(eRFPath, RegAddr, BitMask)) {
  539. RTW_INFO("DBG_IO rtw_hal_write_rfreg(%u, 0x%04x, 0x%08x) write:0x%08x(0x%08x)\n"
  540. , eRFPath, RegAddr, BitMask, (Data << PHY_CalculateBitShift(BitMask)), Data);
  541. }
  542. padapter->hal_func.write_rfreg(padapter, eRFPath, RegAddr, BitMask, Data);
  543. #ifdef CONFIG_PCI_HCI
  544. if (!IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(padapter)) /*For N-Series IC, suggest by Jenyu*/
  545. rtw_udelay_os(2);
  546. #endif
  547. }
  548. }
  549. #if defined(CONFIG_PCI_HCI)
  550. s32 rtw_hal_interrupt_handler(_adapter *padapter)
  551. {
  552. s32 ret = _FAIL;
  553. ret = padapter->hal_func.interrupt_handler(padapter);
  554. return ret;
  555. }
  556. #endif
  557. #if defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT)
  558. void rtw_hal_interrupt_handler(_adapter *padapter, u16 pkt_len, u8 *pbuf)
  559. {
  560. padapter->hal_func.interrupt_handler(padapter, pkt_len, pbuf);
  561. }
  562. #endif
  563. void rtw_hal_set_chnl_bw(_adapter *padapter, u8 channel, CHANNEL_WIDTH Bandwidth, u8 Offset40, u8 Offset80)
  564. {
  565. PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
  566. struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv);
  567. u8 cch_160 = Bandwidth == CHANNEL_WIDTH_160 ? channel : 0;
  568. u8 cch_80 = Bandwidth == CHANNEL_WIDTH_80 ? channel : 0;
  569. u8 cch_40 = Bandwidth == CHANNEL_WIDTH_40 ? channel : 0;
  570. u8 cch_20 = Bandwidth == CHANNEL_WIDTH_20 ? channel : 0;
  571. odm_acquire_spin_lock(pDM_Odm, RT_IQK_SPINLOCK);
  572. if (pDM_Odm->rf_calibrate_info.is_iqk_in_progress == _TRUE)
  573. RTW_ERR("%s, %d, IQK may race condition\n", __func__, __LINE__);
  574. odm_release_spin_lock(pDM_Odm, RT_IQK_SPINLOCK);
  575. /* MP mode channel don't use secondary channel */
  576. if (rtw_mi_mp_mode_check(padapter) == _FALSE) {
  577. #if 0
  578. if (cch_160 != 0)
  579. cch_80 = rtw_get_scch_by_cch_offset(cch_160, CHANNEL_WIDTH_160, Offset80);
  580. #endif
  581. if (cch_80 != 0)
  582. cch_40 = rtw_get_scch_by_cch_offset(cch_80, CHANNEL_WIDTH_80, Offset80);
  583. if (cch_40 != 0)
  584. cch_20 = rtw_get_scch_by_cch_offset(cch_40, CHANNEL_WIDTH_40, Offset40);
  585. }
  586. pHalData->cch_80 = cch_80;
  587. pHalData->cch_40 = cch_40;
  588. pHalData->cch_20 = cch_20;
  589. if (0)
  590. RTW_INFO("%s cch:%u, %s, offset40:%u, offset80:%u (%u, %u, %u)\n", __func__
  591. , channel, ch_width_str(Bandwidth), Offset40, Offset80
  592. , pHalData->cch_80, pHalData->cch_40, pHalData->cch_20);
  593. padapter->hal_func.set_chnl_bw_handler(padapter, channel, Bandwidth, Offset40, Offset80);
  594. }
  595. void rtw_hal_set_tx_power_level(_adapter *padapter, u8 channel)
  596. {
  597. if (padapter->hal_func.set_tx_power_level_handler)
  598. padapter->hal_func.set_tx_power_level_handler(padapter, channel);
  599. }
  600. void rtw_hal_get_tx_power_level(_adapter *padapter, s32 *powerlevel)
  601. {
  602. if (padapter->hal_func.get_tx_power_level_handler)
  603. padapter->hal_func.get_tx_power_level_handler(padapter, powerlevel);
  604. }
  605. void rtw_hal_dm_watchdog(_adapter *padapter)
  606. {
  607. #ifdef CONFIG_MCC_MODE
  608. if (MCC_EN(padapter)) {
  609. if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
  610. return;
  611. }
  612. #endif /* CONFIG_MCC_MODE */
  613. rtw_hal_turbo_edca(padapter);
  614. padapter->hal_func.hal_dm_watchdog(padapter);
  615. }
  616. #ifdef CONFIG_LPS_LCLK_WD_TIMER
  617. void rtw_hal_dm_watchdog_in_lps(_adapter *padapter)
  618. {
  619. #if defined(CONFIG_CONCURRENT_MODE)
  620. #ifndef CONFIG_FW_MULTI_PORT_SUPPORT
  621. if (padapter->hw_port != HW_PORT0)
  622. return;
  623. #endif
  624. #endif
  625. if (adapter_to_pwrctl(padapter)->bFwCurrentInPSMode == _TRUE) {
  626. padapter->hal_func.hal_dm_watchdog_in_lps(padapter);/* this function caller is in interrupt context */
  627. }
  628. }
  629. #endif
  630. void rtw_hal_bcn_related_reg_setting(_adapter *padapter)
  631. {
  632. padapter->hal_func.SetBeaconRelatedRegistersHandler(padapter);
  633. }
  634. #ifdef CONFIG_HOSTAPD_MLME
  635. s32 rtw_hal_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt)
  636. {
  637. if (padapter->hal_func.hostap_mgnt_xmit_entry)
  638. return padapter->hal_func.hostap_mgnt_xmit_entry(padapter, pkt);
  639. return _FAIL;
  640. }
  641. #endif /* CONFIG_HOSTAPD_MLME */
  642. #ifdef DBG_CONFIG_ERROR_DETECT
  643. void rtw_hal_sreset_init(_adapter *padapter)
  644. {
  645. padapter->hal_func.sreset_init_value(padapter);
  646. }
  647. void rtw_hal_sreset_reset(_adapter *padapter)
  648. {
  649. padapter = GET_PRIMARY_ADAPTER(padapter);
  650. padapter->hal_func.silentreset(padapter);
  651. }
  652. void rtw_hal_sreset_reset_value(_adapter *padapter)
  653. {
  654. padapter->hal_func.sreset_reset_value(padapter);
  655. }
  656. void rtw_hal_sreset_xmit_status_check(_adapter *padapter)
  657. {
  658. padapter->hal_func.sreset_xmit_status_check(padapter);
  659. }
  660. void rtw_hal_sreset_linked_status_check(_adapter *padapter)
  661. {
  662. padapter->hal_func.sreset_linked_status_check(padapter);
  663. }
  664. u8 rtw_hal_sreset_get_wifi_status(_adapter *padapter)
  665. {
  666. return padapter->hal_func.sreset_get_wifi_status(padapter);
  667. }
  668. bool rtw_hal_sreset_inprogress(_adapter *padapter)
  669. {
  670. padapter = GET_PRIMARY_ADAPTER(padapter);
  671. return padapter->hal_func.sreset_inprogress(padapter);
  672. }
  673. #endif /* DBG_CONFIG_ERROR_DETECT */
  674. #ifdef CONFIG_IOL
  675. int rtw_hal_iol_cmd(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_waiting_ms, u32 bndy_cnt)
  676. {
  677. if (adapter->hal_func.IOL_exec_cmds_sync)
  678. return adapter->hal_func.IOL_exec_cmds_sync(adapter, xmit_frame, max_waiting_ms, bndy_cnt);
  679. return _FAIL;
  680. }
  681. #endif
  682. #ifdef CONFIG_XMIT_THREAD_MODE
  683. s32 rtw_hal_xmit_thread_handler(_adapter *padapter)
  684. {
  685. return padapter->hal_func.xmit_thread_handler(padapter);
  686. }
  687. #endif
  688. #ifdef CONFIG_RECV_THREAD_MODE
  689. s32 rtw_hal_recv_hdl(_adapter *adapter)
  690. {
  691. return adapter->hal_func.recv_hdl(adapter);
  692. }
  693. #endif
  694. void rtw_hal_notch_filter(_adapter *adapter, bool enable)
  695. {
  696. if (adapter->hal_func.hal_notch_filter)
  697. adapter->hal_func.hal_notch_filter(adapter, enable);
  698. }
  699. #ifdef CONFIG_FW_C2H_REG
  700. inline bool rtw_hal_c2h_valid(_adapter *adapter, u8 *buf)
  701. {
  702. HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
  703. HAL_VERSION *hal_ver = &HalData->version_id;
  704. bool ret = _FAIL;
  705. ret = C2H_ID_88XX(buf) || C2H_PLEN_88XX(buf);
  706. return ret;
  707. }
  708. inline s32 rtw_hal_c2h_evt_read(_adapter *adapter, u8 *buf)
  709. {
  710. HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
  711. HAL_VERSION *hal_ver = &HalData->version_id;
  712. s32 ret = _FAIL;
  713. ret = c2h_evt_read_88xx(adapter, buf);
  714. return ret;
  715. }
  716. bool rtw_hal_c2h_reg_hdr_parse(_adapter *adapter, u8 *buf, u8 *id, u8 *seq, u8 *plen, u8 **payload)
  717. {
  718. HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
  719. HAL_VERSION *hal_ver = &HalData->version_id;
  720. bool ret = _FAIL;
  721. *id = C2H_ID_88XX(buf);
  722. *seq = C2H_SEQ_88XX(buf);
  723. *plen = C2H_PLEN_88XX(buf);
  724. *payload = C2H_PAYLOAD_88XX(buf);
  725. ret = _SUCCESS;
  726. return ret;
  727. }
  728. #endif /* CONFIG_FW_C2H_REG */
  729. #ifdef CONFIG_FW_C2H_PKT
  730. bool rtw_hal_c2h_pkt_hdr_parse(_adapter *adapter, u8 *buf, u16 len, u8 *id, u8 *seq, u8 *plen, u8 **payload)
  731. {
  732. HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
  733. HAL_VERSION *hal_ver = &HalData->version_id;
  734. bool ret = _FAIL;
  735. if (!buf || len > 256 || len < 3)
  736. goto exit;
  737. *id = C2H_ID_88XX(buf);
  738. *seq = C2H_SEQ_88XX(buf);
  739. *plen = len - 2;
  740. *payload = C2H_PAYLOAD_88XX(buf);
  741. ret = _SUCCESS;
  742. exit:
  743. return ret;
  744. }
  745. #endif /* CONFIG_FW_C2H_PKT */
  746. #if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTL8723B)
  747. #include <rtw_bt_mp.h> /* for MPTBT_FwC2hBtMpCtrl */
  748. #endif
  749. s32 c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload)
  750. {
  751. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
  752. struct PHY_DM_STRUCT *odm = &hal_data->odmpriv;
  753. u8 sub_id = 0;
  754. s32 ret = _SUCCESS;
  755. switch (id) {
  756. case C2H_FW_SCAN_COMPLETE:
  757. RTW_INFO("[C2H], FW Scan Complete\n");
  758. break;
  759. #ifdef CONFIG_BT_COEXIST
  760. case C2H_BT_INFO:
  761. rtw_btcoex_BtInfoNotify(adapter, plen, payload);
  762. break;
  763. case C2H_BT_MP_INFO:
  764. #if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTL8723B)
  765. MPTBT_FwC2hBtMpCtrl(adapter, payload, plen);
  766. #endif
  767. rtw_btcoex_BtMpRptNotify(adapter, plen, payload);
  768. break;
  769. case C2H_MAILBOX_STATUS:
  770. RTW_INFO_DUMP("C2H_MAILBOX_STATUS: ", payload, plen);
  771. break;
  772. #endif /* CONFIG_BT_COEXIST */
  773. case C2H_IQK_FINISH:
  774. c2h_iqk_offload(adapter, payload, plen);
  775. break;
  776. #if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
  777. case C2H_FW_CHNL_SWITCH_COMPLETE:
  778. rtw_tdls_chsw_oper_done(adapter);
  779. break;
  780. case C2H_BCN_EARLY_RPT:
  781. rtw_tdls_ch_sw_back_to_base_chnl(adapter);
  782. break;
  783. #endif
  784. #ifdef CONFIG_MCC_MODE
  785. case C2H_MCC:
  786. rtw_hal_mcc_c2h_handler(adapter, plen, payload);
  787. break;
  788. #endif
  789. #ifdef CONFIG_RTW_MAC_HIDDEN_RPT
  790. case C2H_MAC_HIDDEN_RPT:
  791. c2h_mac_hidden_rpt_hdl(adapter, payload, plen);
  792. break;
  793. case C2H_MAC_HIDDEN_RPT_2:
  794. c2h_mac_hidden_rpt_2_hdl(adapter, payload, plen);
  795. break;
  796. #endif
  797. case C2H_DEFEATURE_DBG:
  798. c2h_defeature_dbg_hdl(adapter, payload, plen);
  799. break;
  800. #ifdef CONFIG_RTW_CUSTOMER_STR
  801. case C2H_CUSTOMER_STR_RPT:
  802. c2h_customer_str_rpt_hdl(adapter, payload, plen);
  803. break;
  804. case C2H_CUSTOMER_STR_RPT_2:
  805. c2h_customer_str_rpt_2_hdl(adapter, payload, plen);
  806. break;
  807. #endif
  808. case C2H_EXTEND:
  809. sub_id = payload[0];
  810. /* no handle, goto default */
  811. default:
  812. if (phydm_c2H_content_parsing(odm, id, plen, payload) != TRUE)
  813. ret = _FAIL;
  814. break;
  815. }
  816. exit:
  817. if (ret != _SUCCESS) {
  818. if (id == C2H_EXTEND)
  819. RTW_WARN("%s: unknown C2H(0x%02x, 0x%02x)\n", __func__, id, sub_id);
  820. else
  821. RTW_WARN("%s: unknown C2H(0x%02x)\n", __func__, id);
  822. }
  823. return ret;
  824. }
  825. #ifndef RTW_HALMAC
  826. s32 rtw_hal_c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload)
  827. {
  828. s32 ret = _FAIL;
  829. ret = adapter->hal_func.c2h_handler(adapter, id, seq, plen, payload);
  830. if (ret != _SUCCESS)
  831. ret = c2h_handler(adapter, id, seq, plen, payload);
  832. return ret;
  833. }
  834. s32 rtw_hal_c2h_id_handle_directly(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload)
  835. {
  836. switch (id) {
  837. case C2H_CCX_TX_RPT:
  838. case C2H_BT_MP_INFO:
  839. case C2H_FW_CHNL_SWITCH_COMPLETE:
  840. case C2H_IQK_FINISH:
  841. case C2H_MCC:
  842. case C2H_BCN_EARLY_RPT:
  843. case C2H_AP_REQ_TXRPT:
  844. case C2H_SPC_STAT:
  845. return _TRUE;
  846. default:
  847. return _FALSE;
  848. }
  849. }
  850. #endif /* !RTW_HALMAC */
  851. s32 rtw_hal_is_disable_sw_channel_plan(PADAPTER padapter)
  852. {
  853. return GET_HAL_DATA(padapter)->bDisableSWChannelPlan;
  854. }
  855. s32 rtw_hal_macid_sleep(PADAPTER padapter, u8 macid)
  856. {
  857. struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
  858. struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
  859. u8 support;
  860. support = _FALSE;
  861. rtw_hal_get_def_var(padapter, HAL_DEF_MACID_SLEEP, &support);
  862. if (_FALSE == support)
  863. return _FAIL;
  864. if (macid >= macid_ctl->num) {
  865. RTW_ERR(FUNC_ADPT_FMT": Invalid macid(%u)\n",
  866. FUNC_ADPT_ARG(padapter), macid);
  867. return _FAIL;
  868. }
  869. rtw_hal_set_hwreg(padapter, HW_VAR_MACID_SLEEP, &macid);
  870. return _SUCCESS;
  871. }
  872. s32 rtw_hal_macid_wakeup(PADAPTER padapter, u8 macid)
  873. {
  874. struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
  875. struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
  876. u8 support;
  877. support = _FALSE;
  878. rtw_hal_get_def_var(padapter, HAL_DEF_MACID_SLEEP, &support);
  879. if (_FALSE == support)
  880. return _FAIL;
  881. if (macid >= macid_ctl->num) {
  882. RTW_ERR(FUNC_ADPT_FMT": Invalid macid(%u)\n",
  883. FUNC_ADPT_ARG(padapter), macid);
  884. return _FAIL;
  885. }
  886. rtw_hal_set_hwreg(padapter, HW_VAR_MACID_WAKEUP, &macid);
  887. return _SUCCESS;
  888. }
  889. s32 rtw_hal_fill_h2c_cmd(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer)
  890. {
  891. _adapter *pri_adapter = GET_PRIMARY_ADAPTER(padapter);
  892. if (pri_adapter->bFWReady == _TRUE)
  893. return padapter->hal_func.fill_h2c_cmd(padapter, ElementID, CmdLen, pCmdBuffer);
  894. else if (padapter->registrypriv.mp_mode == 0)
  895. RTW_PRINT(FUNC_ADPT_FMT" FW doesn't exit when no MP mode, by pass H2C id:0x%02x\n"
  896. , FUNC_ADPT_ARG(padapter), ElementID);
  897. return _FAIL;
  898. }
  899. void rtw_hal_fill_fake_txdesc(_adapter *padapter, u8 *pDesc, u32 BufferLen,
  900. u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame)
  901. {
  902. padapter->hal_func.fill_fake_txdesc(padapter, pDesc, BufferLen, IsPsPoll, IsBTQosNull, bDataFrame);
  903. }
  904. u8 rtw_hal_get_txbuff_rsvd_page_num(_adapter *adapter, bool wowlan)
  905. {
  906. return adapter->hal_func.hal_get_tx_buff_rsvd_page_num(adapter, wowlan);
  907. }
  908. #ifdef CONFIG_GPIO_API
  909. void rtw_hal_update_hisr_hsisr_ind(_adapter *padapter, u32 flag)
  910. {
  911. if (padapter->hal_func.update_hisr_hsisr_ind)
  912. padapter->hal_func.update_hisr_hsisr_ind(padapter, flag);
  913. }
  914. int rtw_hal_gpio_func_check(_adapter *padapter, u8 gpio_num)
  915. {
  916. int ret = _SUCCESS;
  917. if (padapter->hal_func.hal_gpio_func_check)
  918. ret = padapter->hal_func.hal_gpio_func_check(padapter, gpio_num);
  919. return ret;
  920. }
  921. void rtw_hal_gpio_multi_func_reset(_adapter *padapter, u8 gpio_num)
  922. {
  923. if (padapter->hal_func.hal_gpio_multi_func_reset)
  924. padapter->hal_func.hal_gpio_multi_func_reset(padapter, gpio_num);
  925. }
  926. #endif
  927. void rtw_hal_fw_correct_bcn(_adapter *padapter)
  928. {
  929. if (padapter->hal_func.fw_correct_bcn)
  930. padapter->hal_func.fw_correct_bcn(padapter);
  931. }
  932. void rtw_hal_set_tx_power_index(PADAPTER padapter, u32 powerindex, u8 rfpath, u8 rate)
  933. {
  934. return padapter->hal_func.set_tx_power_index_handler(padapter, powerindex, rfpath, rate);
  935. }
  936. u8 rtw_hal_get_tx_power_index(PADAPTER padapter, u8 rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic)
  937. {
  938. return padapter->hal_func.get_tx_power_index_handler(padapter, rfpath, rate, bandwidth, channel, tic);
  939. }
  940. #ifdef RTW_HALMAC
  941. /*
  942. * Description:
  943. * Initialize MAC registers
  944. *
  945. * Return:
  946. * _TRUE success
  947. * _FALSE fail
  948. */
  949. u8 rtw_hal_init_mac_register(PADAPTER adapter)
  950. {
  951. return adapter->hal_func.init_mac_register(adapter);
  952. }
  953. /*
  954. * Description:
  955. * Initialize PHY(BB/RF) related functions
  956. *
  957. * Return:
  958. * _TRUE success
  959. * _FALSE fail
  960. */
  961. u8 rtw_hal_init_phy(PADAPTER adapter)
  962. {
  963. return adapter->hal_func.init_phy(adapter);
  964. }
  965. #endif /* RTW_HALMAC */
  966. #define rtw_hal_error_msg(ops_fun) \
  967. RTW_PRINT("### %s - Error : Please hook hal_func.%s ###\n", __FUNCTION__, ops_fun)
  968. u8 rtw_hal_ops_check(_adapter *padapter)
  969. {
  970. u8 ret = _SUCCESS;
  971. #if 1
  972. /*** initialize section ***/
  973. if (NULL == padapter->hal_func.read_chip_version) {
  974. rtw_hal_error_msg("read_chip_version");
  975. ret = _FAIL;
  976. }
  977. if (NULL == padapter->hal_func.init_default_value) {
  978. rtw_hal_error_msg("init_default_value");
  979. ret = _FAIL;
  980. }
  981. if (NULL == padapter->hal_func.intf_chip_configure) {
  982. rtw_hal_error_msg("intf_chip_configure");
  983. ret = _FAIL;
  984. }
  985. if (NULL == padapter->hal_func.read_adapter_info) {
  986. rtw_hal_error_msg("read_adapter_info");
  987. ret = _FAIL;
  988. }
  989. if (NULL == padapter->hal_func.hal_power_on) {
  990. rtw_hal_error_msg("hal_power_on");
  991. ret = _FAIL;
  992. }
  993. if (NULL == padapter->hal_func.hal_power_off) {
  994. rtw_hal_error_msg("hal_power_off");
  995. ret = _FAIL;
  996. }
  997. if (NULL == padapter->hal_func.hal_init) {
  998. rtw_hal_error_msg("hal_init");
  999. ret = _FAIL;
  1000. }
  1001. if (NULL == padapter->hal_func.hal_deinit) {
  1002. rtw_hal_error_msg("hal_deinit");
  1003. ret = _FAIL;
  1004. }
  1005. /*** xmit section ***/
  1006. if (NULL == padapter->hal_func.init_xmit_priv) {
  1007. rtw_hal_error_msg("init_xmit_priv");
  1008. ret = _FAIL;
  1009. }
  1010. if (NULL == padapter->hal_func.free_xmit_priv) {
  1011. rtw_hal_error_msg("free_xmit_priv");
  1012. ret = _FAIL;
  1013. }
  1014. if (NULL == padapter->hal_func.hal_xmit) {
  1015. rtw_hal_error_msg("hal_xmit");
  1016. ret = _FAIL;
  1017. }
  1018. if (NULL == padapter->hal_func.mgnt_xmit) {
  1019. rtw_hal_error_msg("mgnt_xmit");
  1020. ret = _FAIL;
  1021. }
  1022. #ifdef CONFIG_XMIT_THREAD_MODE
  1023. if (NULL == padapter->hal_func.xmit_thread_handler) {
  1024. rtw_hal_error_msg("xmit_thread_handler");
  1025. ret = _FAIL;
  1026. }
  1027. #endif
  1028. if (NULL == padapter->hal_func.hal_xmitframe_enqueue) {
  1029. rtw_hal_error_msg("hal_xmitframe_enqueue");
  1030. ret = _FAIL;
  1031. }
  1032. #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
  1033. #ifndef CONFIG_SDIO_TX_TASKLET
  1034. if (NULL == padapter->hal_func.run_thread) {
  1035. rtw_hal_error_msg("run_thread");
  1036. ret = _FAIL;
  1037. }
  1038. if (NULL == padapter->hal_func.cancel_thread) {
  1039. rtw_hal_error_msg("cancel_thread");
  1040. ret = _FAIL;
  1041. }
  1042. #endif
  1043. #endif
  1044. /*** recv section ***/
  1045. if (NULL == padapter->hal_func.init_recv_priv) {
  1046. rtw_hal_error_msg("init_recv_priv");
  1047. ret = _FAIL;
  1048. }
  1049. if (NULL == padapter->hal_func.free_recv_priv) {
  1050. rtw_hal_error_msg("free_recv_priv");
  1051. ret = _FAIL;
  1052. }
  1053. #ifdef CONFIG_RECV_THREAD_MODE
  1054. if (NULL == padapter->hal_func.recv_hdl) {
  1055. rtw_hal_error_msg("recv_hdl");
  1056. ret = _FAIL;
  1057. }
  1058. #endif
  1059. #if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
  1060. if (NULL == padapter->hal_func.inirp_init) {
  1061. rtw_hal_error_msg("inirp_init");
  1062. ret = _FAIL;
  1063. }
  1064. if (NULL == padapter->hal_func.inirp_deinit) {
  1065. rtw_hal_error_msg("inirp_deinit");
  1066. ret = _FAIL;
  1067. }
  1068. #endif /* #if defined(CONFIG_USB_HCI) || defined (CONFIG_PCI_HCI) */
  1069. /*** interrupt hdl section ***/
  1070. #if defined(CONFIG_PCI_HCI)
  1071. if (NULL == padapter->hal_func.irp_reset) {
  1072. rtw_hal_error_msg("irp_reset");
  1073. ret = _FAIL;
  1074. }
  1075. #endif/*#if defined(CONFIG_PCI_HCI)*/
  1076. #if (defined(CONFIG_PCI_HCI)) || (defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT))
  1077. if (NULL == padapter->hal_func.interrupt_handler) {
  1078. rtw_hal_error_msg("interrupt_handler");
  1079. ret = _FAIL;
  1080. }
  1081. #endif /*#if (defined(CONFIG_PCI_HCI)) || (defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT))*/
  1082. #if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI)
  1083. if (NULL == padapter->hal_func.enable_interrupt) {
  1084. rtw_hal_error_msg("enable_interrupt");
  1085. ret = _FAIL;
  1086. }
  1087. if (NULL == padapter->hal_func.disable_interrupt) {
  1088. rtw_hal_error_msg("disable_interrupt");
  1089. ret = _FAIL;
  1090. }
  1091. #endif /* defined(CONFIG_PCI_HCI) || defined (CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) */
  1092. /*** DM section ***/
  1093. if (NULL == padapter->hal_func.dm_init) {
  1094. rtw_hal_error_msg("dm_init");
  1095. ret = _FAIL;
  1096. }
  1097. if (NULL == padapter->hal_func.dm_deinit) {
  1098. rtw_hal_error_msg("dm_deinit");
  1099. ret = _FAIL;
  1100. }
  1101. if (NULL == padapter->hal_func.hal_dm_watchdog) {
  1102. rtw_hal_error_msg("hal_dm_watchdog");
  1103. ret = _FAIL;
  1104. }
  1105. #ifdef CONFIG_LPS_LCLK_WD_TIMER
  1106. if (NULL == padapter->hal_func.hal_dm_watchdog_in_lps) {
  1107. rtw_hal_error_msg("hal_dm_watchdog_in_lps");
  1108. ret = _FAIL;
  1109. }
  1110. #endif
  1111. /*** xxx section ***/
  1112. if (NULL == padapter->hal_func.set_chnl_bw_handler) {
  1113. rtw_hal_error_msg("set_chnl_bw_handler");
  1114. ret = _FAIL;
  1115. }
  1116. if (NULL == padapter->hal_func.set_hw_reg_handler) {
  1117. rtw_hal_error_msg("set_hw_reg_handler");
  1118. ret = _FAIL;
  1119. }
  1120. if (NULL == padapter->hal_func.GetHwRegHandler) {
  1121. rtw_hal_error_msg("GetHwRegHandler");
  1122. ret = _FAIL;
  1123. }
  1124. if (NULL == padapter->hal_func.get_hal_def_var_handler) {
  1125. rtw_hal_error_msg("get_hal_def_var_handler");
  1126. ret = _FAIL;
  1127. }
  1128. if (NULL == padapter->hal_func.SetHalDefVarHandler) {
  1129. rtw_hal_error_msg("SetHalDefVarHandler");
  1130. ret = _FAIL;
  1131. }
  1132. if (NULL == padapter->hal_func.GetHalODMVarHandler) {
  1133. rtw_hal_error_msg("GetHalODMVarHandler");
  1134. ret = _FAIL;
  1135. }
  1136. if (NULL == padapter->hal_func.SetHalODMVarHandler) {
  1137. rtw_hal_error_msg("SetHalODMVarHandler");
  1138. ret = _FAIL;
  1139. }
  1140. if (NULL == padapter->hal_func.update_ra_mask_handler) {
  1141. rtw_hal_error_msg("update_ra_mask_handler");
  1142. ret = _FAIL;
  1143. }
  1144. if (NULL == padapter->hal_func.SetBeaconRelatedRegistersHandler) {
  1145. rtw_hal_error_msg("SetBeaconRelatedRegistersHandler");
  1146. ret = _FAIL;
  1147. }
  1148. if (NULL == padapter->hal_func.fill_h2c_cmd) {
  1149. rtw_hal_error_msg("fill_h2c_cmd");
  1150. ret = _FAIL;
  1151. }
  1152. #ifdef RTW_HALMAC
  1153. if (NULL == padapter->hal_func.hal_mac_c2h_handler) {
  1154. rtw_hal_error_msg("hal_mac_c2h_handler");
  1155. ret = _FAIL;
  1156. }
  1157. #elif !defined(CONFIG_RTL8188E)
  1158. if (NULL == padapter->hal_func.c2h_handler) {
  1159. rtw_hal_error_msg("c2h_handler");
  1160. ret = _FAIL;
  1161. }
  1162. #endif
  1163. #if defined(CONFIG_LPS) || defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
  1164. if (NULL == padapter->hal_func.fill_fake_txdesc) {
  1165. rtw_hal_error_msg("fill_fake_txdesc");
  1166. ret = _FAIL;
  1167. }
  1168. #endif
  1169. if (NULL == padapter->hal_func.hal_get_tx_buff_rsvd_page_num) {
  1170. rtw_hal_error_msg("hal_get_tx_buff_rsvd_page_num");
  1171. ret = _FAIL;
  1172. }
  1173. #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
  1174. #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
  1175. if (NULL == padapter->hal_func.clear_interrupt) {
  1176. rtw_hal_error_msg("clear_interrupt");
  1177. ret = _FAIL;
  1178. }
  1179. #endif
  1180. #endif /* CONFIG_WOWLAN */
  1181. if (NULL == padapter->hal_func.fw_dl) {
  1182. rtw_hal_error_msg("fw_dl");
  1183. ret = _FAIL;
  1184. }
  1185. #if defined(RTW_HALMAC) && defined(CONFIG_LPS_PG)
  1186. if (NULL == padapter->hal_func.fw_mem_dl) {
  1187. rtw_hal_error_msg("fw_mem_dl");
  1188. ret = _FAIL;
  1189. }
  1190. #endif
  1191. if ((IS_HARDWARE_TYPE_8814A(padapter)
  1192. || IS_HARDWARE_TYPE_8822BU(padapter) || IS_HARDWARE_TYPE_8822BS(padapter))
  1193. && NULL == padapter->hal_func.fw_correct_bcn) {
  1194. rtw_hal_error_msg("fw_correct_bcn");
  1195. ret = _FAIL;
  1196. }
  1197. if (IS_HARDWARE_TYPE_8822B(padapter) || IS_HARDWARE_TYPE_8821C(padapter)) {
  1198. if (!padapter->hal_func.set_tx_power_index_handler) {
  1199. rtw_hal_error_msg("set_tx_power_index_handler");
  1200. ret = _FAIL;
  1201. }
  1202. }
  1203. if (!padapter->hal_func.get_tx_power_index_handler) {
  1204. rtw_hal_error_msg("get_tx_power_index_handler");
  1205. ret = _FAIL;
  1206. }
  1207. /*** SReset section ***/
  1208. #ifdef DBG_CONFIG_ERROR_DETECT
  1209. if (NULL == padapter->hal_func.sreset_init_value) {
  1210. rtw_hal_error_msg("sreset_init_value");
  1211. ret = _FAIL;
  1212. }
  1213. if (NULL == padapter->hal_func.sreset_reset_value) {
  1214. rtw_hal_error_msg("sreset_reset_value");
  1215. ret = _FAIL;
  1216. }
  1217. if (NULL == padapter->hal_func.silentreset) {
  1218. rtw_hal_error_msg("silentreset");
  1219. ret = _FAIL;
  1220. }
  1221. if (NULL == padapter->hal_func.sreset_xmit_status_check) {
  1222. rtw_hal_error_msg("sreset_xmit_status_check");
  1223. ret = _FAIL;
  1224. }
  1225. if (NULL == padapter->hal_func.sreset_linked_status_check) {
  1226. rtw_hal_error_msg("sreset_linked_status_check");
  1227. ret = _FAIL;
  1228. }
  1229. if (NULL == padapter->hal_func.sreset_get_wifi_status) {
  1230. rtw_hal_error_msg("sreset_get_wifi_status");
  1231. ret = _FAIL;
  1232. }
  1233. if (NULL == padapter->hal_func.sreset_inprogress) {
  1234. rtw_hal_error_msg("sreset_inprogress");
  1235. ret = _FAIL;
  1236. }
  1237. #endif /* #ifdef DBG_CONFIG_ERROR_DETECT */
  1238. #ifdef RTW_HALMAC
  1239. if (NULL == padapter->hal_func.init_mac_register) {
  1240. rtw_hal_error_msg("init_mac_register");
  1241. ret = _FAIL;
  1242. }
  1243. if (NULL == padapter->hal_func.init_phy) {
  1244. rtw_hal_error_msg("init_phy");
  1245. ret = _FAIL;
  1246. }
  1247. #endif /* RTW_HALMAC */
  1248. #endif
  1249. return ret;
  1250. }