phydm_antdect.c 37 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. *
  19. ******************************************************************************/
  20. /* ************************************************************
  21. * include files
  22. * ************************************************************ */
  23. #include "mp_precomp.h"
  24. #include "phydm_precomp.h"
  25. /* #if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE)) */
  26. #if (defined(CONFIG_ANT_DETECTION))
  27. /* IS_ANT_DETECT_SUPPORT_SINGLE_TONE(adapter)
  28. * IS_ANT_DETECT_SUPPORT_RSSI(adapter)
  29. * IS_ANT_DETECT_SUPPORT_PSD(adapter) */
  30. /* 1 [1. Single Tone method] =================================================== */
  31. /*
  32. * Description:
  33. * Set Single/Dual Antenna default setting for products that do not do detection in advance.
  34. *
  35. * Added by Joseph, 2012.03.22
  36. * */
  37. void
  38. odm_single_dual_antenna_default_setting(
  39. void *p_dm_void
  40. )
  41. {
  42. struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
  43. struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table;
  44. struct _ADAPTER *p_adapter = p_dm_odm->adapter;
  45. u8 bt_ant_num = BT_GetPgAntNum(p_adapter);
  46. /* Set default antenna A and B status */
  47. if (bt_ant_num == 2) {
  48. p_dm_swat_table->ANTA_ON = true;
  49. p_dm_swat_table->ANTB_ON = true;
  50. } else if (bt_ant_num == 1) {
  51. /* Set antenna A as default */
  52. p_dm_swat_table->ANTA_ON = true;
  53. p_dm_swat_table->ANTB_ON = false;
  54. } else
  55. RT_ASSERT(false, ("Incorrect antenna number!!\n"));
  56. }
  57. /* 2 8723A ANT DETECT
  58. *
  59. * Description:
  60. * Implement IQK single tone for RF DPK loopback and BB PSD scanning.
  61. * This function is cooperated with BB team Neil.
  62. *
  63. * Added by Roger, 2011.12.15
  64. * */
  65. boolean
  66. odm_single_dual_antenna_detection(
  67. void *p_dm_void,
  68. u8 mode
  69. )
  70. {
  71. struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
  72. struct _ADAPTER *p_adapter = p_dm_odm->adapter;
  73. struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table;
  74. u32 current_channel, rf_loop_reg;
  75. u8 n;
  76. u32 reg88c, regc08, reg874, regc50, reg948, regb2c, reg92c, reg930, reg064, afe_rrx_wait_cca;
  77. u8 initial_gain = 0x5a;
  78. u32 PSD_report_tmp;
  79. u32 ant_a_report = 0x0, ant_b_report = 0x0, ant_0_report = 0x0;
  80. boolean is_result = true;
  81. u32 afe_backup[16];
  82. u32 AFE_REG_8723A[16] = {
  83. REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
  84. REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
  85. REG_TX_OFDM_BBON, REG_TX_TO_RX,
  86. REG_TX_TO_TX, REG_RX_CCK,
  87. REG_RX_OFDM, REG_RX_WAIT_RIFS,
  88. REG_RX_TO_RX, REG_STANDBY,
  89. REG_SLEEP, REG_PMPD_ANAEN,
  90. REG_FPGA0_XCD_SWITCH_CONTROL, REG_BLUE_TOOTH
  91. };
  92. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_single_dual_antenna_detection()============>\n"));
  93. if (!(p_dm_odm->support_ic_type & ODM_RTL8723B))
  94. return is_result;
  95. /* Retrieve antenna detection registry info, added by Roger, 2012.11.27. */
  96. if (!IS_ANT_DETECT_SUPPORT_SINGLE_TONE(p_adapter))
  97. return is_result;
  98. /* 1 Backup Current RF/BB Settings */
  99. current_channel = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK);
  100. rf_loop_reg = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x00, RFREGOFFSETMASK);
  101. if (p_dm_odm->support_ic_type & ODM_RTL8723B) {
  102. reg92c = odm_get_bb_reg(p_dm_odm, REG_DPDT_CONTROL, MASKDWORD);
  103. reg930 = odm_get_bb_reg(p_dm_odm, rfe_ctrl_anta_src, MASKDWORD);
  104. reg948 = odm_get_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, MASKDWORD);
  105. regb2c = odm_get_bb_reg(p_dm_odm, REG_AGC_TABLE_SELECT, MASKDWORD);
  106. reg064 = odm_get_mac_reg(p_dm_odm, REG_SYM_WLBT_PAPE_SEL, BIT(29));
  107. odm_set_bb_reg(p_dm_odm, REG_DPDT_CONTROL, 0x3, 0x1);
  108. odm_set_bb_reg(p_dm_odm, rfe_ctrl_anta_src, 0xff, 0x77);
  109. odm_set_mac_reg(p_dm_odm, REG_SYM_WLBT_PAPE_SEL, BIT(29), 0x1); /* dbg 7 */
  110. odm_set_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, 0x3c0, 0x0);/* dbg 8 */
  111. odm_set_bb_reg(p_dm_odm, REG_AGC_TABLE_SELECT, BIT(31), 0x0);
  112. }
  113. odm_stall_execution(10);
  114. /* Store A path Register 88c, c08, 874, c50 */
  115. reg88c = odm_get_bb_reg(p_dm_odm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD);
  116. regc08 = odm_get_bb_reg(p_dm_odm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD);
  117. reg874 = odm_get_bb_reg(p_dm_odm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD);
  118. regc50 = odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD);
  119. /* Store AFE Registers */
  120. if (p_dm_odm->support_ic_type & ODM_RTL8723B)
  121. afe_rrx_wait_cca = odm_get_bb_reg(p_dm_odm, REG_RX_WAIT_CCA, MASKDWORD);
  122. /* Set PSD 128 pts */
  123. odm_set_bb_reg(p_dm_odm, REG_FPGA0_PSD_FUNCTION, BIT(14) | BIT15, 0x0); /* 128 pts */
  124. /* To SET CH1 to do */
  125. odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK, 0x7401); /* channel 1 */
  126. /* AFE all on step */
  127. if (p_dm_odm->support_ic_type & ODM_RTL8723B)
  128. odm_set_bb_reg(p_dm_odm, REG_RX_WAIT_CCA, MASKDWORD, 0x01c00016);
  129. /* 3 wire Disable */
  130. odm_set_bb_reg(p_dm_odm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD, 0xCCF000C0);
  131. /* BB IQK setting */
  132. odm_set_bb_reg(p_dm_odm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, 0x000800E4);
  133. odm_set_bb_reg(p_dm_odm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, 0x22208000);
  134. /* IQK setting tone@ 4.34Mhz */
  135. odm_set_bb_reg(p_dm_odm, REG_TX_IQK_TONE_A, MASKDWORD, 0x10008C1C);
  136. odm_set_bb_reg(p_dm_odm, REG_TX_IQK, MASKDWORD, 0x01007c00);
  137. /* Page B init */
  138. odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_A, MASKDWORD, 0x00080000);
  139. odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_A, MASKDWORD, 0x0f600000);
  140. odm_set_bb_reg(p_dm_odm, REG_RX_IQK, MASKDWORD, 0x01004800);
  141. odm_set_bb_reg(p_dm_odm, REG_RX_IQK_TONE_A, MASKDWORD, 0x10008c1f);
  142. if (p_dm_odm->support_ic_type & ODM_RTL8723B) {
  143. odm_set_bb_reg(p_dm_odm, REG_TX_IQK_PI_A, MASKDWORD, 0x82150016);
  144. odm_set_bb_reg(p_dm_odm, REG_RX_IQK_PI_A, MASKDWORD, 0x28150016);
  145. }
  146. odm_set_bb_reg(p_dm_odm, REG_IQK_AGC_RSP, MASKDWORD, 0x001028d0);
  147. odm_set_bb_reg(p_dm_odm, REG_OFDM_0_XA_AGC_CORE1, 0x7f, initial_gain);
  148. /* IQK Single tone start */
  149. odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x808000);
  150. odm_set_bb_reg(p_dm_odm, REG_IQK_AGC_PTS, MASKDWORD, 0xf9000000);
  151. odm_set_bb_reg(p_dm_odm, REG_IQK_AGC_PTS, MASKDWORD, 0xf8000000);
  152. odm_stall_execution(10000);
  153. /* PSD report of antenna A */
  154. PSD_report_tmp = 0x0;
  155. for (n = 0; n < 2; n++) {
  156. PSD_report_tmp = phydm_get_psd_data(p_dm_odm, 14, initial_gain);
  157. if (PSD_report_tmp > ant_a_report)
  158. ant_a_report = PSD_report_tmp;
  159. }
  160. /* change to Antenna B */
  161. if (p_dm_odm->support_ic_type & ODM_RTL8723B) {
  162. /* odm_set_bb_reg(p_dm_odm, REG_DPDT_CONTROL, 0x3, 0x2); */
  163. odm_set_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, 0xfff, 0x280);
  164. odm_set_bb_reg(p_dm_odm, REG_AGC_TABLE_SELECT, BIT(31), 0x1);
  165. }
  166. odm_stall_execution(10);
  167. /* PSD report of antenna B */
  168. PSD_report_tmp = 0x0;
  169. for (n = 0; n < 2; n++) {
  170. PSD_report_tmp = phydm_get_psd_data(p_dm_odm, 14, initial_gain);
  171. if (PSD_report_tmp > ant_b_report)
  172. ant_b_report = PSD_report_tmp;
  173. }
  174. /* Close IQK Single Tone function */
  175. odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
  176. /* 1 Return to antanna A */
  177. if (p_dm_odm->support_ic_type & ODM_RTL8723B) {
  178. /* external DPDT */
  179. odm_set_bb_reg(p_dm_odm, REG_DPDT_CONTROL, MASKDWORD, reg92c);
  180. /* internal S0/S1 */
  181. odm_set_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, MASKDWORD, reg948);
  182. odm_set_bb_reg(p_dm_odm, REG_AGC_TABLE_SELECT, MASKDWORD, regb2c);
  183. odm_set_bb_reg(p_dm_odm, rfe_ctrl_anta_src, MASKDWORD, reg930);
  184. odm_set_mac_reg(p_dm_odm, REG_SYM_WLBT_PAPE_SEL, BIT(29), reg064);
  185. }
  186. odm_set_bb_reg(p_dm_odm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD, reg88c);
  187. odm_set_bb_reg(p_dm_odm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, regc08);
  188. odm_set_bb_reg(p_dm_odm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, reg874);
  189. odm_set_bb_reg(p_dm_odm, REG_OFDM_0_XA_AGC_CORE1, 0x7F, 0x40);
  190. odm_set_bb_reg(p_dm_odm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD, regc50);
  191. odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, current_channel);
  192. odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x00, RFREGOFFSETMASK, rf_loop_reg);
  193. /* Reload AFE Registers */
  194. if (p_dm_odm->support_ic_type & ODM_RTL8723B)
  195. odm_set_bb_reg(p_dm_odm, REG_RX_WAIT_CCA, MASKDWORD, afe_rrx_wait_cca);
  196. if (p_dm_odm->support_ic_type & ODM_RTL8723B) {
  197. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_A[%d]= %d\n", 2416, ant_a_report));
  198. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_B[%d]= %d\n", 2416, ant_b_report));
  199. /* 2 Test ant B based on ant A is ON */
  200. if ((ant_a_report >= 100) && (ant_b_report >= 100) && (ant_a_report <= 135) && (ant_b_report <= 135)) {
  201. u8 TH1 = 2, TH2 = 6;
  202. if ((ant_a_report - ant_b_report < TH1) || (ant_b_report - ant_a_report < TH1)) {
  203. p_dm_swat_table->ANTA_ON = true;
  204. p_dm_swat_table->ANTB_ON = true;
  205. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_single_dual_antenna_detection(): Dual Antenna\n"));
  206. } else if (((ant_a_report - ant_b_report >= TH1) && (ant_a_report - ant_b_report <= TH2)) ||
  207. ((ant_b_report - ant_a_report >= TH1) && (ant_b_report - ant_a_report <= TH2))) {
  208. p_dm_swat_table->ANTA_ON = false;
  209. p_dm_swat_table->ANTB_ON = false;
  210. is_result = false;
  211. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_single_dual_antenna_detection(): Need to check again\n"));
  212. } else {
  213. p_dm_swat_table->ANTA_ON = true;
  214. p_dm_swat_table->ANTB_ON = false;
  215. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_single_dual_antenna_detection(): Single Antenna\n"));
  216. }
  217. p_dm_odm->ant_detected_info.is_ant_detected = true;
  218. p_dm_odm->ant_detected_info.db_for_ant_a = ant_a_report;
  219. p_dm_odm->ant_detected_info.db_for_ant_b = ant_b_report;
  220. p_dm_odm->ant_detected_info.db_for_ant_o = ant_0_report;
  221. } else {
  222. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("return false!!\n"));
  223. is_result = false;
  224. }
  225. }
  226. return is_result;
  227. }
  228. /* 1 [2. Scan AP RSSI method] ================================================== */
  229. boolean
  230. odm_sw_ant_div_check_before_link(
  231. void *p_dm_void
  232. )
  233. {
  234. #if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM)
  235. struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
  236. struct _ADAPTER *adapter = p_dm_odm->adapter;
  237. HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
  238. PMGNT_INFO p_mgnt_info = &adapter->MgntInfo;
  239. struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table;
  240. struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table;
  241. s8 score = 0;
  242. PRT_WLAN_BSS p_tmp_bss_desc, p_test_bss_desc;
  243. u8 power_target_L = 9, power_target_H = 16;
  244. u8 tmp_power_diff = 0, power_diff = 0, avg_power_diff = 0, max_power_diff = 0, min_power_diff = 0xff;
  245. u16 index, counter = 0;
  246. static u8 scan_channel;
  247. u32 tmp_swas_no_link_bk_reg948;
  248. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ANTA_ON = (( %d )) , ANTB_ON = (( %d ))\n", p_dm_odm->dm_swat_table.ANTA_ON, p_dm_odm->dm_swat_table.ANTB_ON));
  249. /* if(HP id) */
  250. {
  251. if (p_dm_odm->dm_swat_table.rssi_ant_dect_result == true && p_dm_odm->support_ic_type == ODM_RTL8723B) {
  252. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("8723B RSSI-based Antenna Detection is done\n"));
  253. return false;
  254. }
  255. if (p_dm_odm->support_ic_type == ODM_RTL8723B) {
  256. if (p_dm_swat_table->swas_no_link_bk_reg948 == 0xff)
  257. p_dm_swat_table->swas_no_link_bk_reg948 = odm_read_4byte(p_dm_odm, REG_S0_S1_PATH_SWITCH);
  258. }
  259. }
  260. if (p_dm_odm->adapter == NULL) { /* For BSOD when plug/unplug fast. //By YJ,120413 */
  261. /* The ODM structure is not initialized. */
  262. return false;
  263. }
  264. /* Retrieve antenna detection registry info, added by Roger, 2012.11.27. */
  265. if (!IS_ANT_DETECT_SUPPORT_RSSI(adapter))
  266. return false;
  267. else
  268. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Antenna Detection: RSSI method\n"));
  269. /* Since driver is going to set BB register, it shall check if there is another thread controlling BB/RF. */
  270. odm_acquire_spin_lock(p_dm_odm, RT_RF_STATE_SPINLOCK);
  271. if (p_hal_data->eRFPowerState != eRfOn || p_mgnt_info->RFChangeInProgress || p_mgnt_info->bMediaConnect) {
  272. odm_release_spin_lock(p_dm_odm, RT_RF_STATE_SPINLOCK);
  273. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
  274. ("odm_sw_ant_div_check_before_link(): rf_change_in_progress(%x), e_rf_power_state(%x)\n",
  275. p_mgnt_info->RFChangeInProgress, p_hal_data->eRFPowerState));
  276. p_dm_swat_table->swas_no_link_state = 0;
  277. return false;
  278. } else
  279. odm_release_spin_lock(p_dm_odm, RT_RF_STATE_SPINLOCK);
  280. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("p_dm_swat_table->swas_no_link_state = %d\n", p_dm_swat_table->swas_no_link_state));
  281. /* 1 Run AntDiv mechanism "Before Link" part. */
  282. if (p_dm_swat_table->swas_no_link_state == 0) {
  283. /* 1 Prepare to do Scan again to check current antenna state. */
  284. /* Set check state to next step. */
  285. p_dm_swat_table->swas_no_link_state = 1;
  286. /* Copy Current Scan list. */
  287. p_mgnt_info->tmpNumBssDesc = p_mgnt_info->NumBssDesc;
  288. PlatformMoveMemory((void *)adapter->MgntInfo.tmpbssDesc, (void *)p_mgnt_info->bssDesc, sizeof(RT_WLAN_BSS) * MAX_BSS_DESC);
  289. /* Go back to scan function again. */
  290. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link: Scan one more time\n"));
  291. p_mgnt_info->ScanStep = 0;
  292. p_mgnt_info->bScanAntDetect = true;
  293. scan_channel = odm_sw_ant_div_select_scan_chnl(adapter);
  294. if (p_dm_odm->support_ic_type & (ODM_RTL8188E | ODM_RTL8821)) {
  295. if (p_dm_fat_table->rx_idle_ant == MAIN_ANT)
  296. odm_update_rx_idle_ant(p_dm_odm, AUX_ANT);
  297. else
  298. odm_update_rx_idle_ant(p_dm_odm, MAIN_ANT);
  299. if (scan_channel == 0) {
  300. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
  301. ("odm_sw_ant_div_check_before_link(): No AP List Avaiable, Using ant(%s)\n", (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "AUX_ANT" : "MAIN_ANT"));
  302. if (IS_5G_WIRELESS_MODE(p_mgnt_info->dot11CurrentWirelessMode)) {
  303. p_dm_swat_table->ant_5g = p_dm_fat_table->rx_idle_ant;
  304. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("p_dm_swat_table->ant_5g=%s\n", (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"));
  305. } else {
  306. p_dm_swat_table->ant_2g = p_dm_fat_table->rx_idle_ant;
  307. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("p_dm_swat_table->ant_2g=%s\n", (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"));
  308. }
  309. return false;
  310. }
  311. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
  312. ("odm_sw_ant_div_check_before_link: Change to %s for testing.\n", ((p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")));
  313. } else if (p_dm_odm->support_ic_type & (ODM_RTL8723B)) {
  314. /*Switch Antenna to another one.*/
  315. tmp_swas_no_link_bk_reg948 = odm_read_4byte(p_dm_odm, REG_S0_S1_PATH_SWITCH);
  316. if ((p_dm_swat_table->cur_antenna == MAIN_ANT) && (tmp_swas_no_link_bk_reg948 == 0x200)) {
  317. odm_set_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, 0xfff, 0x280);
  318. odm_set_bb_reg(p_dm_odm, REG_AGC_TABLE_SELECT, BIT(31), 0x1);
  319. p_dm_swat_table->cur_antenna = AUX_ANT;
  320. } else {
  321. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Reg[948]= (( %x )) was in wrong state\n", tmp_swas_no_link_bk_reg948));
  322. return false;
  323. }
  324. odm_stall_execution(10);
  325. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link: Change to (( %s-ant)) for testing.\n", (p_dm_swat_table->cur_antenna == MAIN_ANT) ? "MAIN" : "AUX"));
  326. }
  327. odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel);
  328. PlatformSetTimer(adapter, &p_mgnt_info->ScanTimer, 5);
  329. return true;
  330. } else { /* p_dm_swat_table->swas_no_link_state == 1 */
  331. /* 1 ScanComple() is called after antenna swiched. */
  332. /* 1 Check scan result and determine which antenna is going */
  333. /* 1 to be used. */
  334. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" tmp_num_bss_desc= (( %d ))\n", p_mgnt_info->tmpNumBssDesc)); /* debug for Dino */
  335. for (index = 0; index < p_mgnt_info->tmpNumBssDesc; index++) {
  336. p_tmp_bss_desc = &(p_mgnt_info->tmpbssDesc[index]); /* Antenna 1 */
  337. p_test_bss_desc = &(p_mgnt_info->bssDesc[index]); /* Antenna 2 */
  338. if (PlatformCompareMemory(p_test_bss_desc->bdBssIdBuf, p_tmp_bss_desc->bdBssIdBuf, 6) != 0) {
  339. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link(): ERROR!! This shall not happen.\n"));
  340. continue;
  341. }
  342. if (p_dm_odm->support_ic_type != ODM_RTL8723B) {
  343. if (p_tmp_bss_desc->ChannelNumber == scan_channel) {
  344. if (p_tmp_bss_desc->RecvSignalPower > p_test_bss_desc->RecvSignalPower) {
  345. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link: Compare scan entry: score++\n"));
  346. RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen);
  347. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower));
  348. score++;
  349. PlatformMoveMemory(p_test_bss_desc, p_tmp_bss_desc, sizeof(RT_WLAN_BSS));
  350. } else if (p_tmp_bss_desc->RecvSignalPower < p_test_bss_desc->RecvSignalPower) {
  351. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link: Compare scan entry: score--\n"));
  352. RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen);
  353. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower));
  354. score--;
  355. } else {
  356. if (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp < 5000) {
  357. RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen);
  358. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower));
  359. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("The 2nd Antenna didn't get this AP\n\n"));
  360. }
  361. }
  362. }
  363. } else { /* 8723B */
  364. if (p_tmp_bss_desc->ChannelNumber == scan_channel) {
  365. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("channel_number == scan_channel->(( %d ))\n", p_tmp_bss_desc->ChannelNumber));
  366. if (p_tmp_bss_desc->RecvSignalPower > p_test_bss_desc->RecvSignalPower) { /* Pow(Ant1) > Pow(Ant2) */
  367. counter++;
  368. tmp_power_diff = (u8)(p_tmp_bss_desc->RecvSignalPower - p_test_bss_desc->RecvSignalPower);
  369. power_diff = power_diff + tmp_power_diff;
  370. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower));
  371. ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), p_tmp_bss_desc->bdSsIdBuf);
  372. ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), p_tmp_bss_desc->bdSsIdBuf);
  373. /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("tmp_power_diff: (( %d)),max_power_diff: (( %d)),min_power_diff: (( %d))\n", tmp_power_diff,max_power_diff,min_power_diff)); */
  374. if (tmp_power_diff > max_power_diff)
  375. max_power_diff = tmp_power_diff;
  376. if (tmp_power_diff < min_power_diff)
  377. min_power_diff = tmp_power_diff;
  378. /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("max_power_diff: (( %d)),min_power_diff: (( %d))\n",max_power_diff,min_power_diff)); */
  379. PlatformMoveMemory(p_test_bss_desc, p_tmp_bss_desc, sizeof(RT_WLAN_BSS));
  380. } else if (p_test_bss_desc->RecvSignalPower > p_tmp_bss_desc->RecvSignalPower) { /* Pow(Ant1) < Pow(Ant2) */
  381. counter++;
  382. tmp_power_diff = (u8)(p_test_bss_desc->RecvSignalPower - p_tmp_bss_desc->RecvSignalPower);
  383. power_diff = power_diff + tmp_power_diff;
  384. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower));
  385. ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), p_tmp_bss_desc->bdSsIdBuf);
  386. ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), p_tmp_bss_desc->bdSsIdBuf);
  387. if (tmp_power_diff > max_power_diff)
  388. max_power_diff = tmp_power_diff;
  389. if (tmp_power_diff < min_power_diff)
  390. min_power_diff = tmp_power_diff;
  391. } else { /* Pow(Ant1) = Pow(Ant2) */
  392. if (p_test_bss_desc->bdTstamp > p_tmp_bss_desc->bdTstamp) { /* Stamp(Ant1) < Stamp(Ant2) */
  393. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("time_diff: %lld\n", (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp) / 1000));
  394. if (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp > 5000) {
  395. counter++;
  396. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower));
  397. ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), p_tmp_bss_desc->bdSsIdBuf);
  398. ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), p_tmp_bss_desc->bdSsIdBuf);
  399. min_power_diff = 0;
  400. }
  401. } else
  402. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Error !!!]: Time_diff: %lld\n", (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp) / 1000));
  403. }
  404. }
  405. }
  406. }
  407. if (p_dm_odm->support_ic_type & (ODM_RTL8188E | ODM_RTL8821)) {
  408. if (p_mgnt_info->NumBssDesc != 0 && score < 0) {
  409. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
  410. ("odm_sw_ant_div_check_before_link(): Using ant(%s)\n", (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"));
  411. } else {
  412. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
  413. ("odm_sw_ant_div_check_before_link(): Remain ant(%s)\n", (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "AUX_ANT" : "MAIN_ANT"));
  414. if (p_dm_fat_table->rx_idle_ant == MAIN_ANT)
  415. odm_update_rx_idle_ant(p_dm_odm, AUX_ANT);
  416. else
  417. odm_update_rx_idle_ant(p_dm_odm, MAIN_ANT);
  418. }
  419. if (IS_5G_WIRELESS_MODE(p_mgnt_info->dot11CurrentWirelessMode)) {
  420. p_dm_swat_table->ant_5g = p_dm_fat_table->rx_idle_ant;
  421. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("p_dm_swat_table->ant_5g=%s\n", (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"));
  422. } else {
  423. p_dm_swat_table->ant_2g = p_dm_fat_table->rx_idle_ant;
  424. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("p_dm_swat_table->ant_2g=%s\n", (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"));
  425. }
  426. } else if (p_dm_odm->support_ic_type == ODM_RTL8723B) {
  427. if (counter == 0) {
  428. if (p_dm_odm->dm_swat_table.pre_aux_fail_detec == false) {
  429. p_dm_odm->dm_swat_table.pre_aux_fail_detec = true;
  430. p_dm_odm->dm_swat_table.rssi_ant_dect_result = false;
  431. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("counter=(( 0 )) , [[ Cannot find any AP with Aux-ant ]] -> Scan Target-channel again\n"));
  432. /* 3 [ Scan again ] */
  433. odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel);
  434. PlatformSetTimer(adapter, &p_mgnt_info->ScanTimer, 5);
  435. return true;
  436. } else { /* pre_aux_fail_detec == true */
  437. /* 2 [ Single Antenna ] */
  438. p_dm_odm->dm_swat_table.pre_aux_fail_detec = false;
  439. p_dm_odm->dm_swat_table.rssi_ant_dect_result = true;
  440. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("counter=(( 0 )) , [[ Still cannot find any AP ]]\n"));
  441. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link(): Single antenna\n"));
  442. }
  443. p_dm_odm->dm_swat_table.aux_fail_detec_counter++;
  444. } else {
  445. p_dm_odm->dm_swat_table.pre_aux_fail_detec = false;
  446. if (counter == 3) {
  447. avg_power_diff = ((power_diff - max_power_diff - min_power_diff) >> 1) + ((max_power_diff + min_power_diff) >> 2);
  448. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("counter: (( %d )) , power_diff: (( %d ))\n", counter, power_diff));
  449. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ counter==3 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d ))\n", avg_power_diff, max_power_diff, min_power_diff));
  450. } else if (counter >= 4) {
  451. avg_power_diff = (power_diff - max_power_diff - min_power_diff) / (counter - 2);
  452. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("counter: (( %d )) , power_diff: (( %d ))\n", counter, power_diff));
  453. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ counter>=4 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d ))\n", avg_power_diff, max_power_diff, min_power_diff));
  454. } else { /* counter==1,2 */
  455. avg_power_diff = power_diff / counter;
  456. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("avg_power_diff: (( %d )) , counter: (( %d )) , power_diff: (( %d ))\n", avg_power_diff, counter, power_diff));
  457. }
  458. /* 2 [ Retry ] */
  459. if ((avg_power_diff >= power_target_L) && (avg_power_diff <= power_target_H)) {
  460. p_dm_odm->dm_swat_table.retry_counter++;
  461. if (p_dm_odm->dm_swat_table.retry_counter <= 3) {
  462. p_dm_odm->dm_swat_table.rssi_ant_dect_result = false;
  463. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[[ Low confidence result ]] avg_power_diff= (( %d )) -> Scan Target-channel again ]]\n", avg_power_diff));
  464. /* 3 [ Scan again ] */
  465. odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel);
  466. PlatformSetTimer(adapter, &p_mgnt_info->ScanTimer, 5);
  467. return true;
  468. } else {
  469. p_dm_odm->dm_swat_table.rssi_ant_dect_result = true;
  470. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[[ Still Low confidence result ]] (( retry_counter > 3 ))\n"));
  471. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link(): Single antenna\n"));
  472. }
  473. }
  474. /* 2 [ Dual Antenna ] */
  475. else if ((p_mgnt_info->NumBssDesc != 0) && (avg_power_diff < power_target_L)) {
  476. p_dm_odm->dm_swat_table.rssi_ant_dect_result = true;
  477. if (p_dm_odm->dm_swat_table.ANTB_ON == false) {
  478. p_dm_odm->dm_swat_table.ANTA_ON = true;
  479. p_dm_odm->dm_swat_table.ANTB_ON = true;
  480. }
  481. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link(): Dual antenna\n"));
  482. p_dm_odm->dm_swat_table.dual_ant_counter++;
  483. /* set bt coexDM from 1ant coexDM to 2ant coexDM */
  484. BT_SetBtCoexAntNum(adapter, BT_COEX_ANT_TYPE_DETECTED, 2);
  485. /* 3 [ Init antenna diversity ] */
  486. p_dm_odm->support_ability |= ODM_BB_ANT_DIV;
  487. odm_ant_div_init(p_dm_odm);
  488. }
  489. /* 2 [ Single Antenna ] */
  490. else if (avg_power_diff > power_target_H) {
  491. p_dm_odm->dm_swat_table.rssi_ant_dect_result = true;
  492. if (p_dm_odm->dm_swat_table.ANTB_ON == true) {
  493. p_dm_odm->dm_swat_table.ANTA_ON = true;
  494. p_dm_odm->dm_swat_table.ANTB_ON = false;
  495. /* bt_set_bt_coex_ant_num(adapter, BT_COEX_ANT_TYPE_DETECTED, 1); */
  496. }
  497. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link(): Single antenna\n"));
  498. p_dm_odm->dm_swat_table.single_ant_counter++;
  499. }
  500. }
  501. /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("is_result=(( %d ))\n",p_dm_odm->dm_swat_table.rssi_ant_dect_result)); */
  502. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dual_ant_counter = (( %d )), single_ant_counter = (( %d )) , retry_counter = (( %d )) , aux_fail_detec_counter = (( %d ))\n\n\n",
  503. p_dm_odm->dm_swat_table.dual_ant_counter, p_dm_odm->dm_swat_table.single_ant_counter, p_dm_odm->dm_swat_table.retry_counter, p_dm_odm->dm_swat_table.aux_fail_detec_counter));
  504. /* 2 recover the antenna setting */
  505. if (p_dm_odm->dm_swat_table.ANTB_ON == false)
  506. odm_set_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, 0xfff, (p_dm_swat_table->swas_no_link_bk_reg948));
  507. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("is_result=(( %d )), Recover Reg[948]= (( %x )) \n\n", p_dm_odm->dm_swat_table.rssi_ant_dect_result, p_dm_swat_table->swas_no_link_bk_reg948));
  508. }
  509. /* Check state reset to default and wait for next time. */
  510. p_dm_swat_table->swas_no_link_state = 0;
  511. p_mgnt_info->bScanAntDetect = false;
  512. return false;
  513. }
  514. #else
  515. return false;
  516. #endif
  517. return false;
  518. }
  519. /* 1 [3. PSD method] ========================================================== */
  520. void
  521. odm_single_dual_antenna_detection_psd(
  522. void *p_dm_void
  523. )
  524. {
  525. struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
  526. u32 channel_ori;
  527. u8 initial_gain = 0x36;
  528. u8 tone_idx;
  529. u8 tone_lenth_1 = 7, tone_lenth_2 = 4;
  530. u16 tone_idx_1[7] = {88, 104, 120, 8, 24, 40, 56};
  531. u16 tone_idx_2[4] = {8, 24, 40, 56};
  532. u32 psd_report_main[11] = {0}, psd_report_aux[11] = {0};
  533. /* u8 tone_lenth_1=4, tone_lenth_2=2; */
  534. /* u16 tone_idx_1[4]={88, 120, 24, 56}; */
  535. /* u16 tone_idx_2[2]={ 24, 56}; */
  536. /* u32 psd_report_main[6]={0}, psd_report_aux[6]={0}; */
  537. u32 PSD_report_temp, max_psd_report_main = 0, max_psd_report_aux = 0;
  538. u32 PSD_power_threshold;
  539. u32 main_psd_result = 0, aux_psd_result = 0;
  540. u32 regc50, reg948, regb2c, regc14, reg908;
  541. u32 i = 0, test_num = 8;
  542. if (p_dm_odm->support_ic_type != ODM_RTL8723B)
  543. return;
  544. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_single_dual_antenna_detection_psd()============>\n"));
  545. /* 2 [ Backup Current RF/BB Settings ] */
  546. channel_ori = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK);
  547. reg948 = odm_get_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, MASKDWORD);
  548. regb2c = odm_get_bb_reg(p_dm_odm, REG_AGC_TABLE_SELECT, MASKDWORD);
  549. regc50 = odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD);
  550. regc14 = odm_get_bb_reg(p_dm_odm, 0xc14, MASKDWORD);
  551. reg908 = odm_get_bb_reg(p_dm_odm, 0x908, MASKDWORD);
  552. /* 2 [ setting for doing PSD function (CH4)] */
  553. odm_set_bb_reg(p_dm_odm, REG_FPGA0_RFMOD, BIT(24), 0); /* disable whole CCK block */
  554. odm_write_1byte(p_dm_odm, REG_TXPAUSE, 0xFF); /* Turn off TX -> Pause TX Queue */
  555. odm_set_bb_reg(p_dm_odm, 0xC14, MASKDWORD, 0x0); /* [ Set IQK Matrix = 0 ] equivalent to [ Turn off CCA] */
  556. /* PHYTXON while loop */
  557. odm_set_bb_reg(p_dm_odm, 0x908, MASKDWORD, 0x803);
  558. while (odm_get_bb_reg(p_dm_odm, 0xdf4, BIT(6))) {
  559. i++;
  560. if (i > 1000000) {
  561. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Wait in %s() more than %d times!\n", __FUNCTION__, i));
  562. break;
  563. }
  564. }
  565. odm_set_bb_reg(p_dm_odm, 0xc50, 0x7f, initial_gain);
  566. odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); /* Set RF to CH4 & 40M */
  567. odm_set_bb_reg(p_dm_odm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0xf); /* 3 wire Disable 88c[23:20]=0xf */
  568. odm_set_bb_reg(p_dm_odm, REG_FPGA0_PSD_FUNCTION, BIT(14) | BIT15, 0x0); /* 128 pt */ /* Set PSD 128 ptss */
  569. odm_stall_execution(3000);
  570. /* 2 [ Doing PSD Function in (CH4)] */
  571. /* Antenna A */
  572. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Main-ant (CH4)\n"));
  573. odm_set_bb_reg(p_dm_odm, 0x948, 0xfff, 0x200);
  574. odm_stall_execution(10);
  575. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dbg\n"));
  576. for (i = 0; i < test_num; i++) {
  577. for (tone_idx = 0; tone_idx < tone_lenth_1; tone_idx++) {
  578. PSD_report_temp = phydm_get_psd_data(p_dm_odm, tone_idx_1[tone_idx], initial_gain);
  579. /* if( PSD_report_temp>psd_report_main[tone_idx] ) */
  580. psd_report_main[tone_idx] += PSD_report_temp;
  581. }
  582. }
  583. /* Antenna B */
  584. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Aux-ant (CH4)\n"));
  585. odm_set_bb_reg(p_dm_odm, 0x948, 0xfff, 0x280);
  586. odm_stall_execution(10);
  587. for (i = 0; i < test_num; i++) {
  588. for (tone_idx = 0; tone_idx < tone_lenth_1; tone_idx++) {
  589. PSD_report_temp = phydm_get_psd_data(p_dm_odm, tone_idx_1[tone_idx], initial_gain);
  590. /* if( PSD_report_temp>psd_report_aux[tone_idx] ) */
  591. psd_report_aux[tone_idx] += PSD_report_temp;
  592. }
  593. }
  594. /* 2 [ Doing PSD Function in (CH8)] */
  595. odm_set_bb_reg(p_dm_odm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0x0); /* 3 wire enable 88c[23:20]=0x0 */
  596. odm_stall_execution(3000);
  597. odm_set_bb_reg(p_dm_odm, 0xc50, 0x7f, initial_gain);
  598. odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); /* Set RF to CH8 & 40M */
  599. odm_set_bb_reg(p_dm_odm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0xf); /* 3 wire Disable 88c[23:20]=0xf */
  600. odm_stall_execution(3000);
  601. /* Antenna A */
  602. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Main-ant (CH8)\n"));
  603. odm_set_bb_reg(p_dm_odm, 0x948, 0xfff, 0x200);
  604. odm_stall_execution(10);
  605. for (i = 0; i < test_num; i++) {
  606. for (tone_idx = 0; tone_idx < tone_lenth_2; tone_idx++) {
  607. PSD_report_temp = phydm_get_psd_data(p_dm_odm, tone_idx_2[tone_idx], initial_gain);
  608. /* if( PSD_report_temp>psd_report_main[tone_idx] ) */
  609. psd_report_main[tone_lenth_1 + tone_idx] += PSD_report_temp;
  610. }
  611. }
  612. /* Antenna B */
  613. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Aux-ant (CH8)\n"));
  614. odm_set_bb_reg(p_dm_odm, 0x948, 0xfff, 0x280);
  615. odm_stall_execution(10);
  616. for (i = 0; i < test_num; i++) {
  617. for (tone_idx = 0; tone_idx < tone_lenth_2; tone_idx++) {
  618. PSD_report_temp = phydm_get_psd_data(p_dm_odm, tone_idx_2[tone_idx], initial_gain);
  619. /* if( PSD_report_temp>psd_report_aux[tone_idx] ) */
  620. psd_report_aux[tone_lenth_1 + tone_idx] += PSD_report_temp;
  621. }
  622. }
  623. /* 2 [ Calculate Result ] */
  624. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\nMain PSD Result: (ALL)\n"));
  625. for (tone_idx = 0; tone_idx < (tone_lenth_1 + tone_lenth_2); tone_idx++) {
  626. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Tone-%d]: %d,\n", (tone_idx + 1), psd_report_main[tone_idx]));
  627. main_psd_result += psd_report_main[tone_idx];
  628. if (psd_report_main[tone_idx] > max_psd_report_main)
  629. max_psd_report_main = psd_report_main[tone_idx];
  630. }
  631. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("--------------------------- \nTotal_Main= (( %d ))\n", main_psd_result));
  632. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MAX_Main = (( %d ))\n", max_psd_report_main));
  633. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\nAux PSD Result: (ALL)\n"));
  634. for (tone_idx = 0; tone_idx < (tone_lenth_1 + tone_lenth_2); tone_idx++) {
  635. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Tone-%d]: %d,\n", (tone_idx + 1), psd_report_aux[tone_idx]));
  636. aux_psd_result += psd_report_aux[tone_idx];
  637. if (psd_report_aux[tone_idx] > max_psd_report_aux)
  638. max_psd_report_aux = psd_report_aux[tone_idx];
  639. }
  640. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("--------------------------- \nTotal_Aux= (( %d ))\n", aux_psd_result));
  641. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MAX_Aux = (( %d ))\n\n", max_psd_report_aux));
  642. /* main_psd_result=main_psd_result-max_psd_report_main; */
  643. /* aux_psd_result=aux_psd_result-max_psd_report_aux; */
  644. PSD_power_threshold = (main_psd_result * 7) >> 3;
  645. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Main_result, Aux_result ] = [ %d , %d ], PSD_power_threshold=(( %d ))\n", main_psd_result, aux_psd_result, PSD_power_threshold));
  646. /* 3 [ Dual Antenna ] */
  647. if (aux_psd_result >= PSD_power_threshold) {
  648. if (p_dm_odm->dm_swat_table.ANTB_ON == false) {
  649. p_dm_odm->dm_swat_table.ANTA_ON = true;
  650. p_dm_odm->dm_swat_table.ANTB_ON = true;
  651. }
  652. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link(): Dual antenna\n"));
  653. /* set bt coexDM from 1ant coexDM to 2ant coexDM */
  654. /* bt_set_bt_coex_ant_num(p_adapter, BT_COEX_ANT_TYPE_DETECTED, 2); */
  655. /* Init antenna diversity */
  656. p_dm_odm->support_ability |= ODM_BB_ANT_DIV;
  657. odm_ant_div_init(p_dm_odm);
  658. }
  659. /* 3 [ Single Antenna ] */
  660. else {
  661. if (p_dm_odm->dm_swat_table.ANTB_ON == true) {
  662. p_dm_odm->dm_swat_table.ANTA_ON = true;
  663. p_dm_odm->dm_swat_table.ANTB_ON = false;
  664. }
  665. ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link(): Single antenna\n"));
  666. }
  667. /* 2 [ Recover all parameters ] */
  668. odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, channel_ori);
  669. odm_set_bb_reg(p_dm_odm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0x0); /* 3 wire enable 88c[23:20]=0x0 */
  670. odm_set_bb_reg(p_dm_odm, 0xc50, 0x7f, regc50);
  671. odm_set_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, MASKDWORD, reg948);
  672. odm_set_bb_reg(p_dm_odm, REG_AGC_TABLE_SELECT, MASKDWORD, regb2c);
  673. odm_set_bb_reg(p_dm_odm, REG_FPGA0_RFMOD, BIT(24), 1); /* enable whole CCK block */
  674. odm_write_1byte(p_dm_odm, REG_TXPAUSE, 0x0); /* Turn on TX */ /* Resume TX Queue */
  675. odm_set_bb_reg(p_dm_odm, 0xC14, MASKDWORD, regc14); /* [ Set IQK Matrix = 0 ] equivalent to [ Turn on CCA] */
  676. odm_set_bb_reg(p_dm_odm, 0x908, MASKDWORD, reg908);
  677. return;
  678. }
  679. #endif
  680. void
  681. odm_sw_ant_detect_init(
  682. void *p_dm_void
  683. )
  684. {
  685. #if (defined(CONFIG_ANT_DETECTION))
  686. struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
  687. struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table;
  688. /* p_dm_swat_table->pre_antenna = MAIN_ANT; */
  689. /* p_dm_swat_table->cur_antenna = MAIN_ANT; */
  690. p_dm_swat_table->swas_no_link_state = 0;
  691. p_dm_swat_table->pre_aux_fail_detec = false;
  692. p_dm_swat_table->swas_no_link_bk_reg948 = 0xff;
  693. #if (CONFIG_PSD_TOOL == 1)
  694. phydm_psd_init(p_dm_odm);
  695. #endif
  696. #endif
  697. }