phydm_ccx.c 16 KB

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  1. #include "mp_precomp.h"
  2. #include "phydm_precomp.h"
  3. /*Set NHM period, threshold, disable ignore cca or not, disable ignore txon or not*/
  4. void
  5. phydm_nhm_setting(
  6. void *p_dm_void,
  7. u8 nhm_setting
  8. )
  9. {
  10. struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
  11. struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info;
  12. if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {
  13. if (nhm_setting == SET_NHM_SETTING) {
  14. /*Set inexclude_cca, inexclude_txon*/
  15. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9), ccx_info->nhm_inexclude_cca);
  16. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10), ccx_info->nhm_inexclude_txon);
  17. /*Set NHM period*/
  18. odm_set_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD, ccx_info->NHM_period);
  19. /*Set NHM threshold*/
  20. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE0, ccx_info->NHM_th[0]);
  21. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE1, ccx_info->NHM_th[1]);
  22. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE2, ccx_info->NHM_th[2]);
  23. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE3, ccx_info->NHM_th[3]);
  24. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE0, ccx_info->NHM_th[4]);
  25. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE1, ccx_info->NHM_th[5]);
  26. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE2, ccx_info->NHM_th[6]);
  27. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE3, ccx_info->NHM_th[7]);
  28. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11AC, MASKBYTE0, ccx_info->NHM_th[8]);
  29. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2, ccx_info->NHM_th[9]);
  30. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3, ccx_info->NHM_th[10]);
  31. /*CCX EN*/
  32. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(8), CCX_EN);
  33. } else if (nhm_setting == STORE_NHM_SETTING) {
  34. /*Store pervious disable_ignore_cca, disable_ignore_txon*/
  35. ccx_info->NHM_inexclude_cca_restore = (enum nhm_inexclude_cca)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9));
  36. ccx_info->NHM_inexclude_txon_restore = (enum nhm_inexclude_txon)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10));
  37. /*Store pervious NHM period*/
  38. ccx_info->NHM_period_restore = (u16)odm_get_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD);
  39. /*Store NHM threshold*/
  40. ccx_info->NHM_th_restore[0] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE0);
  41. ccx_info->NHM_th_restore[1] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE1);
  42. ccx_info->NHM_th_restore[2] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE2);
  43. ccx_info->NHM_th_restore[3] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE3);
  44. ccx_info->NHM_th_restore[4] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE0);
  45. ccx_info->NHM_th_restore[5] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE1);
  46. ccx_info->NHM_th_restore[6] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE2);
  47. ccx_info->NHM_th_restore[7] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE3);
  48. ccx_info->NHM_th_restore[8] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11AC, MASKBYTE0);
  49. ccx_info->NHM_th_restore[9] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2);
  50. ccx_info->NHM_th_restore[10] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3);
  51. } else if (nhm_setting == RESTORE_NHM_SETTING) {
  52. /*Set disable_ignore_cca, disable_ignore_txon*/
  53. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9), ccx_info->NHM_inexclude_cca_restore);
  54. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10), ccx_info->NHM_inexclude_txon_restore);
  55. /*Set NHM period*/
  56. odm_set_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD, ccx_info->NHM_period);
  57. /*Set NHM threshold*/
  58. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE0, ccx_info->NHM_th_restore[0]);
  59. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE1, ccx_info->NHM_th_restore[1]);
  60. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE2, ccx_info->NHM_th_restore[2]);
  61. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE3, ccx_info->NHM_th_restore[3]);
  62. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE0, ccx_info->NHM_th_restore[4]);
  63. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE1, ccx_info->NHM_th_restore[5]);
  64. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE2, ccx_info->NHM_th_restore[6]);
  65. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE3, ccx_info->NHM_th_restore[7]);
  66. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11AC, MASKBYTE0, ccx_info->NHM_th_restore[8]);
  67. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2, ccx_info->NHM_th_restore[9]);
  68. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3, ccx_info->NHM_th_restore[10]);
  69. } else
  70. return;
  71. }
  72. else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
  73. if (nhm_setting == SET_NHM_SETTING) {
  74. /*Set disable_ignore_cca, disable_ignore_txon*/
  75. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(9), ccx_info->nhm_inexclude_cca);
  76. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(10), ccx_info->nhm_inexclude_txon);
  77. /*Set NHM period*/
  78. odm_set_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11N, MASKHWORD, ccx_info->NHM_period);
  79. /*Set NHM threshold*/
  80. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE0, ccx_info->NHM_th[0]);
  81. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE1, ccx_info->NHM_th[1]);
  82. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE2, ccx_info->NHM_th[2]);
  83. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE3, ccx_info->NHM_th[3]);
  84. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE0, ccx_info->NHM_th[4]);
  85. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE1, ccx_info->NHM_th[5]);
  86. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE2, ccx_info->NHM_th[6]);
  87. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE3, ccx_info->NHM_th[7]);
  88. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11N, MASKBYTE0, ccx_info->NHM_th[8]);
  89. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2, ccx_info->NHM_th[9]);
  90. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3, ccx_info->NHM_th[10]);
  91. /*CCX EN*/
  92. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(8), CCX_EN);
  93. } else if (nhm_setting == STORE_NHM_SETTING) {
  94. /*Store pervious disable_ignore_cca, disable_ignore_txon*/
  95. ccx_info->NHM_inexclude_cca_restore = (enum nhm_inexclude_cca)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(9));
  96. ccx_info->NHM_inexclude_txon_restore = (enum nhm_inexclude_txon)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(10));
  97. /*Store pervious NHM period*/
  98. ccx_info->NHM_period_restore = (u16)odm_get_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11N, MASKHWORD);
  99. /*Store NHM threshold*/
  100. ccx_info->NHM_th_restore[0] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE0);
  101. ccx_info->NHM_th_restore[1] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE1);
  102. ccx_info->NHM_th_restore[2] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE2);
  103. ccx_info->NHM_th_restore[3] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE3);
  104. ccx_info->NHM_th_restore[4] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE0);
  105. ccx_info->NHM_th_restore[5] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE1);
  106. ccx_info->NHM_th_restore[6] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE2);
  107. ccx_info->NHM_th_restore[7] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE3);
  108. ccx_info->NHM_th_restore[8] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11N, MASKBYTE0);
  109. ccx_info->NHM_th_restore[9] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2);
  110. ccx_info->NHM_th_restore[10] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3);
  111. } else if (nhm_setting == RESTORE_NHM_SETTING) {
  112. /*Set disable_ignore_cca, disable_ignore_txon*/
  113. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(9), ccx_info->NHM_inexclude_cca_restore);
  114. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(10), ccx_info->NHM_inexclude_txon_restore);
  115. /*Set NHM period*/
  116. odm_set_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11N, MASKHWORD, ccx_info->NHM_period_restore);
  117. /*Set NHM threshold*/
  118. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE0, ccx_info->NHM_th_restore[0]);
  119. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE1, ccx_info->NHM_th_restore[1]);
  120. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE2, ccx_info->NHM_th_restore[2]);
  121. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE3, ccx_info->NHM_th_restore[3]);
  122. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE0, ccx_info->NHM_th_restore[4]);
  123. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE1, ccx_info->NHM_th_restore[5]);
  124. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE2, ccx_info->NHM_th_restore[6]);
  125. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE3, ccx_info->NHM_th_restore[7]);
  126. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11N, MASKBYTE0, ccx_info->NHM_th_restore[8]);
  127. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2, ccx_info->NHM_th_restore[9]);
  128. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3, ccx_info->NHM_th_restore[10]);
  129. } else
  130. return;
  131. }
  132. }
  133. void
  134. phydm_nhm_trigger(
  135. void *p_dm_void
  136. )
  137. {
  138. struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
  139. struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info;
  140. if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {
  141. /*Trigger NHM*/
  142. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 0);
  143. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 1);
  144. } else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
  145. /*Trigger NHM*/
  146. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 0);
  147. odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 1);
  148. }
  149. }
  150. void
  151. phydm_get_nhm_result(
  152. void *p_dm_void
  153. )
  154. {
  155. struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
  156. u32 value32;
  157. struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info;
  158. if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {
  159. value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT_11AC);
  160. ccx_info->NHM_result[0] = (u8)(value32 & MASKBYTE0);
  161. ccx_info->NHM_result[1] = (u8)((value32 & MASKBYTE1) >> 8);
  162. ccx_info->NHM_result[2] = (u8)((value32 & MASKBYTE2) >> 16);
  163. ccx_info->NHM_result[3] = (u8)((value32 & MASKBYTE3) >> 24);
  164. value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT7_TO_CNT4_11AC);
  165. ccx_info->NHM_result[4] = (u8)(value32 & MASKBYTE0);
  166. ccx_info->NHM_result[5] = (u8)((value32 & MASKBYTE1) >> 8);
  167. ccx_info->NHM_result[6] = (u8)((value32 & MASKBYTE2) >> 16);
  168. ccx_info->NHM_result[7] = (u8)((value32 & MASKBYTE3) >> 24);
  169. value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT11_TO_CNT8_11AC);
  170. ccx_info->NHM_result[8] = (u8)(value32 & MASKBYTE0);
  171. ccx_info->NHM_result[9] = (u8)((value32 & MASKBYTE1) >> 8);
  172. ccx_info->NHM_result[10] = (u8)((value32 & MASKBYTE2) >> 16);
  173. ccx_info->NHM_result[11] = (u8)((value32 & MASKBYTE3) >> 24);
  174. /*Get NHM duration*/
  175. value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_DUR_READY_11AC);
  176. ccx_info->NHM_duration = (u16)(value32 & MASKLWORD);
  177. }
  178. else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
  179. value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT_11N);
  180. ccx_info->NHM_result[0] = (u8)(value32 & MASKBYTE0);
  181. ccx_info->NHM_result[1] = (u8)((value32 & MASKBYTE1) >> 8);
  182. ccx_info->NHM_result[2] = (u8)((value32 & MASKBYTE2) >> 16);
  183. ccx_info->NHM_result[3] = (u8)((value32 & MASKBYTE3) >> 24);
  184. value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT7_TO_CNT4_11N);
  185. ccx_info->NHM_result[4] = (u8)(value32 & MASKBYTE0);
  186. ccx_info->NHM_result[5] = (u8)((value32 & MASKBYTE1) >> 8);
  187. ccx_info->NHM_result[6] = (u8)((value32 & MASKBYTE2) >> 16);
  188. ccx_info->NHM_result[7] = (u8)((value32 & MASKBYTE3) >> 24);
  189. value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT9_TO_CNT8_11N);
  190. ccx_info->NHM_result[8] = (u8)((value32 & MASKBYTE2) >> 16);
  191. ccx_info->NHM_result[9] = (u8)((value32 & MASKBYTE3) >> 24);
  192. value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT10_TO_CNT11_11N);
  193. ccx_info->NHM_result[10] = (u8)((value32 & MASKBYTE2) >> 16);
  194. ccx_info->NHM_result[11] = (u8)((value32 & MASKBYTE3) >> 24);
  195. /*Get NHM duration*/
  196. value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT10_TO_CNT11_11N);
  197. ccx_info->NHM_duration = (u16)(value32 & MASKLWORD);
  198. }
  199. }
  200. boolean
  201. phydm_check_nhm_ready(
  202. void *p_dm_void
  203. )
  204. {
  205. struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
  206. u32 value32 = 0;
  207. u8 i;
  208. boolean ret = false;
  209. if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {
  210. value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_CLM_RESULT_11AC, MASKDWORD);
  211. for (i = 0; i < 200; i++) {
  212. ODM_delay_ms(1);
  213. if (odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_DUR_READY_11AC, BIT(17))) {
  214. ret = 1;
  215. break;
  216. }
  217. }
  218. }
  219. else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
  220. value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_CLM_READY_11N, MASKDWORD);
  221. for (i = 0; i < 200; i++) {
  222. ODM_delay_ms(1);
  223. if (odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_DUR_READY_11AC, BIT(17))) {
  224. ret = 1;
  225. break;
  226. }
  227. }
  228. }
  229. return ret;
  230. }
  231. void
  232. phydm_store_nhm_setting(
  233. void *p_dm_void
  234. )
  235. {
  236. struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
  237. struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info;
  238. if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {
  239. } else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
  240. }
  241. }
  242. void
  243. phydm_clm_setting(
  244. void *p_dm_void
  245. )
  246. {
  247. struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
  248. struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info;
  249. if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {
  250. odm_set_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11AC, MASKLWORD, ccx_info->CLM_period); /*4us sample 1 time*/
  251. odm_set_bb_reg(p_dm_odm, ODM_REG_CLM_11AC, BIT(8), 0x1); /*Enable CCX for CLM*/
  252. } else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
  253. odm_set_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11N, MASKLWORD, ccx_info->CLM_period); /*4us sample 1 time*/
  254. odm_set_bb_reg(p_dm_odm, ODM_REG_CLM_11N, BIT(8), 0x1); /*Enable CCX for CLM*/
  255. }
  256. ODM_RT_TRACE(p_dm_odm, ODM_COMP_CCX, ODM_DBG_LOUD, ("[%s] : CLM period = %dus\n", __func__, ccx_info->CLM_period * 4));
  257. }
  258. void
  259. phydm_clm_trigger(
  260. void *p_dm_void
  261. )
  262. {
  263. struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
  264. if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {
  265. odm_set_bb_reg(p_dm_odm, ODM_REG_CLM_11AC, BIT(0), 0x0); /*Trigger CLM*/
  266. odm_set_bb_reg(p_dm_odm, ODM_REG_CLM_11AC, BIT(0), 0x1);
  267. } else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
  268. odm_set_bb_reg(p_dm_odm, ODM_REG_CLM_11N, BIT(0), 0x0); /*Trigger CLM*/
  269. odm_set_bb_reg(p_dm_odm, ODM_REG_CLM_11N, BIT(0), 0x1);
  270. }
  271. }
  272. boolean
  273. phydm_check_cl_mready(
  274. void *p_dm_void
  275. )
  276. {
  277. struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
  278. u32 value32 = 0;
  279. boolean ret = false;
  280. if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES)
  281. value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_CLM_RESULT_11AC, MASKDWORD); /*make sure CLM calc is ready*/
  282. else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES)
  283. value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_CLM_READY_11N, MASKDWORD); /*make sure CLM calc is ready*/
  284. if ((p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) && (value32 & BIT(16)))
  285. ret = true;
  286. else if ((p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) && (value32 & BIT(16)))
  287. ret = true;
  288. else
  289. ret = false;
  290. ODM_RT_TRACE(p_dm_odm, ODM_COMP_CCX, ODM_DBG_LOUD, ("[%s] : CLM ready = %d\n", __func__, ret));
  291. return ret;
  292. }
  293. void
  294. phydm_get_cl_mresult(
  295. void *p_dm_void
  296. )
  297. {
  298. struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
  299. struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info;
  300. u32 value32 = 0;
  301. u16 results = 0;
  302. if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES)
  303. value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_CLM_RESULT_11AC, MASKDWORD); /*read CLM calc result*/
  304. else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES)
  305. value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_CLM_RESULT_11N, MASKDWORD); /*read CLM calc result*/
  306. ccx_info->CLM_result = (u16)(value32 & MASKLWORD);
  307. ODM_RT_TRACE(p_dm_odm, ODM_COMP_CCX, ODM_DBG_LOUD, ("[%s] : CLM result = %dus\n", __func__, ccx_info->CLM_result * 4));
  308. }