rtw_pwrctrl.h 17 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2007 - 2017 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. *****************************************************************************/
  15. #ifndef __RTW_PWRCTRL_H_
  16. #define __RTW_PWRCTRL_H_
  17. #define FW_PWR0 0
  18. #define FW_PWR1 1
  19. #define FW_PWR2 2
  20. #define FW_PWR3 3
  21. #define HW_PWR0 7
  22. #define HW_PWR1 6
  23. #define HW_PWR2 2
  24. #define HW_PWR3 0
  25. #define HW_PWR4 8
  26. #define FW_PWRMSK 0x7
  27. #define XMIT_ALIVE BIT(0)
  28. #define RECV_ALIVE BIT(1)
  29. #define CMD_ALIVE BIT(2)
  30. #define EVT_ALIVE BIT(3)
  31. #ifdef CONFIG_BT_COEXIST
  32. #define BTCOEX_ALIVE BIT(4)
  33. #endif /* CONFIG_BT_COEXIST */
  34. #ifdef CONFIG_WOWLAN
  35. #ifdef CONFIG_PLATFORM_ANDROID_INTEL_X86
  36. /* TCP/ICMP/UDP multicast with specific IP addr */
  37. #define DEFAULT_PATTERN_NUM 4
  38. #else
  39. /* TCP/ICMP */
  40. #define DEFAULT_PATTERN_NUM 3
  41. #endif
  42. #ifdef CONFIG_WOW_PATTERN_HW_CAM /* Frame Mask Cam number for pattern match */
  43. #define MAX_WKFM_CAM_NUM 12
  44. #else
  45. #define MAX_WKFM_CAM_NUM 16
  46. #endif
  47. #define MAX_WKFM_SIZE 16 /* (16 bytes for WKFM bit mask, 16*8 = 128 bits) */
  48. #define MAX_WKFM_PATTERN_SIZE 128
  49. #define WKFMCAM_ADDR_NUM 6
  50. #define WKFMCAM_SIZE 24 /* each entry need 6*4 bytes */
  51. enum pattern_type {
  52. PATTERN_BROADCAST = 0,
  53. PATTERN_MULTICAST,
  54. PATTERN_UNICAST,
  55. PATTERN_VALID,
  56. PATTERN_INVALID,
  57. };
  58. typedef struct rtl_priv_pattern {
  59. int len;
  60. char content[MAX_WKFM_PATTERN_SIZE];
  61. char mask[MAX_WKFM_SIZE];
  62. } rtl_priv_pattern_t;
  63. #endif /* CONFIG_WOWLAN */
  64. enum Power_Mgnt {
  65. PS_MODE_ACTIVE = 0 ,
  66. PS_MODE_MIN ,
  67. PS_MODE_MAX ,
  68. PS_MODE_DTIM , /* PS_MODE_SELF_DEFINED */
  69. PS_MODE_VOIP ,
  70. PS_MODE_UAPSD_WMM ,
  71. PS_MODE_UAPSD ,
  72. PS_MODE_IBSS ,
  73. PS_MODE_WWLAN ,
  74. PM_Radio_Off ,
  75. PM_Card_Disable ,
  76. PS_MODE_NUM,
  77. };
  78. enum lps_level {
  79. LPS_NORMAL = 0,
  80. LPS_LCLK,
  81. LPS_PG,
  82. LPS_LEVEL_MAX,
  83. };
  84. #ifdef CONFIG_PNO_SUPPORT
  85. #define MAX_PNO_LIST_COUNT 16
  86. #define MAX_SCAN_LIST_COUNT 14 /* 2.4G only */
  87. #define MAX_HIDDEN_AP 8 /* 8 hidden AP */
  88. #endif
  89. /*
  90. BIT[2:0] = HW state
  91. BIT[3] = Protocol PS state, 0: register active state , 1: register sleep state
  92. BIT[4] = sub-state
  93. */
  94. #define PS_DPS BIT(0)
  95. #define PS_LCLK (PS_DPS)
  96. #define PS_RF_OFF BIT(1)
  97. #define PS_ALL_ON BIT(2)
  98. #define PS_ST_ACTIVE BIT(3)
  99. #define PS_ISR_ENABLE BIT(4)
  100. #define PS_IMR_ENABLE BIT(5)
  101. #define PS_ACK BIT(6)
  102. #define PS_TOGGLE BIT(7)
  103. #define PS_STATE_MASK (0x0F)
  104. #define PS_STATE_HW_MASK (0x07)
  105. #define PS_SEQ_MASK (0xc0)
  106. #define PS_STATE(x) (PS_STATE_MASK & (x))
  107. #define PS_STATE_HW(x) (PS_STATE_HW_MASK & (x))
  108. #define PS_SEQ(x) (PS_SEQ_MASK & (x))
  109. #define PS_STATE_S0 (PS_DPS)
  110. #define PS_STATE_S1 (PS_LCLK)
  111. #define PS_STATE_S2 (PS_RF_OFF)
  112. #define PS_STATE_S3 (PS_ALL_ON)
  113. #define PS_STATE_S4 ((PS_ST_ACTIVE) | (PS_ALL_ON))
  114. #define PS_IS_RF_ON(x) ((x) & (PS_ALL_ON))
  115. #define PS_IS_ACTIVE(x) ((x) & (PS_ST_ACTIVE))
  116. #define CLR_PS_STATE(x) ((x) = ((x) & (0xF0)))
  117. struct reportpwrstate_parm {
  118. unsigned char mode;
  119. unsigned char state; /* the CPWM value */
  120. unsigned short rsvd;
  121. };
  122. typedef _sema _pwrlock;
  123. __inline static void _init_pwrlock(_pwrlock *plock)
  124. {
  125. _rtw_init_sema(plock, 1);
  126. }
  127. __inline static void _free_pwrlock(_pwrlock *plock)
  128. {
  129. _rtw_free_sema(plock);
  130. }
  131. __inline static void _enter_pwrlock(_pwrlock *plock)
  132. {
  133. _rtw_down_sema(plock);
  134. }
  135. __inline static void _exit_pwrlock(_pwrlock *plock)
  136. {
  137. _rtw_up_sema(plock);
  138. }
  139. #define LPS_DELAY_MS 1000 /* 1 sec */
  140. #define EXE_PWR_NONE 0x01
  141. #define EXE_PWR_IPS 0x02
  142. #define EXE_PWR_LPS 0x04
  143. /* RF state. */
  144. typedef enum _rt_rf_power_state {
  145. rf_on, /* RF is on after RFSleep or RFOff */
  146. rf_sleep, /* 802.11 Power Save mode */
  147. rf_off, /* HW/SW Radio OFF or Inactive Power Save */
  148. /* =====Add the new RF state above this line===== */
  149. rf_max
  150. } rt_rf_power_state;
  151. /* RF Off Level for IPS or HW/SW radio off */
  152. #define RT_RF_OFF_LEVL_ASPM BIT(0) /* PCI ASPM */
  153. #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /* PCI clock request */
  154. #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /* PCI D3 mode */
  155. #define RT_RF_OFF_LEVL_HALT_NIC BIT(3) /* NIC halt, re-initialize hw parameters */
  156. #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /* FW free, re-download the FW */
  157. #define RT_RF_OFF_LEVL_FW_32K BIT(5) /* FW in 32k */
  158. #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6) /* Always enable ASPM and Clock Req in initialization. */
  159. #define RT_RF_LPS_DISALBE_2R BIT(30) /* When LPS is on, disable 2R if no packet is received or transmittd. */
  160. #define RT_RF_LPS_LEVEL_ASPM BIT(31) /* LPS with ASPM */
  161. #define RT_IN_PS_LEVEL(ppsc, _PS_FLAG) ((ppsc->cur_ps_level & _PS_FLAG) ? _TRUE : _FALSE)
  162. #define RT_CLEAR_PS_LEVEL(ppsc, _PS_FLAG) (ppsc->cur_ps_level &= (~(_PS_FLAG)))
  163. #define RT_SET_PS_LEVEL(ppsc, _PS_FLAG) (ppsc->cur_ps_level |= _PS_FLAG)
  164. /* ASPM OSC Control bit, added by Roger, 2013.03.29. */
  165. #define RT_PCI_ASPM_OSC_IGNORE 0 /* PCI ASPM ignore OSC control in default */
  166. #define RT_PCI_ASPM_OSC_ENABLE BIT0 /* PCI ASPM controlled by OS according to ACPI Spec 5.0 */
  167. #define RT_PCI_ASPM_OSC_DISABLE BIT1 /* PCI ASPM controlled by driver or BIOS, i.e., force enable ASPM */
  168. enum _PS_BBRegBackup_ {
  169. PSBBREG_RF0 = 0,
  170. PSBBREG_RF1,
  171. PSBBREG_RF2,
  172. PSBBREG_AFE0,
  173. PSBBREG_TOTALCNT
  174. };
  175. enum { /* for ips_mode */
  176. IPS_NONE = 0,
  177. IPS_NORMAL,
  178. IPS_LEVEL_2,
  179. IPS_NUM
  180. };
  181. /* Design for pwrctrl_priv.ips_deny, 32 bits for 32 reasons at most */
  182. typedef enum _PS_DENY_REASON {
  183. PS_DENY_DRV_INITIAL = 0,
  184. PS_DENY_SCAN,
  185. PS_DENY_JOIN,
  186. PS_DENY_DISCONNECT,
  187. PS_DENY_SUSPEND,
  188. PS_DENY_IOCTL,
  189. PS_DENY_MGNT_TX,
  190. PS_DENY_MONITOR_MODE,
  191. PS_DENY_BEAMFORMING, /* Beamforming */
  192. PS_DENY_DRV_REMOVE = 30,
  193. PS_DENY_OTHERS = 31
  194. } PS_DENY_REASON;
  195. #ifdef CONFIG_PNO_SUPPORT
  196. typedef struct pno_nlo_info {
  197. u32 fast_scan_period; /* Fast scan period */
  198. u8 ssid_num; /* number of entry */
  199. u8 hidden_ssid_num;
  200. u32 slow_scan_period; /* slow scan period */
  201. u32 fast_scan_iterations; /* Fast scan iterations */
  202. u8 ssid_length[MAX_PNO_LIST_COUNT]; /* SSID Length Array */
  203. u8 ssid_cipher_info[MAX_PNO_LIST_COUNT]; /* Cipher information for security */
  204. u8 ssid_channel_info[MAX_PNO_LIST_COUNT]; /* channel information */
  205. u8 loc_probe_req[MAX_HIDDEN_AP]; /* loc_probeReq */
  206. } pno_nlo_info_t;
  207. typedef struct pno_ssid {
  208. u32 SSID_len;
  209. u8 SSID[32];
  210. } pno_ssid_t;
  211. typedef struct pno_ssid_list {
  212. pno_ssid_t node[MAX_PNO_LIST_COUNT];
  213. } pno_ssid_list_t;
  214. typedef struct pno_scan_channel_info {
  215. u8 channel;
  216. u8 tx_power;
  217. u8 timeout;
  218. u8 active; /* set 1 means active scan, or pasivite scan. */
  219. } pno_scan_channel_info_t;
  220. typedef struct pno_scan_info {
  221. u8 enableRFE; /* Enable RFE */
  222. u8 period_scan_time; /* exclusive with fast_scan_period and slow_scan_period */
  223. u8 periodScan; /* exclusive with fast_scan_period and slow_scan_period */
  224. u8 orig_80_offset; /* original channel 80 offset */
  225. u8 orig_40_offset; /* original channel 40 offset */
  226. u8 orig_bw; /* original bandwidth */
  227. u8 orig_ch; /* original channel */
  228. u8 channel_num; /* number of channel */
  229. u64 rfe_type; /* rfe_type && 0x00000000000000ff */
  230. pno_scan_channel_info_t ssid_channel_info[MAX_SCAN_LIST_COUNT];
  231. } pno_scan_info_t;
  232. #endif /* CONFIG_PNO_SUPPORT */
  233. #ifdef CONFIG_LPS_POFF
  234. /* Driver context for LPS 32K Close IO Power */
  235. typedef struct lps_poff_info {
  236. bool bEn;
  237. u8 *pStaticFile;
  238. u8 *pDynamicFile;
  239. u32 ConfFileOffset;
  240. u32 tx_bndy_static;
  241. u32 tx_bndy_dynamic;
  242. u16 ConfLenForPTK;
  243. u16 ConfLenForGTK;
  244. ATOMIC_T bEnterPOFF;
  245. ATOMIC_T bTxBoundInProgress;
  246. ATOMIC_T bSetPOFFParm;
  247. } lps_poff_info_t;
  248. #endif /*CONFIG_LPS_POFF*/
  249. struct aoac_report {
  250. u8 iv[8];
  251. u8 replay_counter_eapol_key[8];
  252. u8 group_key[32];
  253. u8 key_index;
  254. u8 security_type;
  255. u8 wow_pattern_idx;
  256. u8 version_info;
  257. u8 rekey_ok:1;
  258. u8 dummy:7;
  259. u8 reserved[3];
  260. u8 rxptk_iv[8];
  261. u8 rxgtk_iv[4][8];
  262. };
  263. struct pwrctrl_priv {
  264. _pwrlock lock;
  265. _pwrlock check_32k_lock;
  266. volatile u8 rpwm; /* requested power state for fw */
  267. volatile u8 cpwm; /* fw current power state. updated when 1. read from HCPWM 2. driver lowers power level */
  268. volatile u8 tog; /* toggling */
  269. volatile u8 cpwm_tog; /* toggling */
  270. u8 rpwm_retry;
  271. u8 pwr_mode;
  272. u8 smart_ps;
  273. u8 bcn_ant_mode;
  274. u8 dtim;
  275. #ifdef CONFIG_LPS_CHK_BY_TP
  276. u8 lps_chk_by_tp;
  277. u16 lps_tx_tp_th;/*Mbps*/
  278. u16 lps_rx_tp_th;/*Mbps*/
  279. u16 lps_bi_tp_th;/*Mbps*//*TRX TP*/
  280. int lps_chk_cnt_th;
  281. int lps_chk_cnt;
  282. u32 lps_tx_pkts;
  283. u32 lps_rx_pkts;
  284. #endif
  285. #ifdef CONFIG_WMMPS_STA
  286. u8 wmm_smart_ps;
  287. #endif /* CONFIG_WMMPS_STA */
  288. u32 alives;
  289. _workitem cpwm_event;
  290. _workitem dma_event; /*for handle un-synchronized tx dma*/
  291. #ifdef CONFIG_LPS_RPWM_TIMER
  292. u8 brpwmtimeout;
  293. _workitem rpwmtimeoutwi;
  294. _timer pwr_rpwm_timer;
  295. #endif /* CONFIG_LPS_RPWM_TIMER */
  296. u8 bpower_saving; /* for LPS/IPS */
  297. u8 b_hw_radio_off;
  298. u8 reg_rfoff;
  299. u8 reg_pdnmode; /* powerdown mode */
  300. u32 rfoff_reason;
  301. /* RF OFF Level */
  302. u32 cur_ps_level;
  303. u32 reg_rfps_level;
  304. uint ips_enter_cnts;
  305. uint ips_leave_cnts;
  306. uint lps_enter_cnts;
  307. uint lps_leave_cnts;
  308. u8 ips_mode;
  309. u8 ips_org_mode;
  310. u8 ips_mode_req; /* used to accept the mode setting request, will update to ipsmode later */
  311. uint bips_processing;
  312. systime ips_deny_time; /* will deny IPS when system time is smaller than this */
  313. u8 pre_ips_type;/* 0: default flow, 1: carddisbale flow */
  314. /* ps_deny: if 0, power save is free to go; otherwise deny all kinds of power save. */
  315. /* Use PS_DENY_REASON to decide reason. */
  316. /* Don't access this variable directly without control function, */
  317. /* and this variable should be protected by lock. */
  318. u32 ps_deny;
  319. u8 ps_processing; /* temporarily used to mark whether in rtw_ps_processor */
  320. u8 fw_psmode_iface_id;
  321. u8 bLeisurePs;
  322. u8 LpsIdleCount;
  323. u8 power_mgnt;
  324. u8 org_power_mgnt;
  325. u8 bFwCurrentInPSMode;
  326. systime DelayLPSLastTimeStamp;
  327. s32 pnp_current_pwr_state;
  328. u8 pnp_bstop_trx;
  329. #ifdef CONFIG_AUTOSUSPEND
  330. int ps_flag; /* used by autosuspend */
  331. u8 bInternalAutoSuspend;
  332. #endif
  333. u8 bInSuspend;
  334. #ifdef CONFIG_BT_COEXIST
  335. u8 bAutoResume;
  336. u8 autopm_cnt;
  337. #endif
  338. u8 bSupportRemoteWakeup;
  339. u8 wowlan_wake_reason;
  340. u8 wowlan_last_wake_reason;
  341. u8 wowlan_ap_mode;
  342. u8 wowlan_mode;
  343. u8 wowlan_p2p_mode;
  344. u8 wowlan_pno_enable;
  345. u8 wowlan_in_resume;
  346. #ifdef CONFIG_GPIO_WAKEUP
  347. u8 is_high_active;
  348. #endif /* CONFIG_GPIO_WAKEUP */
  349. u8 hst2dev_high_active;
  350. #ifdef CONFIG_WOWLAN
  351. bool default_patterns_en;
  352. #ifdef CONFIG_IPV6
  353. u8 wowlan_ns_offload_en;
  354. #endif /*CONFIG_IPV6*/
  355. u8 wowlan_txpause_status;
  356. u8 wowlan_pattern_idx;
  357. u64 wowlan_fw_iv;
  358. struct rtl_priv_pattern patterns[MAX_WKFM_CAM_NUM];
  359. #ifdef CONFIG_PNO_SUPPORT
  360. u8 pno_inited;
  361. pno_nlo_info_t *pnlo_info;
  362. pno_scan_info_t *pscan_info;
  363. pno_ssid_list_t *pno_ssid_list;
  364. #endif /* CONFIG_PNO_SUPPORT */
  365. #ifdef CONFIG_WOW_PATTERN_HW_CAM
  366. _mutex wowlan_pattern_cam_mutex;
  367. #endif
  368. u8 wowlan_aoac_rpt_loc;
  369. struct aoac_report wowlan_aoac_rpt;
  370. u8 wowlan_dis_lps;/*for debug purpose*/
  371. #endif /* CONFIG_WOWLAN */
  372. _timer pwr_state_check_timer;
  373. int pwr_state_check_interval;
  374. u8 pwr_state_check_cnts;
  375. rt_rf_power_state rf_pwrstate;/* cur power state, only for IPS */
  376. /* rt_rf_power_state current_rfpwrstate; */
  377. rt_rf_power_state change_rfpwrstate;
  378. u8 bHWPowerdown; /* power down mode selection. 0:radio off, 1:power down */
  379. u8 bHWPwrPindetect; /* come from registrypriv.hwpwrp_detect. enable power down function. 0:disable, 1:enable */
  380. u8 bkeepfwalive;
  381. u8 brfoffbyhw;
  382. unsigned long PS_BBRegBackup[PSBBREG_TOTALCNT];
  383. #ifdef CONFIG_RESUME_IN_WORKQUEUE
  384. struct workqueue_struct *rtw_workqueue;
  385. _workitem resume_work;
  386. #endif
  387. #ifdef CONFIG_HAS_EARLYSUSPEND
  388. struct early_suspend early_suspend;
  389. u8 do_late_resume;
  390. #endif /* CONFIG_HAS_EARLYSUSPEND */
  391. #ifdef CONFIG_ANDROID_POWER
  392. android_early_suspend_t early_suspend;
  393. u8 do_late_resume;
  394. #endif
  395. #ifdef CONFIG_INTEL_PROXIM
  396. u8 stored_power_mgnt;
  397. #endif
  398. #ifdef CONFIG_LPS_POFF
  399. lps_poff_info_t *plps_poff_info;
  400. #endif
  401. u8 lps_level_bk;
  402. u8 lps_level; /*LPS_NORMAL,LPA_CG,LPS_PG*/
  403. #ifdef CONFIG_LPS_PG
  404. u8 lpspg_rsvd_page_locate;
  405. u8 blpspg_info_up;
  406. #endif
  407. u8 current_lps_hw_port_id;
  408. #ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS
  409. systime radio_on_start_time;
  410. systime pwr_saving_start_time;
  411. u32 pwr_saving_time;
  412. u32 on_time;
  413. u32 tx_time;
  414. u32 rx_time;
  415. #endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */
  416. };
  417. #define rtw_get_ips_mode_req(pwrctl) \
  418. (pwrctl)->ips_mode_req
  419. #define rtw_ips_mode_req(pwrctl, ips_mode) \
  420. (pwrctl)->ips_mode_req = (ips_mode)
  421. #define RTW_PWR_STATE_CHK_INTERVAL 2000
  422. #define _rtw_set_pwr_state_check_timer(pwrctl, ms) \
  423. do { \
  424. /*RTW_INFO("%s _rtw_set_pwr_state_check_timer(%p, %d)\n", __FUNCTION__, (pwrctl), (ms));*/ \
  425. _set_timer(&(pwrctl)->pwr_state_check_timer, (ms)); \
  426. } while (0)
  427. #define rtw_set_pwr_state_check_timer(pwrctl) \
  428. _rtw_set_pwr_state_check_timer((pwrctl), (pwrctl)->pwr_state_check_interval)
  429. extern void rtw_init_pwrctrl_priv(_adapter *adapter);
  430. extern void rtw_free_pwrctrl_priv(_adapter *adapter);
  431. #ifdef CONFIG_LPS_LCLK
  432. s32 rtw_register_task_alive(PADAPTER, u32 task);
  433. void rtw_unregister_task_alive(PADAPTER, u32 task);
  434. extern s32 rtw_register_tx_alive(PADAPTER padapter);
  435. extern void rtw_unregister_tx_alive(PADAPTER padapter);
  436. extern s32 rtw_register_rx_alive(PADAPTER padapter);
  437. extern void rtw_unregister_rx_alive(PADAPTER padapter);
  438. extern s32 rtw_register_cmd_alive(PADAPTER padapter);
  439. extern void rtw_unregister_cmd_alive(PADAPTER padapter);
  440. extern s32 rtw_register_evt_alive(PADAPTER padapter);
  441. extern void rtw_unregister_evt_alive(PADAPTER padapter);
  442. extern void cpwm_int_hdl(PADAPTER padapter, struct reportpwrstate_parm *preportpwrstate);
  443. extern void LPS_Leave_check(PADAPTER padapter);
  444. #endif
  445. extern void LeaveAllPowerSaveMode(PADAPTER Adapter);
  446. extern void LeaveAllPowerSaveModeDirect(PADAPTER Adapter);
  447. #ifdef CONFIG_IPS
  448. void _ips_enter(_adapter *padapter);
  449. void ips_enter(_adapter *padapter);
  450. int _ips_leave(_adapter *padapter);
  451. int ips_leave(_adapter *padapter);
  452. #endif
  453. void rtw_ps_processor(_adapter *padapter);
  454. #ifdef CONFIG_AUTOSUSPEND
  455. int autoresume_enter(_adapter *padapter);
  456. #endif
  457. #ifdef SUPPORT_HW_RFOFF_DETECTED
  458. rt_rf_power_state RfOnOffDetect(IN PADAPTER pAdapter);
  459. #endif
  460. #ifdef DBG_CHECK_FW_PS_STATE
  461. int rtw_fw_ps_state(PADAPTER padapter);
  462. #endif
  463. #ifdef CONFIG_LPS
  464. s32 LPS_RF_ON_check(PADAPTER padapter, u32 delay_ms);
  465. void LPS_Enter(PADAPTER padapter, const char *msg);
  466. void LPS_Leave(PADAPTER padapter, const char *msg);
  467. #ifdef CONFIG_CHECK_LEAVE_LPS
  468. #ifdef CONFIG_LPS_CHK_BY_TP
  469. void traffic_check_for_leave_lps_by_tp(PADAPTER padapter, u8 tx, struct sta_info *sta);
  470. #endif
  471. void traffic_check_for_leave_lps(PADAPTER padapter, u8 tx, u32 tx_packets);
  472. #endif /*CONFIG_CHECK_LEAVE_LPS*/
  473. void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode, const char *msg);
  474. void rtw_set_fw_in_ips_mode(PADAPTER padapter, u8 enable);
  475. u8 rtw_set_rpwm(_adapter *padapter, u8 val8);
  476. void rtw_wow_lps_level_decide(_adapter *adapter, u8 wow_en);
  477. #endif
  478. #ifdef CONFIG_RESUME_IN_WORKQUEUE
  479. void rtw_resume_in_workqueue(struct pwrctrl_priv *pwrpriv);
  480. #endif /* CONFIG_RESUME_IN_WORKQUEUE */
  481. #if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER)
  482. bool rtw_is_earlysuspend_registered(struct pwrctrl_priv *pwrpriv);
  483. bool rtw_is_do_late_resume(struct pwrctrl_priv *pwrpriv);
  484. void rtw_set_do_late_resume(struct pwrctrl_priv *pwrpriv, bool enable);
  485. void rtw_register_early_suspend(struct pwrctrl_priv *pwrpriv);
  486. void rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv);
  487. #else
  488. #define rtw_is_earlysuspend_registered(pwrpriv) _FALSE
  489. #define rtw_is_do_late_resume(pwrpriv) _FALSE
  490. #define rtw_set_do_late_resume(pwrpriv, enable) do {} while (0)
  491. #define rtw_register_early_suspend(pwrpriv) do {} while (0)
  492. #define rtw_unregister_early_suspend(pwrpriv) do {} while (0)
  493. #endif /* CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER */
  494. u8 rtw_interface_ps_func(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val);
  495. void rtw_set_ips_deny(_adapter *padapter, u32 ms);
  496. int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller);
  497. #define rtw_pwr_wakeup(adapter) _rtw_pwr_wakeup(adapter, RTW_PWR_STATE_CHK_INTERVAL, __FUNCTION__)
  498. #define rtw_pwr_wakeup_ex(adapter, ips_deffer_ms) _rtw_pwr_wakeup(adapter, ips_deffer_ms, __FUNCTION__)
  499. int rtw_pm_set_ips(_adapter *padapter, u8 mode);
  500. int rtw_pm_set_lps(_adapter *padapter, u8 mode);
  501. int rtw_pm_set_lps_level(_adapter *padapter, u8 level);
  502. void rtw_ps_deny(PADAPTER padapter, PS_DENY_REASON reason);
  503. void rtw_ps_deny_cancel(PADAPTER padapter, PS_DENY_REASON reason);
  504. u32 rtw_ps_deny_get(PADAPTER padapter);
  505. #if defined(CONFIG_WOWLAN)
  506. void rtw_get_current_ip_address(PADAPTER padapter, u8 *pcurrentip);
  507. void rtw_get_sec_iv(PADAPTER padapter, u8 *pcur_dot11txpn, u8 *StaAddr);
  508. bool rtw_check_pattern_valid(u8 *input, u8 len);
  509. bool rtw_wowlan_parser_pattern_cmd(u8 *input, char *pattern,
  510. int *pattern_len, char *bit_mask);
  511. void rtw_wow_pattern_sw_reset(_adapter *adapter);
  512. u8 rtw_set_default_pattern(_adapter *adapter);
  513. void rtw_wow_pattern_sw_dump(_adapter *adapter);
  514. #endif /* CONFIG_WOWLAN */
  515. #endif /* __RTL871X_PWRCTRL_H_ */