phydm_rainfo.c 57 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2007 - 2017 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * The full GNU General Public License is included in this distribution in the
  15. * file called LICENSE.
  16. *
  17. * Contact Information:
  18. * wlanfae <wlanfae@realtek.com>
  19. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20. * Hsinchu 300, Taiwan.
  21. *
  22. * Larry Finger <Larry.Finger@lwfinger.net>
  23. *
  24. *****************************************************************************/
  25. /*@************************************************************
  26. * include files
  27. ************************************************************/
  28. #include "mp_precomp.h"
  29. #include "phydm_precomp.h"
  30. boolean phydm_is_vht_rate(void *dm_void, u8 rate)
  31. {
  32. return ((rate & 0x7f) >= ODM_RATEVHTSS1MCS0) ? true : false;
  33. }
  34. boolean phydm_is_ht_rate(void *dm_void, u8 rate)
  35. {
  36. return (((rate & 0x7f) >= ODM_RATEMCS0) &&
  37. ((rate & 0x7f) <= ODM_RATEMCS31)) ? true : false;
  38. }
  39. boolean phydm_is_ofdm_rate(void *dm_void, u8 rate)
  40. {
  41. return (((rate & 0x7f) >= ODM_RATE6M) &&
  42. ((rate & 0x7f) <= ODM_RATE54M)) ? true : false;
  43. }
  44. boolean phydm_is_cck_rate(void *dm_void, u8 rate)
  45. {
  46. return ((rate & 0x7f) <= ODM_RATE11M) ? true : false;
  47. }
  48. u8 phydm_rate_2_rate_digit(void *dm_void, u8 rate)
  49. {
  50. u8 legacy_table[12] = {1, 2, 5, 11, 6, 9, 12, 18, 24, 36, 48, 54};
  51. u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/
  52. u8 rate_digit = 0;
  53. if (rate_idx >= ODM_RATEVHTSS1MCS0)
  54. rate_digit = (rate_idx - ODM_RATEVHTSS1MCS0) % 10;
  55. else if (rate_idx >= ODM_RATEMCS0)
  56. rate_digit = (rate_idx - ODM_RATEMCS0);
  57. else if (rate_idx <= ODM_RATE54M)
  58. rate_digit = legacy_table[rate_idx];
  59. return rate_digit;
  60. }
  61. u8 phydm_rate_type_2_num_ss(void *dm_void, enum PDM_RATE_TYPE type)
  62. {
  63. u8 num_ss = 1;
  64. switch (type) {
  65. case PDM_CCK:
  66. case PDM_OFDM:
  67. case PDM_1SS:
  68. num_ss = 1;
  69. break;
  70. case PDM_2SS:
  71. num_ss = 2;
  72. break;
  73. case PDM_3SS:
  74. num_ss = 3;
  75. break;
  76. case PDM_4SS:
  77. num_ss = 4;
  78. break;
  79. default:
  80. break;
  81. }
  82. return num_ss;
  83. }
  84. u8 phydm_rate_to_num_ss(void *dm_void, u8 data_rate)
  85. {
  86. u8 num_ss = 1;
  87. if (data_rate <= ODM_RATE54M)
  88. num_ss = 1;
  89. else if (data_rate <= ODM_RATEMCS31)
  90. num_ss = ((data_rate - ODM_RATEMCS0) >> 3) + 1;
  91. else if (data_rate <= ODM_RATEVHTSS1MCS9)
  92. num_ss = 1;
  93. else if (data_rate <= ODM_RATEVHTSS2MCS9)
  94. num_ss = 2;
  95. else if (data_rate <= ODM_RATEVHTSS3MCS9)
  96. num_ss = 3;
  97. else if (data_rate <= ODM_RATEVHTSS4MCS9)
  98. num_ss = 4;
  99. return num_ss;
  100. }
  101. void phydm_h2C_debug(void *dm_void, char input[][16], u32 *_used,
  102. char *output, u32 *_out_len)
  103. {
  104. struct dm_struct *dm = (struct dm_struct *)dm_void;
  105. u32 used = *_used;
  106. u32 out_len = *_out_len;
  107. u32 dm_value[10] = {0};
  108. u8 i = 0, input_idx = 0;
  109. u8 h2c_parameter[H2C_MAX_LENGTH] = {0};
  110. u8 phydm_h2c_id = 0;
  111. for (i = 0; i < 8; i++) {
  112. if (input[i + 1]) {
  113. PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]);
  114. input_idx++;
  115. }
  116. }
  117. if (input_idx == 0)
  118. return;
  119. phydm_h2c_id = (u8)dm_value[0];
  120. PDM_SNPF(out_len, used, output + used, out_len - used,
  121. "Phydm Send H2C_ID (( 0x%x))\n", phydm_h2c_id);
  122. for (i = 0; i < H2C_MAX_LENGTH; i++) {
  123. h2c_parameter[i] = (u8)dm_value[i + 1];
  124. PDM_SNPF(out_len, used, output + used, out_len - used,
  125. "H2C: Byte[%d] = ((0x%x))\n", i, h2c_parameter[i]);
  126. }
  127. odm_fill_h2c_cmd(dm, phydm_h2c_id, H2C_MAX_LENGTH, h2c_parameter);
  128. *_used = used;
  129. *_out_len = out_len;
  130. }
  131. void phydm_fw_fix_rate(void *dm_void, u8 en, u8 macid, u8 bw, u8 rate)
  132. {
  133. struct dm_struct *dm = (struct dm_struct *)dm_void;
  134. u32 reg_u32_tmp;
  135. if (dm->support_ic_type & PHYDM_IC_8051_SERIES) {
  136. reg_u32_tmp = (bw << 24) | (rate << 16) | (macid << 8) | en;
  137. odm_set_bb_reg(dm, R_0x4a0, MASKDWORD, reg_u32_tmp);
  138. } else {
  139. if (en == 1)
  140. reg_u32_tmp = BYTE_2_DWORD(0x60, macid, bw, rate);
  141. else
  142. reg_u32_tmp = 0x40000000;
  143. odm_set_bb_reg(dm, R_0x450, MASKDWORD, reg_u32_tmp);
  144. }
  145. if (en == 1) {
  146. PHYDM_DBG(dm, ODM_COMP_API,
  147. "FW fix TX rate[id =%d], %dM, Rate(%d)=", macid,
  148. (20 << bw), rate);
  149. phydm_print_rate(dm, rate, ODM_COMP_API);
  150. } else {
  151. PHYDM_DBG(dm, ODM_COMP_API, "Auto Rate\n");
  152. }
  153. }
  154. void phydm_ra_debug(void *dm_void, char input[][16], u32 *_used, char *output,
  155. u32 *_out_len)
  156. {
  157. struct dm_struct *dm = (struct dm_struct *)dm_void;
  158. struct ra_table *ra_tab = &dm->dm_ra_table;
  159. u32 used = *_used;
  160. u32 out_len = *_out_len;
  161. char help[] = "-h";
  162. u32 var[5] = {0};
  163. u8 macid = 0, bw = 0, rate = 0;
  164. u8 i = 0;
  165. for (i = 0; i < 5; i++) {
  166. if (input[i + 1])
  167. PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var[i]);
  168. }
  169. if ((strcmp(input[1], help) == 0)) {
  170. PDM_SNPF(out_len, used, output + used, out_len - used,
  171. "{1} {0:-,1:+} {ofst}: set offset\n");
  172. PDM_SNPF(out_len, used, output + used, out_len - used,
  173. "{1} {100}: show offset\n");
  174. PDM_SNPF(out_len, used, output + used, out_len - used,
  175. "{2} {en} {macid} {bw} {rate}: fw fix rate\n");
  176. } else if (var[0] == 1) { /*@Adjust PCR offset*/
  177. if (var[1] == 100) {
  178. PDM_SNPF(out_len, used, output + used, out_len - used,
  179. "[Get] RA_ofst=((%s%d))\n",
  180. ((ra_tab->ra_ofst_direc) ? "+" : "-"),
  181. ra_tab->ra_th_ofst);
  182. } else if (var[1] == 0) {
  183. ra_tab->ra_ofst_direc = 0;
  184. ra_tab->ra_th_ofst = (u8)var[2];
  185. PDM_SNPF(out_len, used, output + used, out_len - used,
  186. "[Set] RA_ofst=((-%d))\n", ra_tab->ra_th_ofst);
  187. } else if (var[1] == 1) {
  188. ra_tab->ra_ofst_direc = 1;
  189. ra_tab->ra_th_ofst = (u8)var[2];
  190. PDM_SNPF(out_len, used, output + used, out_len - used,
  191. "[Set] RA_ofst=((+%d))\n", ra_tab->ra_th_ofst);
  192. }
  193. } else if (var[0] == 2) { /*@FW fix rate*/
  194. macid = (u8)var[2];
  195. bw = (u8)var[3];
  196. rate = (u8)var[4];
  197. PDM_SNPF(out_len, used, output + used, out_len - used,
  198. "[FW fix TX Rate] {en, macid,bw,rate}={%d, %d, %d, 0x%x}",
  199. var[1], macid, bw, rate);
  200. phydm_fw_fix_rate(dm, (u8)var[1], macid, bw, rate);
  201. } else {
  202. PDM_SNPF(out_len, used, output + used, out_len - used,
  203. "[Set] Error\n");
  204. }
  205. *_used = used;
  206. *_out_len = out_len;
  207. }
  208. void odm_c2h_ra_para_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)
  209. {
  210. struct dm_struct *dm = (struct dm_struct *)dm_void;
  211. u8 mode = cmd_buf[0]; /*Retry Penalty, NH, NL*/
  212. u8 i;
  213. PHYDM_DBG(dm, DBG_FW_TRACE, "[%s] [mode: %d]----------------------->\n",
  214. __func__, mode);
  215. if (mode == RADBG_DEBUG_MONITOR1) {
  216. if (dm->support_ic_type & PHYDM_IC_3081_SERIES) {
  217. PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "RSSI =",
  218. cmd_buf[1]);
  219. PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", "rate =",
  220. cmd_buf[2] & 0x7f);
  221. PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "SGI =",
  222. (cmd_buf[2] & 0x80) >> 7);
  223. PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "BW =",
  224. cmd_buf[3]);
  225. PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "BW_max =",
  226. cmd_buf[4]);
  227. PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n",
  228. "multi_rate0 =", cmd_buf[5]);
  229. PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n",
  230. "multi_rate1 =", cmd_buf[6]);
  231. PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "DISRA =",
  232. cmd_buf[7]);
  233. PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "VHT_EN =",
  234. cmd_buf[8]);
  235. PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n",
  236. "SGI_support =", cmd_buf[9]);
  237. PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "try_ness =",
  238. cmd_buf[10]);
  239. PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", "pre_rate =",
  240. cmd_buf[11]);
  241. } else {
  242. PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "RSSI =",
  243. cmd_buf[1]);
  244. PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %x\n", "BW =",
  245. cmd_buf[2]);
  246. PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "DISRA =",
  247. cmd_buf[3]);
  248. PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "VHT_EN =",
  249. cmd_buf[4]);
  250. PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n",
  251. "Hightest rate =", cmd_buf[5]);
  252. PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n",
  253. "Lowest rate =", cmd_buf[6]);
  254. PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n",
  255. "SGI_support =", cmd_buf[7]);
  256. PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "Rate_ID =",
  257. cmd_buf[8]);
  258. }
  259. } else if (mode == RADBG_DEBUG_MONITOR2) {
  260. if (dm->support_ic_type & PHYDM_IC_3081_SERIES) {
  261. PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "rate_id =",
  262. cmd_buf[1]);
  263. PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n",
  264. "highest_rate =", cmd_buf[2]);
  265. PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n",
  266. "lowest_rate =", cmd_buf[3]);
  267. for (i = 4; i <= 11; i++)
  268. PHYDM_DBG(dm, DBG_FW_TRACE, "RAMASK = 0x%x\n",
  269. cmd_buf[i]);
  270. } else {
  271. PHYDM_DBG(dm, DBG_FW_TRACE,
  272. "%5s %x%x %x%x %x%x %x%x\n", "RA Mask:",
  273. cmd_buf[8], cmd_buf[7], cmd_buf[6],
  274. cmd_buf[5], cmd_buf[4], cmd_buf[3],
  275. cmd_buf[2], cmd_buf[1]);
  276. }
  277. } else if (mode == RADBG_DEBUG_MONITOR3) {
  278. for (i = 0; i < (cmd_len - 1); i++)
  279. PHYDM_DBG(dm, DBG_FW_TRACE, "content[%d] = %d\n", i,
  280. cmd_buf[1 + i]);
  281. } else if (mode == RADBG_DEBUG_MONITOR4)
  282. PHYDM_DBG(dm, DBG_FW_TRACE, "%5s {%d.%d}\n", "RA version =",
  283. cmd_buf[1], cmd_buf[2]);
  284. else if (mode == RADBG_DEBUG_MONITOR5) {
  285. PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", "Current rate =",
  286. cmd_buf[1]);
  287. PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "Retry ratio =",
  288. cmd_buf[2]);
  289. PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "rate down ratio =",
  290. cmd_buf[3]);
  291. PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", "highest rate =",
  292. cmd_buf[4]);
  293. PHYDM_DBG(dm, DBG_FW_TRACE, "%5s {0x%x 0x%x}\n", "Muti-try =",
  294. cmd_buf[5], cmd_buf[6]);
  295. PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x%x%x%x%x\n", "RA mask =",
  296. cmd_buf[11], cmd_buf[10], cmd_buf[9], cmd_buf[8],
  297. cmd_buf[7]);
  298. }
  299. PHYDM_DBG(dm, DBG_FW_TRACE, "-------------------------------\n");
  300. }
  301. void phydm_ra_dynamic_retry_count(void *dm_void)
  302. {
  303. struct dm_struct *dm = (struct dm_struct *)dm_void;
  304. if (!(dm->support_ability & ODM_BB_DYNAMIC_ARFR))
  305. return;
  306. #if 0
  307. /*PHYDM_DBG(dm, DBG_RA, "dm->pre_b_noisy = %d\n", dm->pre_b_noisy );*/
  308. #endif
  309. if (dm->pre_b_noisy != dm->noisy_decision) {
  310. if (dm->noisy_decision) {
  311. PHYDM_DBG(dm, DBG_DYN_ARFR, "Noisy Env. RA fallback\n");
  312. odm_set_mac_reg(dm, R_0x430, MASKDWORD, 0x0);
  313. odm_set_mac_reg(dm, R_0x434, MASKDWORD, 0x04030201);
  314. } else {
  315. PHYDM_DBG(dm, DBG_DYN_ARFR, "Clean Env. RA fallback\n");
  316. odm_set_mac_reg(dm, R_0x430, MASKDWORD, 0x01000000);
  317. odm_set_mac_reg(dm, R_0x434, MASKDWORD, 0x06050402);
  318. }
  319. dm->pre_b_noisy = dm->noisy_decision;
  320. }
  321. }
  322. void phydm_print_rate(void *dm_void, u8 rate, u32 dbg_component)
  323. {
  324. struct dm_struct *dm = (struct dm_struct *)dm_void;
  325. u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/
  326. boolean vht_en = phydm_is_vht_rate(dm, rate_idx);
  327. u8 b_sgi = (rate & 0x80) >> 7;
  328. u8 rate_ss = phydm_rate_to_num_ss(dm, rate_idx);
  329. u8 rate_digit = phydm_rate_2_rate_digit(dm, rate_idx);
  330. PHYDM_DBG_F(dm, dbg_component, "( %s%s%s%s%d%s%s)\n",
  331. (vht_en && (rate_ss == 1)) ? "VHT 1ss " : "",
  332. (vht_en && (rate_ss == 2)) ? "VHT 2ss " : "",
  333. (vht_en && (rate_ss == 3)) ? "VHT 3ss " : "",
  334. (rate_idx >= ODM_RATEMCS0) ? "MCS " : "",
  335. rate_digit,
  336. (b_sgi) ? "-S" : " ",
  337. (rate_idx >= ODM_RATEMCS0) ? "" : "M");
  338. }
  339. void phydm_print_rate_2_buff(void *dm_void, u8 rate, char *buf, u16 buf_size)
  340. {
  341. struct dm_struct *dm = (struct dm_struct *)dm_void;
  342. u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/
  343. boolean vht_en = phydm_is_vht_rate(dm, rate_idx);
  344. u8 b_sgi = (rate & 0x80) >> 7;
  345. u8 rate_ss = phydm_rate_to_num_ss(dm, rate_idx);
  346. u8 rate_digit = phydm_rate_2_rate_digit(dm, rate_idx);
  347. PHYDM_SNPRINTF(buf, buf_size, "( %s%s%s%s%d%s%s)",
  348. (vht_en && (rate_ss == 1)) ? "VHT 1ss " : "",
  349. (vht_en && (rate_ss == 2)) ? "VHT 2ss " : "",
  350. (vht_en && (rate_ss == 3)) ? "VHT 3ss " : "",
  351. (rate_idx >= ODM_RATEMCS0) ? "MCS " : "",
  352. rate_digit,
  353. (b_sgi) ? "-S" : " ",
  354. (rate_idx >= ODM_RATEMCS0) ? "" : "M");
  355. }
  356. void phydm_c2h_ra_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)
  357. {
  358. struct dm_struct *dm = (struct dm_struct *)dm_void;
  359. struct ra_table *ra_tab = &dm->dm_ra_table;
  360. struct cmn_sta_info *sta = NULL;
  361. u8 macid = cmd_buf[1];
  362. u8 rate = cmd_buf[0];
  363. u8 curr_ra_ratio = 0xff;
  364. u8 curr_bw = 0xff;
  365. u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/
  366. u8 rate_order;
  367. #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
  368. sta = dm->phydm_sta_info[dm->phydm_macid_table[macid]];
  369. #else
  370. sta = dm->phydm_sta_info[macid];
  371. #endif
  372. if (cmd_len >= 7) {
  373. curr_ra_ratio = cmd_buf[5];
  374. curr_bw = cmd_buf[6];
  375. PHYDM_DBG(dm, DBG_RA, "RA retry ratio: [%d]:", curr_ra_ratio);
  376. }
  377. if (cmd_buf[3] != 0) {
  378. if (cmd_buf[3] == 0xff)
  379. PHYDM_DBG(dm, DBG_RA, "FW Level: Fix rate[%d]:", macid);
  380. else if (cmd_buf[3] == 1)
  381. PHYDM_DBG(dm, DBG_RA, "Try Success[%d]:", macid);
  382. else if (cmd_buf[3] == 2)
  383. PHYDM_DBG(dm, DBG_RA, "Try Fail & Again[%d]:", macid);
  384. else if (cmd_buf[3] == 3)
  385. PHYDM_DBG(dm, DBG_RA, "rate Back[%d]:", macid);
  386. else if (cmd_buf[3] == 4)
  387. PHYDM_DBG(dm, DBG_RA, "start rate by RSSI[%d]:", macid);
  388. else if (cmd_buf[3] == 5)
  389. PHYDM_DBG(dm, DBG_RA, "Try rate[%d]:", macid);
  390. }
  391. PHYDM_DBG(dm, DBG_RA, "Tx rate Update[%d]:", macid);
  392. phydm_print_rate(dm, rate, DBG_RA);
  393. if (macid >= 128) {
  394. u8 gid_index = macid - 128;
  395. ra_tab->mu1_rate[gid_index] = rate;
  396. }
  397. /*@ra_tab->link_tx_rate[macid] = rate;*/
  398. if (is_sta_active(sta)) {
  399. sta->ra_info.curr_tx_rate = rate;
  400. sta->ra_info.curr_tx_bw = (enum channel_width)curr_bw;
  401. sta->ra_info.curr_retry_ratio = curr_ra_ratio;
  402. }
  403. /*trigger power training*/
  404. #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
  405. rate_order = phydm_rate_order_compute(dm, rate_idx);
  406. if (dm->is_one_entry_only ||
  407. (rate_order > ra_tab->highest_client_tx_order &&
  408. ra_tab->power_tracking_flag == 1)) {
  409. halrf_update_pwr_track(dm, rate_idx);
  410. ra_tab->power_tracking_flag = 0;
  411. }
  412. #endif
  413. #if 0
  414. /*trigger dynamic rate ID*/
  415. if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E))
  416. phydm_update_rate_id(dm, rate, macid);
  417. #endif
  418. }
  419. void odm_ra_post_action_on_assoc(void *dm_void)
  420. {
  421. #if 0
  422. struct dm_struct *dm = (struct dm_struct *)dm_void;
  423. dm->h2c_rarpt_connect = 1;
  424. phydm_rssi_monitor_check(dm);
  425. dm->h2c_rarpt_connect = 0;
  426. #endif
  427. }
  428. void phydm_modify_RA_PCR_threshold(void *dm_void, u8 ra_ofst_direc,
  429. u8 ra_th_ofst)
  430. {
  431. struct dm_struct *dm = (struct dm_struct *)dm_void;
  432. struct ra_table *ra_tab = &dm->dm_ra_table;
  433. ra_tab->ra_ofst_direc = ra_ofst_direc;
  434. ra_tab->ra_th_ofst = ra_th_ofst;
  435. PHYDM_DBG(dm, DBG_RA_MASK, "Set ra_th_offset=(( %s%d ))\n",
  436. ((ra_ofst_direc) ? "+" : "-"), ra_th_ofst);
  437. }
  438. #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
  439. void phydm_gen_ramask_h2c_AP(
  440. void *dm_void,
  441. struct rtl8192cd_priv *priv,
  442. struct sta_info *entry,
  443. u8 rssi_level)
  444. {
  445. struct dm_struct *dm = (struct dm_struct *)dm_void;
  446. if (dm->support_ic_type == ODM_RTL8812) {
  447. #if (RTL8812A_SUPPORT == 1)
  448. UpdateHalRAMask8812(priv, entry, rssi_level);
  449. #endif
  450. } else if (dm->support_ic_type == ODM_RTL8188E) {
  451. #if (RTL8188E_SUPPORT == 1)
  452. #ifdef TXREPORT
  453. add_RATid(priv, entry);
  454. #endif
  455. #endif
  456. } else {
  457. #ifdef CONFIG_WLAN_HAL
  458. GET_HAL_INTERFACE(priv)->UpdateHalRAMaskHandler(priv, entry, rssi_level);
  459. #endif
  460. }
  461. }
  462. void phydm_update_hal_ra_mask(
  463. void *dm_void,
  464. u32 wireless_mode,
  465. u8 rf_type,
  466. u8 bw,
  467. u8 mimo_ps_enable,
  468. u8 disable_cck_rate,
  469. u32 *ratr_bitmap_msb_in,
  470. u32 *ratr_bitmap_lsb_in,
  471. u8 tx_rate_level)
  472. {
  473. struct dm_struct *dm = (struct dm_struct *)dm_void;
  474. u32 ratr_bitmap = *ratr_bitmap_lsb_in;
  475. u32 ratr_bitmap_msb = *ratr_bitmap_msb_in;
  476. #if 0
  477. /*PHYDM_DBG(dm, DBG_RA_MASK, "phydm_rf_type = (( %x )), rf_type = (( %x ))\n", phydm_rf_type, rf_type);*/
  478. #endif
  479. PHYDM_DBG(dm, DBG_RA_MASK,
  480. "Platfoem original RA Mask = (( 0x %x | %x ))\n",
  481. ratr_bitmap_msb, ratr_bitmap);
  482. switch (wireless_mode) {
  483. case PHYDM_WIRELESS_MODE_B: {
  484. ratr_bitmap &= 0x0000000f;
  485. } break;
  486. case PHYDM_WIRELESS_MODE_G: {
  487. ratr_bitmap &= 0x00000ff5;
  488. } break;
  489. case PHYDM_WIRELESS_MODE_A: {
  490. ratr_bitmap &= 0x00000ff0;
  491. } break;
  492. case PHYDM_WIRELESS_MODE_N_24G:
  493. case PHYDM_WIRELESS_MODE_N_5G: {
  494. if (mimo_ps_enable)
  495. rf_type = RF_1T1R;
  496. if (rf_type == RF_1T1R) {
  497. if (bw == CHANNEL_WIDTH_40)
  498. ratr_bitmap &= 0x000ff015;
  499. else
  500. ratr_bitmap &= 0x000ff005;
  501. } else if (rf_type == RF_2T2R || rf_type == RF_2T4R || rf_type == RF_2T3R) {
  502. if (bw == CHANNEL_WIDTH_40)
  503. ratr_bitmap &= 0x0ffff015;
  504. else
  505. ratr_bitmap &= 0x0ffff005;
  506. } else { /*@3T*/
  507. ratr_bitmap &= 0xfffff015;
  508. ratr_bitmap_msb &= 0xf;
  509. }
  510. } break;
  511. case PHYDM_WIRELESS_MODE_AC_24G: {
  512. if (rf_type == RF_1T1R) {
  513. ratr_bitmap &= 0x003ff015;
  514. } else if (rf_type == RF_2T2R || rf_type == RF_2T4R || rf_type == RF_2T3R) {
  515. ratr_bitmap &= 0xfffff015;
  516. } else { /*@3T*/
  517. ratr_bitmap &= 0xfffff010;
  518. ratr_bitmap_msb &= 0x3ff;
  519. }
  520. if (bw == CHANNEL_WIDTH_20) { /*@AC 20MHz not support MCS9*/
  521. ratr_bitmap &= 0x7fdfffff;
  522. ratr_bitmap_msb &= 0x1ff;
  523. }
  524. } break;
  525. case PHYDM_WIRELESS_MODE_AC_5G: {
  526. if (rf_type == RF_1T1R) {
  527. ratr_bitmap &= 0x003ff010;
  528. } else if (rf_type == RF_2T2R || rf_type == RF_2T4R || rf_type == RF_2T3R) {
  529. ratr_bitmap &= 0xfffff010;
  530. } else { /*@3T*/
  531. ratr_bitmap &= 0xfffff010;
  532. ratr_bitmap_msb &= 0x3ff;
  533. }
  534. if (bw == CHANNEL_WIDTH_20) { /*@AC 20MHz not support MCS9*/
  535. ratr_bitmap &= 0x7fdfffff;
  536. ratr_bitmap_msb &= 0x1ff;
  537. }
  538. } break;
  539. default:
  540. break;
  541. }
  542. if (wireless_mode != PHYDM_WIRELESS_MODE_B) {
  543. if (tx_rate_level == 0)
  544. ratr_bitmap &= 0xffffffff;
  545. else if (tx_rate_level == 1)
  546. ratr_bitmap &= 0xfffffff0;
  547. else if (tx_rate_level == 2)
  548. ratr_bitmap &= 0xffffefe0;
  549. else if (tx_rate_level == 3)
  550. ratr_bitmap &= 0xffffcfc0;
  551. else if (tx_rate_level == 4)
  552. ratr_bitmap &= 0xffff8f80;
  553. else if (tx_rate_level >= 5)
  554. ratr_bitmap &= 0xffff0f00;
  555. }
  556. if (disable_cck_rate)
  557. ratr_bitmap &= 0xfffffff0;
  558. PHYDM_DBG(dm, DBG_RA_MASK,
  559. "wireless_mode= (( 0x%x )), rf_type = (( 0x%x )), BW = (( 0x%x )), MimoPs_en = (( %d )), tx_rate_level= (( 0x%x ))\n",
  560. wireless_mode, rf_type, bw, mimo_ps_enable, tx_rate_level);
  561. #if 0
  562. /*PHYDM_DBG(dm, DBG_RA_MASK, "111 Phydm modified RA Mask = (( 0x %x | %x ))\n", ratr_bitmap_msb, ratr_bitmap);*/
  563. #endif
  564. *ratr_bitmap_lsb_in = ratr_bitmap;
  565. *ratr_bitmap_msb_in = ratr_bitmap_msb;
  566. PHYDM_DBG(dm, DBG_RA_MASK,
  567. "Phydm modified RA Mask = (( 0x %x | %x ))\n",
  568. *ratr_bitmap_msb_in, *ratr_bitmap_lsb_in);
  569. }
  570. #if 0
  571. void odm_refresh_rate_adaptive_mask_ap(
  572. void *dm_void)
  573. {
  574. struct dm_struct *dm = (struct dm_struct *)dm_void;
  575. struct ra_table *ra_tab = &dm->dm_ra_table;
  576. struct rtl8192cd_priv *priv = dm->priv;
  577. struct aid_obj *aidarray;
  578. u32 i;
  579. struct sta_info *entry;
  580. struct cmn_sta_info *sta;
  581. u8 ratr_state_new;
  582. if (priv->up_time % 2)
  583. return;
  584. for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
  585. entry = dm->odm_sta_info[i];
  586. sta = dm->phydm_sta_info[i];
  587. if (!is_sta_active(sta))
  588. continue;
  589. #if defined(UNIVERSAL_REPEATER) || defined(MBSSID)
  590. aidarray = container_of(entry, struct aid_obj, station);
  591. priv = aidarray->priv;
  592. #endif
  593. if (!priv->pmib->dot11StationConfigEntry.autoRate)
  594. continue;
  595. ratr_state_new = phydm_rssi_lv_dec(dm, (u32)sta->rssi_stat.rssi, sta->ra_info.rssi_level);
  596. if (sta->ra_info.rssi_level != ratr_state_new || ra_tab->up_ramask_cnt >= FORCED_UPDATE_RAMASK_PERIOD) {
  597. ra_tab->up_ramask_cnt = 0;
  598. PHYDM_PRINT_ADDR(dm, DBG_RA_MASK, "Target AP addr :", sta->mac_addr);
  599. PHYDM_DBG(dm, DBG_RA_MASK,
  600. "Update Tx RA Level: ((%x)) -> ((%x)), RSSI = ((%d))\n",
  601. sta->ra_info.rssi_level, ratr_state_new,
  602. sta->rssi_stat.rssi);
  603. sta->ra_info.rssi_level = ratr_state_new;
  604. phydm_gen_ramask_h2c_AP(dm, priv, entry, sta->ra_info.rssi_level);
  605. } else {
  606. PHYDM_DBG(dm, DBG_RA_MASK,
  607. "Stay in RA level = (( %d ))\n\n",
  608. ratr_state_new);
  609. }
  610. }
  611. }
  612. #endif
  613. #endif
  614. void phydm_rate_adaptive_mask_init(void *dm_void)
  615. {
  616. struct dm_struct *dm = (struct dm_struct *)dm_void;
  617. struct ra_table *ra_t = &dm->dm_ra_table;
  618. #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
  619. PADAPTER adapter = dm->adapter;
  620. PMGNT_INFO mgnt_info = &(adapter->MgntInfo);
  621. HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)dm->adapter));
  622. if (mgnt_info->DM_Type == dm_type_by_driver)
  623. hal_data->bUseRAMask = true;
  624. else
  625. hal_data->bUseRAMask = false;
  626. #endif
  627. ra_t->ldpc_thres = 35;
  628. ra_t->up_ramask_cnt = 0;
  629. ra_t->up_ramask_cnt_tmp = 0;
  630. }
  631. void phydm_refresh_rate_adaptive_mask(void *dm_void)
  632. {
  633. /*@Will be removed*/
  634. struct dm_struct *dm = (struct dm_struct *)dm_void;
  635. phydm_ra_mask_watchdog(dm);
  636. }
  637. void phydm_show_sta_info(void *dm_void, char input[][16], u32 *_used,
  638. char *output, u32 *_out_len)
  639. {
  640. struct dm_struct *dm = (struct dm_struct *)dm_void;
  641. struct cmn_sta_info *sta = NULL;
  642. struct ra_sta_info *ra = NULL;
  643. #ifdef CONFIG_BEAMFORMING
  644. struct bf_cmn_info *bf = NULL;
  645. #endif
  646. char help[] = "-h";
  647. u32 var[10] = {0};
  648. u32 used = *_used;
  649. u32 out_len = *_out_len;
  650. u32 i, sta_idx_start, sta_idx_end;
  651. u8 tatal_sta_num = 0;
  652. PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var[0]);
  653. if ((strcmp(input[1], help) == 0)) {
  654. PDM_SNPF(out_len, used, output + used, out_len - used,
  655. "All STA: {1}\n");
  656. PDM_SNPF(out_len, used, output + used, out_len - used,
  657. "STA[macid]: {2} {macid}\n");
  658. return;
  659. } else if (var[0] == 1) {
  660. sta_idx_start = 0;
  661. sta_idx_end = ODM_ASSOCIATE_ENTRY_NUM;
  662. } else if (var[0] == 2) {
  663. sta_idx_start = var[1];
  664. sta_idx_end = var[1];
  665. } else {
  666. PDM_SNPF(out_len, used, output + used, out_len - used,
  667. "Warning input value!\n");
  668. return;
  669. }
  670. for (i = sta_idx_start; i < sta_idx_end; i++) {
  671. sta = dm->phydm_sta_info[i];
  672. if (!is_sta_active(sta))
  673. continue;
  674. ra = &sta->ra_info;
  675. #ifdef CONFIG_BEAMFORMING
  676. bf = &sta->bf_info;
  677. #endif
  678. tatal_sta_num++;
  679. PDM_SNPF(out_len, used, output + used, out_len - used,
  680. "==[sta_idx: %d][MACID: %d]============>\n", i,
  681. sta->mac_id);
  682. PDM_SNPF(out_len, used, output + used, out_len - used,
  683. "AID:%d\n", sta->aid);
  684. PDM_SNPF(out_len, used, output + used, out_len - used,
  685. "ADDR:%x-%x-%x-%x-%x-%x\n", sta->mac_addr[5],
  686. sta->mac_addr[4], sta->mac_addr[3], sta->mac_addr[2],
  687. sta->mac_addr[1], sta->mac_addr[0]);
  688. PDM_SNPF(out_len, used, output + used, out_len - used,
  689. "DM_ctrl:0x%x\n", sta->dm_ctrl);
  690. PDM_SNPF(out_len, used, output + used, out_len - used,
  691. "BW:%d, MIMO_Type:0x%x\n", sta->bw_mode,
  692. sta->mimo_type);
  693. PDM_SNPF(out_len, used, output + used, out_len - used,
  694. "STBC_en:%d, LDPC_en=%d\n", sta->stbc_en,
  695. sta->ldpc_en);
  696. /*@[RSSI Info]*/
  697. PDM_SNPF(out_len, used, output + used, out_len - used,
  698. "RSSI{All, OFDM, CCK}={%d, %d, %d}\n",
  699. sta->rssi_stat.rssi, sta->rssi_stat.rssi_ofdm,
  700. sta->rssi_stat.rssi_cck);
  701. /*@[RA Info]*/
  702. PDM_SNPF(out_len, used, output + used, out_len - used,
  703. "Rate_ID:%d, RSSI_LV:%d, ra_bw:%d, SGI_en:%d\n",
  704. ra->rate_id, ra->rssi_level, ra->ra_bw_mode,
  705. ra->is_support_sgi);
  706. PDM_SNPF(out_len, used, output + used, out_len - used,
  707. "VHT_en:%d, Wireless_set=0x%x, sm_ps=%d\n",
  708. ra->is_vht_enable, sta->support_wireless_set,
  709. sta->sm_ps);
  710. PDM_SNPF(out_len, used, output + used, out_len - used,
  711. "Dis{RA, PT}={%d, %d}, TxRx:%d, Noisy:%d\n",
  712. ra->disable_ra, ra->disable_pt, ra->txrx_state,
  713. ra->is_noisy);
  714. PDM_SNPF(out_len, used, output + used, out_len - used,
  715. "TX{Rate, BW}={0x%x, %d}, RTY:%d\n", ra->curr_tx_rate,
  716. ra->curr_tx_bw, ra->curr_retry_ratio);
  717. PDM_SNPF(out_len, used, output + used, out_len - used,
  718. "RA_Mask:0x%llx\n", ra->ramask);
  719. /*@[TP]*/
  720. PDM_SNPF(out_len, used, output + used, out_len - used,
  721. "TP{TX,RX}={%d, %d}\n", sta->tx_moving_average_tp,
  722. sta->rx_moving_average_tp);
  723. #ifdef CONFIG_BEAMFORMING
  724. /*@[Beamforming]*/
  725. PDM_SNPF(out_len, used, output + used, out_len - used,
  726. "BF CAP{HT,VHT}={0x%x, 0x%x}\n", bf->ht_beamform_cap,
  727. bf->vht_beamform_cap);
  728. PDM_SNPF(out_len, used, output + used, out_len - used,
  729. "BF {p_aid,g_id}={0x%x, 0x%x}\n\n", bf->p_aid,
  730. bf->g_id);
  731. #endif
  732. }
  733. if (tatal_sta_num == 0) {
  734. PDM_SNPF(out_len, used, output + used, out_len - used,
  735. "No Linked STA\n");
  736. }
  737. *_used = used;
  738. *_out_len = out_len;
  739. }
  740. u8 phydm_get_tx_stream_num(void *dm_void, enum rf_type type)
  741. {
  742. struct dm_struct *dm = (struct dm_struct *)dm_void;
  743. u8 tx_num = 1;
  744. if (type == RF_1T1R || type == RF_1T2R)
  745. tx_num = 1;
  746. else if (type == RF_2T2R || type == RF_2T3R || type == RF_2T4R)
  747. tx_num = 2;
  748. else if (type == RF_3T3R || type == RF_3T4R)
  749. tx_num = 3;
  750. else if (type == RF_4T4R)
  751. tx_num = 4;
  752. else
  753. PHYDM_DBG(dm, DBG_RA, "[Warrning] no mimo_type is found\n");
  754. return tx_num;
  755. }
  756. u64 phydm_get_bb_mod_ra_mask(void *dm_void, u8 sta_idx)
  757. {
  758. struct dm_struct *dm = (struct dm_struct *)dm_void;
  759. struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
  760. struct ra_sta_info *ra = NULL;
  761. enum channel_width bw = 0;
  762. enum wireless_set wrls_mode = 0;
  763. u8 tx_stream_num = 1;
  764. u8 rssi_lv = 0;
  765. u64 ra_mask_bitmap = 0;
  766. if (is_sta_active(sta)) {
  767. ra = &sta->ra_info;
  768. bw = ra->ra_bw_mode;
  769. wrls_mode = sta->support_wireless_set;
  770. tx_stream_num = phydm_get_tx_stream_num(dm, sta->mimo_type);
  771. rssi_lv = ra->rssi_level;
  772. ra_mask_bitmap = ra->ramask;
  773. } else {
  774. PHYDM_DBG(dm, DBG_RA, "[Warning] %s invalid STA\n", __func__);
  775. return 0;
  776. }
  777. PHYDM_DBG(dm, DBG_RA, "macid=%d ori_RA_Mask= 0x%llx\n", sta->mac_id,
  778. ra_mask_bitmap);
  779. PHYDM_DBG(dm, DBG_RA,
  780. "wireless_mode=0x%x, tx_ss=%d, BW=%d, MimoPs=%d, rssi_lv=%d\n",
  781. wrls_mode, tx_stream_num, bw, sta->sm_ps, rssi_lv);
  782. if (sta->sm_ps == SM_PS_STATIC) /*@mimo_ps_enable*/
  783. tx_stream_num = 1;
  784. /*@[Modify RA Mask by Wireless Mode]*/
  785. if (wrls_mode == WIRELESS_CCK) { /*@B mode*/
  786. ra_mask_bitmap &= 0x0000000f;
  787. } else if (wrls_mode == WIRELESS_OFDM) { /*@G mode*/
  788. ra_mask_bitmap &= 0x00000ff0;
  789. } else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM)) { /*@BG mode*/
  790. ra_mask_bitmap &= 0x00000ff5;
  791. } else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT)) {
  792. /*N_2G*/
  793. if (tx_stream_num == 1) {
  794. if (bw == CHANNEL_WIDTH_40)
  795. ra_mask_bitmap &= 0x000ff015;
  796. else
  797. ra_mask_bitmap &= 0x000ff005;
  798. } else if (tx_stream_num == 2) {
  799. if (bw == CHANNEL_WIDTH_40)
  800. ra_mask_bitmap &= 0x0ffff015;
  801. else
  802. ra_mask_bitmap &= 0x0ffff005;
  803. } else if (tx_stream_num == 3) {
  804. ra_mask_bitmap &= 0xffffff015;
  805. } else {
  806. ra_mask_bitmap &= 0xffffffff015;
  807. }
  808. } else if (wrls_mode == (WIRELESS_OFDM | WIRELESS_HT)) { /*N_5G*/
  809. if (tx_stream_num == 1) {
  810. if (bw == CHANNEL_WIDTH_40)
  811. ra_mask_bitmap &= 0x000ff030;
  812. else
  813. ra_mask_bitmap &= 0x000ff010;
  814. } else if (tx_stream_num == 2) {
  815. if (bw == CHANNEL_WIDTH_40)
  816. ra_mask_bitmap &= 0x0ffff030;
  817. else
  818. ra_mask_bitmap &= 0x0ffff010;
  819. } else if (tx_stream_num == 3) {
  820. ra_mask_bitmap &= 0xffffff010;
  821. } else {
  822. ra_mask_bitmap &= 0xffffffff010;
  823. }
  824. } else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT)) {
  825. /*@AC_2G*/
  826. if (tx_stream_num == 1)
  827. ra_mask_bitmap &= 0x003ff015;
  828. else if (tx_stream_num == 2)
  829. ra_mask_bitmap &= 0xfffff015;
  830. else if (tx_stream_num == 3)
  831. ra_mask_bitmap &= 0x3fffffff015;
  832. else /*@AC_4SS 2G*/
  833. ra_mask_bitmap &= 0x000ffffffffff015;
  834. if (bw == CHANNEL_WIDTH_20) {
  835. /* @AC 20MHz doesn't support MCS9 except 3SS & 6SS*/
  836. ra_mask_bitmap &= 0x0007ffff7fdff015;
  837. } else if (bw == CHANNEL_WIDTH_80) {
  838. /* @AC 80MHz doesn't support 3SS MCS6*/
  839. ra_mask_bitmap &= 0x000fffbffffff015;
  840. }
  841. } else if (wrls_mode == (WIRELESS_OFDM | WIRELESS_VHT)) { /*@AC_5G*/
  842. if (tx_stream_num == 1)
  843. ra_mask_bitmap &= 0x003ff010;
  844. else if (tx_stream_num == 2)
  845. ra_mask_bitmap &= 0xfffff010;
  846. else if (tx_stream_num == 3)
  847. ra_mask_bitmap &= 0x3fffffff010;
  848. else /*@AC_4SS 5G*/
  849. ra_mask_bitmap &= 0x000ffffffffff010;
  850. if (bw == CHANNEL_WIDTH_20) {
  851. /* @AC 20MHz doesn't support MCS9 except 3SS & 6SS*/
  852. ra_mask_bitmap &= 0x0007ffff7fdff010;
  853. } else if (bw == CHANNEL_WIDTH_80) {
  854. /* @AC 80MHz doesn't support 3SS MCS6*/
  855. ra_mask_bitmap &= 0x000fffbffffff010;
  856. }
  857. } else {
  858. PHYDM_DBG(dm, DBG_RA, "[Warrning] RA mask is Not found\n");
  859. }
  860. PHYDM_DBG(dm, DBG_RA, "Mod by mode=0x%llx\n", ra_mask_bitmap);
  861. /*@[Modify RA Mask by RSSI level]*/
  862. if (wrls_mode != WIRELESS_CCK) {
  863. if (rssi_lv == 0)
  864. ra_mask_bitmap &= 0xffffffffffffffff;
  865. else if (rssi_lv == 1)
  866. ra_mask_bitmap &= 0xfffffffffffffff0;
  867. else if (rssi_lv == 2)
  868. ra_mask_bitmap &= 0xffffffffffffefe0;
  869. else if (rssi_lv == 3)
  870. ra_mask_bitmap &= 0xffffffffffffcfc0;
  871. else if (rssi_lv == 4)
  872. ra_mask_bitmap &= 0xffffffffffff8f80;
  873. else if (rssi_lv >= 5)
  874. ra_mask_bitmap &= 0xffffffffffff0f00;
  875. }
  876. PHYDM_DBG(dm, DBG_RA, "Mod by RSSI=0x%llx\n", ra_mask_bitmap);
  877. return ra_mask_bitmap;
  878. }
  879. u8 phydm_get_rate_from_rssi_lv(void *dm_void, u8 sta_idx)
  880. {
  881. struct dm_struct *dm = (struct dm_struct *)dm_void;
  882. struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
  883. struct ra_sta_info *ra = NULL;
  884. enum wireless_set wrls_set = 0;
  885. u8 rssi_lv = 0;
  886. u8 rate_idx = 0;
  887. u8 rate_ofst = 0;
  888. if (is_sta_active(sta)) {
  889. ra = &sta->ra_info;
  890. wrls_set = sta->support_wireless_set;
  891. rssi_lv = ra->rssi_level;
  892. } else {
  893. pr_debug("[Warning] %s: invalid STA\n", __func__);
  894. return 0;
  895. }
  896. PHYDM_DBG(dm, DBG_RA, "[%s]macid=%d, wireless_set=0x%x, rssi_lv=%d\n",
  897. __func__, sta->mac_id, wrls_set, rssi_lv);
  898. rate_ofst = (rssi_lv <= 1) ? 0 : (rssi_lv - 1);
  899. if (wrls_set & WIRELESS_VHT) {
  900. rate_idx = ODM_RATEVHTSS1MCS0 + rate_ofst;
  901. } else if (wrls_set & WIRELESS_HT) {
  902. rate_idx = ODM_RATEMCS0 + rate_ofst;
  903. } else if (wrls_set & WIRELESS_OFDM) {
  904. rate_idx = ODM_RATE6M + rate_ofst;
  905. } else {
  906. rate_idx = ODM_RATE1M + rate_ofst;
  907. if (rate_idx > ODM_RATE11M)
  908. rate_idx = ODM_RATE11M;
  909. }
  910. return rate_idx;
  911. }
  912. u8 phydm_get_rate_id(void *dm_void, u8 sta_idx)
  913. {
  914. struct dm_struct *dm = (struct dm_struct *)dm_void;
  915. struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
  916. struct ra_sta_info *ra = NULL;
  917. enum channel_width bw = 0;
  918. enum wireless_set wrls_mode = 0;
  919. u8 tx_stream_num = 1;
  920. u8 rate_id_idx = PHYDM_BGN_20M_1SS;
  921. if (is_sta_active(sta)) {
  922. ra = &sta->ra_info;
  923. bw = ra->ra_bw_mode;
  924. wrls_mode = sta->support_wireless_set;
  925. tx_stream_num = phydm_get_tx_stream_num(dm, sta->mimo_type);
  926. } else {
  927. PHYDM_DBG(dm, DBG_RA, "[Warning] %s: invalid STA\n", __func__);
  928. return 0;
  929. }
  930. PHYDM_DBG(dm, DBG_RA, "macid=%d,wireless_set=0x%x,tx_SS_num=%d,BW=%d\n",
  931. sta->mac_id, wrls_mode, tx_stream_num, bw);
  932. if (wrls_mode == WIRELESS_CCK) {
  933. /*@B mode*/
  934. rate_id_idx = PHYDM_B_20M;
  935. } else if (wrls_mode == WIRELESS_OFDM) {
  936. /*@G mode*/
  937. rate_id_idx = PHYDM_G;
  938. } else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM)) {
  939. /*@BG mode*/
  940. rate_id_idx = PHYDM_BG;
  941. } else if (wrls_mode == (WIRELESS_OFDM | WIRELESS_HT)) {
  942. /*@GN mode*/
  943. if (tx_stream_num == 1)
  944. rate_id_idx = PHYDM_GN_N1SS;
  945. else if (tx_stream_num == 2)
  946. rate_id_idx = PHYDM_GN_N2SS;
  947. else if (tx_stream_num == 3)
  948. rate_id_idx = PHYDM_ARFR5_N_3SS;
  949. } else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT)) {
  950. /*@BGN mode*/
  951. if (bw == CHANNEL_WIDTH_40) {
  952. if (tx_stream_num == 1)
  953. rate_id_idx = PHYDM_BGN_40M_1SS;
  954. else if (tx_stream_num == 2)
  955. rate_id_idx = PHYDM_BGN_40M_2SS;
  956. else if (tx_stream_num == 3)
  957. rate_id_idx = PHYDM_ARFR5_N_3SS;
  958. else if (tx_stream_num == 4)
  959. rate_id_idx = PHYDM_ARFR7_N_4SS;
  960. } else {
  961. if (tx_stream_num == 1)
  962. rate_id_idx = PHYDM_BGN_20M_1SS;
  963. else if (tx_stream_num == 2)
  964. rate_id_idx = PHYDM_BGN_20M_2SS;
  965. else if (tx_stream_num == 3)
  966. rate_id_idx = PHYDM_ARFR5_N_3SS;
  967. else if (tx_stream_num == 4)
  968. rate_id_idx = PHYDM_ARFR7_N_4SS;
  969. }
  970. } else if (wrls_mode == (WIRELESS_OFDM | WIRELESS_VHT)) {
  971. /*@AC mode*/
  972. if (tx_stream_num == 1)
  973. rate_id_idx = PHYDM_ARFR1_AC_1SS;
  974. else if (tx_stream_num == 2)
  975. rate_id_idx = PHYDM_ARFR0_AC_2SS;
  976. else if (tx_stream_num == 3)
  977. rate_id_idx = PHYDM_ARFR4_AC_3SS;
  978. else if (tx_stream_num == 4)
  979. rate_id_idx = PHYDM_ARFR6_AC_4SS;
  980. } else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT)) {
  981. /*@AC 2.4G mode*/
  982. if (bw >= CHANNEL_WIDTH_80) {
  983. if (tx_stream_num == 1)
  984. rate_id_idx = PHYDM_ARFR1_AC_1SS;
  985. else if (tx_stream_num == 2)
  986. rate_id_idx = PHYDM_ARFR0_AC_2SS;
  987. else if (tx_stream_num == 3)
  988. rate_id_idx = PHYDM_ARFR4_AC_3SS;
  989. else if (tx_stream_num == 4)
  990. rate_id_idx = PHYDM_ARFR6_AC_4SS;
  991. } else {
  992. if (tx_stream_num == 1)
  993. rate_id_idx = PHYDM_ARFR2_AC_2G_1SS;
  994. else if (tx_stream_num == 2)
  995. rate_id_idx = PHYDM_ARFR3_AC_2G_2SS;
  996. else if (tx_stream_num == 3)
  997. rate_id_idx = PHYDM_ARFR4_AC_3SS;
  998. else if (tx_stream_num == 4)
  999. rate_id_idx = PHYDM_ARFR6_AC_4SS;
  1000. }
  1001. } else {
  1002. PHYDM_DBG(dm, DBG_RA, "[Warrning] No rate_id is found\n");
  1003. rate_id_idx = 0;
  1004. }
  1005. PHYDM_DBG(dm, DBG_RA, "Rate_ID=((0x%x))\n", rate_id_idx);
  1006. return rate_id_idx;
  1007. }
  1008. void phydm_ra_h2c(void *dm_void, u8 sta_idx, u8 dis_ra, u8 dis_pt,
  1009. u8 no_update_bw, u8 init_ra_lv, u64 ra_mask)
  1010. {
  1011. struct dm_struct *dm = (struct dm_struct *)dm_void;
  1012. struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
  1013. struct ra_sta_info *ra = NULL;
  1014. u8 h2c_val[H2C_MAX_LENGTH] = {0};
  1015. if (is_sta_active(sta)) {
  1016. ra = &sta->ra_info;
  1017. } else {
  1018. PHYDM_DBG(dm, DBG_RA, "[Warning] %s invalid sta_info\n",
  1019. __func__);
  1020. return;
  1021. }
  1022. PHYDM_DBG(dm, DBG_RA, "%s ======>\n", __func__);
  1023. PHYDM_DBG(dm, DBG_RA, "MACID=%d\n", sta->mac_id);
  1024. if (dm->is_disable_power_training)
  1025. dis_pt = true;
  1026. else if (!dm->is_disable_power_training)
  1027. dis_pt = false;
  1028. h2c_val[0] = sta->mac_id;
  1029. h2c_val[1] = (ra->rate_id & 0x1f) | ((init_ra_lv & 0x3) << 5) |
  1030. (ra->is_support_sgi << 7);
  1031. h2c_val[2] = (u8)((ra->ra_bw_mode) | (((sta->ldpc_en) ? 1 : 0) << 2) |
  1032. ((no_update_bw & 0x1) << 3) |
  1033. (ra->is_vht_enable << 4) |
  1034. ((dis_pt & 0x1) << 6) | ((dis_ra & 0x1) << 7));
  1035. h2c_val[3] = (u8)(ra_mask & 0xff);
  1036. h2c_val[4] = (u8)((ra_mask & 0xff00) >> 8);
  1037. h2c_val[5] = (u8)((ra_mask & 0xff0000) >> 16);
  1038. h2c_val[6] = (u8)((ra_mask & 0xff000000) >> 24);
  1039. PHYDM_DBG(dm, DBG_RA, "PHYDM h2c[0x40]=0x%x %x %x %x %x %x %x\n",
  1040. h2c_val[6], h2c_val[5], h2c_val[4], h2c_val[3], h2c_val[2],
  1041. h2c_val[1], h2c_val[0]);
  1042. odm_fill_h2c_cmd(dm, PHYDM_H2C_RA_MASK, H2C_MAX_LENGTH, h2c_val);
  1043. #if (defined(PHYDM_COMPILE_ABOVE_3SS))
  1044. if (dm->support_ic_type & (PHYDM_IC_ABOVE_3SS)) {
  1045. h2c_val[3] = (u8)((ra_mask >> 32) & 0x000000ff);
  1046. h2c_val[4] = (u8)(((ra_mask >> 32) & 0x0000ff00) >> 8);
  1047. h2c_val[5] = (u8)(((ra_mask >> 32) & 0x00ff0000) >> 16);
  1048. h2c_val[6] = (u8)(((ra_mask >> 32) & 0xff000000) >> 24);
  1049. PHYDM_DBG(dm, DBG_RA, "h2c[0x46]=0x%x %x %x %x %x %x %x\n",
  1050. h2c_val[6], h2c_val[5], h2c_val[4], h2c_val[3],
  1051. h2c_val[2], h2c_val[1], h2c_val[0]);
  1052. odm_fill_h2c_cmd(dm, PHYDM_RA_MASK_ABOVE_3SS, 5, h2c_val);
  1053. }
  1054. #endif
  1055. }
  1056. void phydm_ra_registed(void *dm_void, u8 sta_idx,
  1057. /*@index of sta_info array, not MACID*/
  1058. u8 rssi_from_assoc)
  1059. {
  1060. struct dm_struct *dm = (struct dm_struct *)dm_void;
  1061. struct ra_table *ra_t = &dm->dm_ra_table;
  1062. struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
  1063. struct ra_sta_info *ra = NULL;
  1064. u8 init_ra_lv = 0;
  1065. u64 ra_mask = 0;
  1066. /*@SD7 STA_idx != macid*/
  1067. /*@SD4,8 STA_idx == macid, */
  1068. PHYDM_DBG(dm, DBG_RA_MASK, "%s ======>\n", __func__);
  1069. if (is_sta_active(sta)) {
  1070. ra = &sta->ra_info;
  1071. PHYDM_DBG(dm, DBG_RA_MASK, "sta_idx=%d, macid=%d\n", sta_idx,
  1072. sta->mac_id);
  1073. } else {
  1074. PHYDM_DBG(dm, DBG_RA_MASK, "[Warning] %s invalid STA\n",
  1075. __func__);
  1076. PHYDM_DBG(dm, DBG_RA_MASK, "sta_idx=%d\n", sta_idx);
  1077. return;
  1078. }
  1079. #if (RTL8188E_SUPPORT == 1) && (RATE_ADAPTIVE_SUPPORT == 1)
  1080. if (dm->support_ic_type == ODM_RTL8188E)
  1081. ra->rate_id = phydm_get_rate_id_88e(dm, sta_idx);
  1082. else
  1083. #endif
  1084. {
  1085. ra->rate_id = phydm_get_rate_id(dm, sta_idx);
  1086. }
  1087. ra_mask = phydm_get_bb_mod_ra_mask(dm, sta_idx);
  1088. PHYDM_DBG(dm, DBG_RA_MASK, "rssi_assoc=%d\n", rssi_from_assoc);
  1089. if (rssi_from_assoc > 40)
  1090. init_ra_lv = 1;
  1091. else if (rssi_from_assoc > 20)
  1092. init_ra_lv = 2;
  1093. else if (rssi_from_assoc > 1)
  1094. init_ra_lv = 3;
  1095. else
  1096. init_ra_lv = 0;
  1097. if (ra_t->record_ra_info)
  1098. ra_t->record_ra_info(dm, sta_idx, sta, ra_mask);
  1099. #if (RTL8188E_SUPPORT == 1) && (RATE_ADAPTIVE_SUPPORT == 1)
  1100. if (dm->support_ic_type == ODM_RTL8188E)
  1101. /*@Driver RA*/
  1102. phydm_ra_update_8188e(dm, sta_idx, ra->rate_id,
  1103. (u32)ra_mask, ra->is_support_sgi);
  1104. else
  1105. #endif
  1106. {
  1107. /*@FW RA*/
  1108. phydm_ra_h2c(dm, sta_idx, ra->disable_ra, ra->disable_pt, 0,
  1109. init_ra_lv, ra_mask);
  1110. }
  1111. }
  1112. void phydm_ra_offline(void *dm_void, u8 sta_idx)
  1113. {
  1114. struct dm_struct *dm = (struct dm_struct *)dm_void;
  1115. struct ra_table *ra_t = &dm->dm_ra_table;
  1116. struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
  1117. struct ra_sta_info *ra = NULL;
  1118. if (is_sta_active(sta)) {
  1119. ra = &sta->ra_info;
  1120. } else {
  1121. PHYDM_DBG(dm, DBG_RA, "[Warning] %s invalid STA\n", __func__);
  1122. return;
  1123. }
  1124. PHYDM_DBG(dm, DBG_RA, "%s ======>\n", __func__);
  1125. PHYDM_DBG(dm, DBG_RA, "MACID=%d\n", sta->mac_id);
  1126. odm_memory_set(dm, &ra->rate_id, 0, sizeof(struct ra_sta_info));
  1127. ra->disable_ra = 1;
  1128. ra->disable_pt = 1;
  1129. if (ra_t->record_ra_info)
  1130. ra_t->record_ra_info(dm, sta->mac_id, sta, 0);
  1131. if (dm->support_ic_type != ODM_RTL8188E)
  1132. phydm_ra_h2c(dm, sta->mac_id, 1, 1, 0, 0, 0);
  1133. }
  1134. void phydm_ra_mask_watchdog(void *dm_void)
  1135. {
  1136. struct dm_struct *dm = (struct dm_struct *)dm_void;
  1137. struct ra_table *ra_t = &dm->dm_ra_table;
  1138. struct cmn_sta_info *sta = NULL;
  1139. struct ra_sta_info *ra = NULL;
  1140. u8 sta_idx;
  1141. u64 ra_mask;
  1142. u8 rssi_lv_new;
  1143. u8 rssi = 0;
  1144. if (!(dm->support_ability & ODM_BB_RA_MASK))
  1145. return;
  1146. if (!dm->is_linked || (dm->phydm_sys_up_time % 2) == 1)
  1147. return;
  1148. PHYDM_DBG(dm, DBG_RA_MASK, "%s ======>\n", __func__);
  1149. ra_t->up_ramask_cnt++;
  1150. for (sta_idx = 0; sta_idx < ODM_ASSOCIATE_ENTRY_NUM; sta_idx++) {
  1151. sta = dm->phydm_sta_info[sta_idx];
  1152. if (!is_sta_active(sta))
  1153. continue;
  1154. ra = &sta->ra_info;
  1155. if (ra->disable_ra)
  1156. continue;
  1157. PHYDM_DBG(dm, DBG_RA_MASK, "sta_idx=%d, macid=%d\n", sta_idx,
  1158. sta->mac_id);
  1159. rssi = (u8)(sta->rssi_stat.rssi);
  1160. /*@to be modified*/
  1161. #if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
  1162. if (dm->support_ic_type == ODM_RTL8812 ||
  1163. (dm->support_ic_type == ODM_RTL8821 &&
  1164. dm->cut_version == ODM_CUT_A)
  1165. ) {
  1166. if (rssi < ra_t->ldpc_thres) {
  1167. /*@LDPC TX enable*/
  1168. #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
  1169. set_ra_ldpc_8812(sta, true);
  1170. #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
  1171. MgntSet_TX_LDPC(sta->mac_id, true);
  1172. #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
  1173. /*to be added*/
  1174. #endif
  1175. PHYDM_DBG(dm, DBG_RA_MASK,
  1176. "RSSI=%d, ldpc_en =TRUE\n", rssi);
  1177. } else if (rssi > (ra_t->ldpc_thres + 3)) {
  1178. /*@LDPC TX disable*/
  1179. #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
  1180. set_ra_ldpc_8812(sta, false);
  1181. #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
  1182. MgntSet_TX_LDPC(sta->mac_id, false);
  1183. #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
  1184. /*to be added*/
  1185. #endif
  1186. PHYDM_DBG(dm, DBG_RA_MASK,
  1187. "RSSI=%d, ldpc_en =FALSE\n", rssi);
  1188. }
  1189. }
  1190. #endif
  1191. rssi_lv_new = phydm_rssi_lv_dec(dm, (u32)rssi, ra->rssi_level);
  1192. if (ra->rssi_level != rssi_lv_new ||
  1193. ra_t->up_ramask_cnt >= FORCED_UPDATE_RAMASK_PERIOD) {
  1194. PHYDM_DBG(dm, DBG_RA_MASK, "RSSI LV:((%d))->((%d))\n",
  1195. ra->rssi_level, rssi_lv_new);
  1196. ra->rssi_level = rssi_lv_new;
  1197. ra_t->up_ramask_cnt = 0;
  1198. ra_mask = phydm_get_bb_mod_ra_mask(dm, sta_idx);
  1199. if (ra_t->record_ra_info)
  1200. ra_t->record_ra_info(dm, sta_idx, sta, ra_mask);
  1201. #if (RTL8188E_SUPPORT) && (RATE_ADAPTIVE_SUPPORT)
  1202. if (dm->support_ic_type == ODM_RTL8188E)
  1203. /*@Driver RA*/
  1204. phydm_ra_update_8188e(dm, sta_idx, ra->rate_id,
  1205. (u32)ra_mask,
  1206. ra->is_support_sgi);
  1207. else
  1208. #endif
  1209. {
  1210. /*@FW RA*/
  1211. phydm_ra_h2c(dm, sta_idx, ra->disable_ra,
  1212. ra->disable_pt, 1, 0, ra_mask);
  1213. }
  1214. }
  1215. }
  1216. }
  1217. u8 phydm_vht_en_mapping(void *dm_void, u32 wireless_mode)
  1218. {
  1219. struct dm_struct *dm = (struct dm_struct *)dm_void;
  1220. u8 vht_en_out = 0;
  1221. if (wireless_mode == PHYDM_WIRELESS_MODE_AC_5G ||
  1222. wireless_mode == PHYDM_WIRELESS_MODE_AC_24G ||
  1223. wireless_mode == PHYDM_WIRELESS_MODE_AC_ONLY)
  1224. vht_en_out = 1;
  1225. PHYDM_DBG(dm, DBG_RA, "wireless_mode= (( 0x%x )), VHT_EN= (( %d ))\n",
  1226. wireless_mode, vht_en_out);
  1227. return vht_en_out;
  1228. }
  1229. u8 phydm_rftype2rateid_2g_n20(void *dm_void, u8 rf_type)
  1230. {
  1231. u8 rate_id_idx = 0;
  1232. if (rf_type == RF_1T1R)
  1233. rate_id_idx = PHYDM_BGN_20M_1SS;
  1234. else if (rf_type == RF_2T2R)
  1235. rate_id_idx = PHYDM_BGN_20M_2SS;
  1236. else if (rf_type == RF_3T3R)
  1237. rate_id_idx = PHYDM_ARFR5_N_3SS;
  1238. else
  1239. rate_id_idx = PHYDM_ARFR7_N_4SS;
  1240. return rate_id_idx;
  1241. }
  1242. u8 phydm_rftype2rateid_2g_n40(void *dm_void, u8 rf_type)
  1243. {
  1244. u8 rate_id_idx = 0;
  1245. if (rf_type == RF_1T1R)
  1246. rate_id_idx = PHYDM_BGN_40M_1SS;
  1247. else if (rf_type == RF_2T2R)
  1248. rate_id_idx = PHYDM_BGN_40M_2SS;
  1249. else if (rf_type == RF_3T3R)
  1250. rate_id_idx = PHYDM_ARFR5_N_3SS;
  1251. else
  1252. rate_id_idx = PHYDM_ARFR7_N_4SS;
  1253. return rate_id_idx;
  1254. }
  1255. u8 phydm_rftype2rateid_5g_n(void *dm_void, u8 rf_type)
  1256. {
  1257. u8 rate_id_idx = 0;
  1258. if (rf_type == RF_1T1R)
  1259. rate_id_idx = PHYDM_GN_N1SS;
  1260. else if (rf_type == RF_2T2R)
  1261. rate_id_idx = PHYDM_GN_N2SS;
  1262. else if (rf_type == RF_3T3R)
  1263. rate_id_idx = PHYDM_ARFR5_N_3SS;
  1264. else
  1265. rate_id_idx = PHYDM_ARFR7_N_4SS;
  1266. return rate_id_idx;
  1267. }
  1268. u8 phydm_rftype2rateid_ac80(void *dm_void, u8 rf_type)
  1269. {
  1270. u8 rate_id_idx = 0;
  1271. if (rf_type == RF_1T1R)
  1272. rate_id_idx = PHYDM_ARFR1_AC_1SS;
  1273. else if (rf_type == RF_2T2R)
  1274. rate_id_idx = PHYDM_ARFR0_AC_2SS;
  1275. else if (rf_type == RF_3T3R)
  1276. rate_id_idx = PHYDM_ARFR4_AC_3SS;
  1277. else
  1278. rate_id_idx = PHYDM_ARFR6_AC_4SS;
  1279. return rate_id_idx;
  1280. }
  1281. u8 phydm_rftype2rateid_ac40(void *dm_void, u8 rf_type)
  1282. {
  1283. u8 rate_id_idx = 0;
  1284. if (rf_type == RF_1T1R)
  1285. rate_id_idx = PHYDM_ARFR2_AC_2G_1SS;
  1286. else if (rf_type == RF_2T2R)
  1287. rate_id_idx = PHYDM_ARFR3_AC_2G_2SS;
  1288. else if (rf_type == RF_3T3R)
  1289. rate_id_idx = PHYDM_ARFR4_AC_3SS;
  1290. else
  1291. rate_id_idx = PHYDM_ARFR6_AC_4SS;
  1292. return rate_id_idx;
  1293. }
  1294. u8 phydm_rate_id_mapping(void *dm_void, u32 wireless_mode, u8 rf_type, u8 bw)
  1295. {
  1296. struct dm_struct *dm = (struct dm_struct *)dm_void;
  1297. u8 rate_id_idx = 0;
  1298. PHYDM_DBG(dm, DBG_RA,
  1299. "wireless_mode= (( 0x%x )), rf_type = (( 0x%x )), BW = (( 0x%x ))\n",
  1300. wireless_mode, rf_type, bw);
  1301. switch (wireless_mode) {
  1302. case PHYDM_WIRELESS_MODE_N_24G:
  1303. if (bw == CHANNEL_WIDTH_40)
  1304. rate_id_idx = phydm_rftype2rateid_2g_n40(dm, rf_type);
  1305. else
  1306. rate_id_idx = phydm_rftype2rateid_2g_n20(dm, rf_type);
  1307. break;
  1308. case PHYDM_WIRELESS_MODE_N_5G:
  1309. rate_id_idx = phydm_rftype2rateid_5g_n(dm, rf_type);
  1310. break;
  1311. case PHYDM_WIRELESS_MODE_G:
  1312. rate_id_idx = PHYDM_BG;
  1313. break;
  1314. case PHYDM_WIRELESS_MODE_A:
  1315. rate_id_idx = PHYDM_G;
  1316. break;
  1317. case PHYDM_WIRELESS_MODE_B:
  1318. rate_id_idx = PHYDM_B_20M;
  1319. break;
  1320. case PHYDM_WIRELESS_MODE_AC_5G:
  1321. case PHYDM_WIRELESS_MODE_AC_ONLY:
  1322. rate_id_idx = phydm_rftype2rateid_ac80(dm, rf_type);
  1323. break;
  1324. case PHYDM_WIRELESS_MODE_AC_24G:
  1325. /*@Becareful to set "Lowest rate" while using PHYDM_ARFR4_AC_3SS in 2.4G/5G*/
  1326. if (bw >= CHANNEL_WIDTH_80)
  1327. rate_id_idx = phydm_rftype2rateid_ac80(dm, rf_type);
  1328. else
  1329. rate_id_idx = phydm_rftype2rateid_ac40(dm, rf_type);
  1330. break;
  1331. default:
  1332. rate_id_idx = 0;
  1333. break;
  1334. }
  1335. PHYDM_DBG(dm, DBG_RA, "RA rate ID = (( 0x%x ))\n", rate_id_idx);
  1336. return rate_id_idx;
  1337. }
  1338. u8 phydm_rssi_lv_dec(void *dm_void, u32 rssi, u8 ratr_state)
  1339. {
  1340. struct dm_struct *dm = (struct dm_struct *)dm_void;
  1341. /*@MCS0 ~ MCS4 , VHT1SS MCS0 ~ MCS4 , G 6M~24M*/
  1342. u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {20, 34, 38, 42, 46, 50, 100};
  1343. u8 new_rssi_lv = 0;
  1344. u8 i;
  1345. PHYDM_DBG(dm, DBG_RA_MASK,
  1346. "curr RA level=(%d), Table_ori=[%d, %d, %d, %d, %d, %d]\n",
  1347. ratr_state, rssi_lv_t[0], rssi_lv_t[1], rssi_lv_t[2],
  1348. rssi_lv_t[3], rssi_lv_t[4], rssi_lv_t[5]);
  1349. for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
  1350. if (i >= (ratr_state))
  1351. rssi_lv_t[i] += RA_FLOOR_UP_GAP;
  1352. }
  1353. PHYDM_DBG(dm, DBG_RA_MASK,
  1354. "RSSI=(%d), Table_mod=[%d, %d, %d, %d, %d, %d]\n", rssi,
  1355. rssi_lv_t[0], rssi_lv_t[1], rssi_lv_t[2], rssi_lv_t[3],
  1356. rssi_lv_t[4], rssi_lv_t[5]);
  1357. for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
  1358. if (rssi < rssi_lv_t[i]) {
  1359. new_rssi_lv = i;
  1360. break;
  1361. }
  1362. }
  1363. return new_rssi_lv;
  1364. }
  1365. u8 phydm_rate_order_compute(void *dm_void, u8 rate_idx)
  1366. {
  1367. u8 rate_order = 0;
  1368. if (rate_idx >= ODM_RATEVHTSS4MCS0)
  1369. rate_idx -= ODM_RATEVHTSS4MCS0;
  1370. else if (rate_idx >= ODM_RATEVHTSS3MCS0)
  1371. rate_idx -= ODM_RATEVHTSS3MCS0;
  1372. else if (rate_idx >= ODM_RATEVHTSS2MCS0)
  1373. rate_idx -= ODM_RATEVHTSS2MCS0;
  1374. else if (rate_idx >= ODM_RATEVHTSS1MCS0)
  1375. rate_idx -= ODM_RATEVHTSS1MCS0;
  1376. else if (rate_idx >= ODM_RATEMCS24)
  1377. rate_idx -= ODM_RATEMCS24;
  1378. else if (rate_idx >= ODM_RATEMCS16)
  1379. rate_idx -= ODM_RATEMCS16;
  1380. else if (rate_idx >= ODM_RATEMCS8)
  1381. rate_idx -= ODM_RATEMCS8;
  1382. rate_order = rate_idx;
  1383. return rate_order;
  1384. }
  1385. #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
  1386. u8 phydm_rate2ss(void *dm_void, u8 rate_idx)
  1387. {
  1388. u8 ret = 0xff;
  1389. u8 i, j;
  1390. u8 search_idx;
  1391. u32 ss_mapping_tab[4][3] = {{0x00000000, 0x003ff000, 0x000ff000},
  1392. {0x00000000, 0xffc00000, 0x0ff00000},
  1393. {0x000003ff, 0x0000000f, 0xf0000000},
  1394. {0x000ffc00, 0x00000ff0, 0x00000000} };
  1395. if (rate_idx < 32) {
  1396. search_idx = rate_idx;
  1397. j = 0;
  1398. } else if (rate_idx < 64) {
  1399. search_idx = rate_idx - 32;
  1400. j = 1;
  1401. } else {
  1402. search_idx = rate_idx - 64;
  1403. j = 2;
  1404. }
  1405. for (i = 0; i < 4; i++)
  1406. if (ss_mapping_tab[i][j] & BIT(search_idx))
  1407. ret = i;
  1408. return ret;
  1409. }
  1410. u8 phydm_rate2plcp(void *dm_void, u8 rate_idx)
  1411. {
  1412. u8 rate2ss = 0;
  1413. u8 ltftime = 0;
  1414. u8 plcptime = 0xff;
  1415. if (rate_idx < ODM_RATE6M) {
  1416. plcptime = 192;
  1417. /* @CCK PLCP = 192us (long preamble) */
  1418. } else if (rate_idx < ODM_RATEMCS0) {
  1419. plcptime = 20;
  1420. /* @LegOFDM PLCP = 20us */
  1421. } else {
  1422. if (rate_idx < ODM_RATEVHTSS1MCS0)
  1423. plcptime = 32;
  1424. /* @HT mode PLCP = 20us + 12us + 4us x Nss */
  1425. else
  1426. plcptime = 36;
  1427. /* VHT mode PLCP = 20us + 16us + 4us x Nss */
  1428. rate2ss = phydm_rate2ss(dm_void, rate_idx);
  1429. if (rate2ss != 0xff)
  1430. ltftime = (rate2ss + 1) * 4;
  1431. else
  1432. return 0xff;
  1433. plcptime += ltftime;
  1434. }
  1435. return plcptime;
  1436. }
  1437. u8 phydm_get_plcp(void *dm_void, u16 macid)
  1438. {
  1439. u8 plcp_time = 0;
  1440. struct dm_struct *dm = (struct dm_struct *)dm_void;
  1441. struct cmn_sta_info *sta = NULL;
  1442. struct ra_sta_info *ra = NULL;
  1443. sta = dm->phydm_sta_info[macid];
  1444. ra = &sta->ra_info;
  1445. plcp_time = phydm_rate2plcp(dm, ra->curr_tx_rate);
  1446. return plcp_time;
  1447. }
  1448. #endif
  1449. void phydm_ra_common_info_update(void *dm_void)
  1450. {
  1451. struct dm_struct *dm = (struct dm_struct *)dm_void;
  1452. struct ra_table *ra_tab = &dm->dm_ra_table;
  1453. struct cmn_sta_info *sta = NULL;
  1454. u16 macid;
  1455. u8 rate_order_tmp;
  1456. u8 rate_idx = 0;
  1457. u8 cnt = 0;
  1458. ra_tab->highest_client_tx_order = 0;
  1459. ra_tab->power_tracking_flag = 1;
  1460. if (!dm->number_linked_client)
  1461. return;
  1462. for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) {
  1463. sta = dm->phydm_sta_info[macid];
  1464. if (!is_sta_active(sta))
  1465. continue;
  1466. rate_idx = sta->ra_info.curr_tx_rate & 0x7f;
  1467. rate_order_tmp = phydm_rate_order_compute(dm, rate_idx);
  1468. if (rate_order_tmp >= ra_tab->highest_client_tx_order) {
  1469. ra_tab->highest_client_tx_order = rate_order_tmp;
  1470. ra_tab->highest_client_tx_rate_order = macid;
  1471. }
  1472. cnt++;
  1473. if (cnt == dm->number_linked_client)
  1474. break;
  1475. }
  1476. PHYDM_DBG(dm, DBG_RA,
  1477. "MACID[%d], Highest Tx order Update for power traking: %d\n",
  1478. ra_tab->highest_client_tx_rate_order,
  1479. ra_tab->highest_client_tx_order);
  1480. }
  1481. void phydm_ra_info_watchdog(void *dm_void)
  1482. {
  1483. struct dm_struct *dm = (struct dm_struct *)dm_void;
  1484. phydm_ra_common_info_update(dm);
  1485. phydm_ra_dynamic_retry_count(dm);
  1486. phydm_ra_mask_watchdog(dm);
  1487. #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
  1488. odm_refresh_basic_rate_mask(dm);
  1489. #endif
  1490. }
  1491. void phydm_ra_info_init(void *dm_void)
  1492. {
  1493. struct dm_struct *dm = (struct dm_struct *)dm_void;
  1494. struct ra_table *ra_tab = &dm->dm_ra_table;
  1495. ra_tab->highest_client_tx_rate_order = 0;
  1496. ra_tab->highest_client_tx_order = 0;
  1497. ra_tab->ra_th_ofst = 0;
  1498. ra_tab->ra_ofst_direc = 0;
  1499. #if (RTL8822B_SUPPORT == 1)
  1500. if (dm->support_ic_type == ODM_RTL8822B) {
  1501. u32 ret_value;
  1502. ret_value = odm_get_bb_reg(dm, R_0x4c8, MASKBYTE2);
  1503. odm_set_bb_reg(dm, R_0x4cc, MASKBYTE3, (ret_value - 1));
  1504. }
  1505. #endif
  1506. #if 0 /*@CONFIG_RA_DYNAMIC_RTY_LIMIT*/
  1507. phydm_ra_dynamic_retry_limit_init(dm);
  1508. #endif
  1509. #if 0 /*@CONFIG_RA_DYNAMIC_RATE_ID*/
  1510. phydm_ra_dynamic_rate_id_init(dm);
  1511. #endif
  1512. phydm_rate_adaptive_mask_init(dm);
  1513. }
  1514. u8 odm_find_rts_rate(void *dm_void, u8 tx_rate, boolean is_erp_protect)
  1515. {
  1516. struct dm_struct *dm = (struct dm_struct *)dm_void;
  1517. u8 rts_ini_rate = ODM_RATE6M;
  1518. if (is_erp_protect) { /* use CCK rate as RTS*/
  1519. rts_ini_rate = ODM_RATE1M;
  1520. } else {
  1521. switch (tx_rate) {
  1522. case ODM_RATEVHTSS4MCS9:
  1523. case ODM_RATEVHTSS4MCS8:
  1524. case ODM_RATEVHTSS4MCS7:
  1525. case ODM_RATEVHTSS4MCS6:
  1526. case ODM_RATEVHTSS4MCS5:
  1527. case ODM_RATEVHTSS4MCS4:
  1528. case ODM_RATEVHTSS4MCS3:
  1529. case ODM_RATEVHTSS3MCS9:
  1530. case ODM_RATEVHTSS3MCS8:
  1531. case ODM_RATEVHTSS3MCS7:
  1532. case ODM_RATEVHTSS3MCS6:
  1533. case ODM_RATEVHTSS3MCS5:
  1534. case ODM_RATEVHTSS3MCS4:
  1535. case ODM_RATEVHTSS3MCS3:
  1536. case ODM_RATEVHTSS2MCS9:
  1537. case ODM_RATEVHTSS2MCS8:
  1538. case ODM_RATEVHTSS2MCS7:
  1539. case ODM_RATEVHTSS2MCS6:
  1540. case ODM_RATEVHTSS2MCS5:
  1541. case ODM_RATEVHTSS2MCS4:
  1542. case ODM_RATEVHTSS2MCS3:
  1543. case ODM_RATEVHTSS1MCS9:
  1544. case ODM_RATEVHTSS1MCS8:
  1545. case ODM_RATEVHTSS1MCS7:
  1546. case ODM_RATEVHTSS1MCS6:
  1547. case ODM_RATEVHTSS1MCS5:
  1548. case ODM_RATEVHTSS1MCS4:
  1549. case ODM_RATEVHTSS1MCS3:
  1550. case ODM_RATEMCS31:
  1551. case ODM_RATEMCS30:
  1552. case ODM_RATEMCS29:
  1553. case ODM_RATEMCS28:
  1554. case ODM_RATEMCS27:
  1555. case ODM_RATEMCS23:
  1556. case ODM_RATEMCS22:
  1557. case ODM_RATEMCS21:
  1558. case ODM_RATEMCS20:
  1559. case ODM_RATEMCS19:
  1560. case ODM_RATEMCS15:
  1561. case ODM_RATEMCS14:
  1562. case ODM_RATEMCS13:
  1563. case ODM_RATEMCS12:
  1564. case ODM_RATEMCS11:
  1565. case ODM_RATEMCS7:
  1566. case ODM_RATEMCS6:
  1567. case ODM_RATEMCS5:
  1568. case ODM_RATEMCS4:
  1569. case ODM_RATEMCS3:
  1570. case ODM_RATE54M:
  1571. case ODM_RATE48M:
  1572. case ODM_RATE36M:
  1573. case ODM_RATE24M:
  1574. rts_ini_rate = ODM_RATE24M;
  1575. break;
  1576. case ODM_RATEVHTSS4MCS2:
  1577. case ODM_RATEVHTSS4MCS1:
  1578. case ODM_RATEVHTSS3MCS2:
  1579. case ODM_RATEVHTSS3MCS1:
  1580. case ODM_RATEVHTSS2MCS2:
  1581. case ODM_RATEVHTSS2MCS1:
  1582. case ODM_RATEVHTSS1MCS2:
  1583. case ODM_RATEVHTSS1MCS1:
  1584. case ODM_RATEMCS26:
  1585. case ODM_RATEMCS25:
  1586. case ODM_RATEMCS18:
  1587. case ODM_RATEMCS17:
  1588. case ODM_RATEMCS10:
  1589. case ODM_RATEMCS9:
  1590. case ODM_RATEMCS2:
  1591. case ODM_RATEMCS1:
  1592. case ODM_RATE18M:
  1593. case ODM_RATE12M:
  1594. rts_ini_rate = ODM_RATE12M;
  1595. break;
  1596. case ODM_RATEVHTSS4MCS0:
  1597. case ODM_RATEVHTSS3MCS0:
  1598. case ODM_RATEVHTSS2MCS0:
  1599. case ODM_RATEVHTSS1MCS0:
  1600. case ODM_RATEMCS24:
  1601. case ODM_RATEMCS16:
  1602. case ODM_RATEMCS8:
  1603. case ODM_RATEMCS0:
  1604. case ODM_RATE9M:
  1605. case ODM_RATE6M:
  1606. rts_ini_rate = ODM_RATE6M;
  1607. break;
  1608. case ODM_RATE11M:
  1609. case ODM_RATE5_5M:
  1610. case ODM_RATE2M:
  1611. case ODM_RATE1M:
  1612. rts_ini_rate = ODM_RATE1M;
  1613. break;
  1614. default:
  1615. rts_ini_rate = ODM_RATE6M;
  1616. break;
  1617. }
  1618. }
  1619. if (*dm->band_type == ODM_BAND_5G) {
  1620. if (rts_ini_rate < ODM_RATE6M)
  1621. rts_ini_rate = ODM_RATE6M;
  1622. }
  1623. return rts_ini_rate;
  1624. }
  1625. #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
  1626. void odm_refresh_basic_rate_mask(
  1627. void *dm_void)
  1628. {
  1629. struct dm_struct *dm = (struct dm_struct *)dm_void;
  1630. void *adapter = dm->adapter;
  1631. static u8 stage = 0;
  1632. u8 cur_stage = 0;
  1633. OCTET_STRING os_rate_set;
  1634. PMGNT_INFO mgnt_info = GetDefaultMgntInfo(((PADAPTER)adapter));
  1635. u8 rate_set[5] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M, MGN_6M};
  1636. if (dm->support_ic_type != ODM_RTL8812 && dm->support_ic_type != ODM_RTL8821)
  1637. return;
  1638. if (dm->is_linked == false) /* unlink Default port information */
  1639. cur_stage = 0;
  1640. else if (dm->rssi_min < 40) /* @link RSSI < 40% */
  1641. cur_stage = 1;
  1642. else if (dm->rssi_min > 45) /* @link RSSI > 45% */
  1643. cur_stage = 3;
  1644. else
  1645. cur_stage = 2; /* @link 25% <= RSSI <= 30% */
  1646. if (cur_stage != stage) {
  1647. if (cur_stage == 1) {
  1648. FillOctetString(os_rate_set, rate_set, 5);
  1649. FilterSupportRate(mgnt_info->mBrates, &os_rate_set, false);
  1650. phydm_set_hw_reg_handler_interface(dm, HW_VAR_BASIC_RATE, (u8 *)&os_rate_set);
  1651. } else if (cur_stage == 3 && (stage == 1 || stage == 2))
  1652. phydm_set_hw_reg_handler_interface(dm, HW_VAR_BASIC_RATE, (u8 *)(&mgnt_info->mBrates));
  1653. }
  1654. stage = cur_stage;
  1655. }
  1656. #endif
  1657. #if 0 /*@CONFIG_RA_DYNAMIC_RTY_LIMIT*/
  1658. void phydm_retry_limit_table_bound(
  1659. void *dm_void,
  1660. u8 *retry_limit,
  1661. u8 offset)
  1662. {
  1663. struct dm_struct *dm = (struct dm_struct *)dm_void;
  1664. struct ra_table *ra_tab = &dm->dm_ra_table;
  1665. if (*retry_limit > offset) {
  1666. *retry_limit -= offset;
  1667. if (*retry_limit < ra_tab->retrylimit_low)
  1668. *retry_limit = ra_tab->retrylimit_low;
  1669. else if (*retry_limit > ra_tab->retrylimit_high)
  1670. *retry_limit = ra_tab->retrylimit_high;
  1671. } else
  1672. *retry_limit = ra_tab->retrylimit_low;
  1673. }
  1674. void phydm_reset_retry_limit_table(
  1675. void *dm_void)
  1676. {
  1677. struct dm_struct *dm = (struct dm_struct *)dm_void;
  1678. struct ra_table *ra_t = &dm->dm_ra_table;
  1679. u8 i;
  1680. u8 per_rate_retrylimit_table_20M[ODM_RATEMCS15 + 1] = {
  1681. 1, 1, 2, 4, /*@CCK*/
  1682. 2, 2, 4, 6, 8, 12, 16, 18, /*OFDM*/
  1683. 2, 4, 6, 8, 12, 18, 20, 22, /*@20M HT-1SS*/
  1684. 2, 4, 6, 8, 12, 18, 20, 22 /*@20M HT-2SS*/
  1685. };
  1686. u8 per_rate_retrylimit_table_40M[ODM_RATEMCS15 + 1] = {
  1687. 1, 1, 2, 4, /*@CCK*/
  1688. 2, 2, 4, 6, 8, 12, 16, 18, /*OFDM*/
  1689. 4, 8, 12, 16, 24, 32, 32, 32, /*@40M HT-1SS*/
  1690. 4, 8, 12, 16, 24, 32, 32, 32 /*@40M HT-2SS*/
  1691. };
  1692. memcpy(&ra_t->per_rate_retrylimit_20M[0],
  1693. &per_rate_retrylimit_table_20M[0], ODM_NUM_RATE_IDX);
  1694. memcpy(&ra_t->per_rate_retrylimit_40M[0],
  1695. &per_rate_retrylimit_table_40M[0], ODM_NUM_RATE_IDX);
  1696. for (i = 0; i < ODM_NUM_RATE_IDX; i++) {
  1697. phydm_retry_limit_table_bound(dm,
  1698. &ra_t->per_rate_retrylimit_20M[i],
  1699. 0);
  1700. phydm_retry_limit_table_bound(dm,
  1701. &ra_t->per_rate_retrylimit_40M[i],
  1702. 0);
  1703. }
  1704. }
  1705. void phydm_ra_dynamic_retry_limit_init(
  1706. void *dm_void)
  1707. {
  1708. struct dm_struct *dm = (struct dm_struct *)dm_void;
  1709. struct ra_table *ra_tab = &dm->dm_ra_table;
  1710. ra_tab->retry_descend_num = RA_RETRY_DESCEND_NUM;
  1711. ra_tab->retrylimit_low = RA_RETRY_LIMIT_LOW;
  1712. ra_tab->retrylimit_high = RA_RETRY_LIMIT_HIGH;
  1713. phydm_reset_retry_limit_table(dm);
  1714. }
  1715. void phydm_ra_dynamic_retry_limit(
  1716. void *dm_void)
  1717. {
  1718. struct dm_struct *dm = (struct dm_struct *)dm_void;
  1719. struct ra_table *ra_tab = &dm->dm_ra_table;
  1720. u8 i, retry_offset;
  1721. u32 ma_rx_tp;
  1722. if (dm->pre_number_active_client == dm->number_active_client) {
  1723. PHYDM_DBG(dm, DBG_RA,
  1724. "pre_number_active_client == number_active_client\n");
  1725. return;
  1726. } else {
  1727. if (dm->number_active_client == 1) {
  1728. phydm_reset_retry_limit_table(dm);
  1729. PHYDM_DBG(dm, DBG_RA,
  1730. "one client only->reset to default value\n");
  1731. } else {
  1732. retry_offset = dm->number_active_client * ra_tab->retry_descend_num;
  1733. for (i = 0; i < ODM_NUM_RATE_IDX; i++) {
  1734. phydm_retry_limit_table_bound(dm,
  1735. &ra_tab->per_rate_retrylimit_20M[i],
  1736. retry_offset);
  1737. phydm_retry_limit_table_bound(dm,
  1738. &ra_tab->per_rate_retrylimit_40M[i],
  1739. retry_offset);
  1740. }
  1741. }
  1742. }
  1743. }
  1744. #endif
  1745. #if 0 /*@CONFIG_RA_DYNAMIC_RATE_ID*/
  1746. void phydm_ra_dynamic_rate_id_on_assoc(
  1747. void *dm_void,
  1748. u8 wireless_mode,
  1749. u8 init_rate_id)
  1750. {
  1751. struct dm_struct *dm = (struct dm_struct *)dm_void;
  1752. PHYDM_DBG(dm, DBG_RA,
  1753. "[ON ASSOC] rf_mode = ((0x%x)), wireless_mode = ((0x%x)), init_rate_id = ((0x%x))\n",
  1754. dm->rf_type, wireless_mode, init_rate_id);
  1755. if (dm->rf_type == RF_2T2R || dm->rf_type == RF_2T3R || dm->rf_type == RF_2T4R) {
  1756. if ((dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) &&
  1757. (wireless_mode & (ODM_WM_N24G | ODM_WM_N5G))) {
  1758. PHYDM_DBG(dm, DBG_RA,
  1759. "[ON ASSOC] set N-2SS ARFR5 table\n");
  1760. odm_set_mac_reg(dm, R_0x4a4, MASKDWORD, 0xfc1ffff); /*N-2SS, ARFR5, rate_id = 0xe*/
  1761. odm_set_mac_reg(dm, R_0x4a8, MASKDWORD, 0x0); /*N-2SS, ARFR5, rate_id = 0xe*/
  1762. } else if ((dm->support_ic_type & (ODM_RTL8812)) &&
  1763. (wireless_mode & (ODM_WM_AC_5G | ODM_WM_AC_24G | ODM_WM_AC_ONLY))) {
  1764. PHYDM_DBG(dm, DBG_RA,
  1765. "[ON ASSOC] set AC-2SS ARFR0 table\n");
  1766. odm_set_mac_reg(dm, R_0x444, MASKDWORD, 0x0fff); /*@AC-2SS, ARFR0, rate_id = 0x9*/
  1767. odm_set_mac_reg(dm, R_0x448, MASKDWORD, 0xff01f000); /*@AC-2SS, ARFR0, rate_id = 0x9*/
  1768. }
  1769. }
  1770. }
  1771. void phydm_ra_dynamic_rate_id_init(
  1772. void *dm_void)
  1773. {
  1774. struct dm_struct *dm = (struct dm_struct *)dm_void;
  1775. if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) {
  1776. odm_set_mac_reg(dm, R_0x4a4, MASKDWORD, 0xfc1ffff); /*N-2SS, ARFR5, rate_id = 0xe*/
  1777. odm_set_mac_reg(dm, R_0x4a8, MASKDWORD, 0x0); /*N-2SS, ARFR5, rate_id = 0xe*/
  1778. odm_set_mac_reg(dm, R_0x444, MASKDWORD, 0x0fff); /*@AC-2SS, ARFR0, rate_id = 0x9*/
  1779. odm_set_mac_reg(dm, R_0x448, MASKDWORD, 0xff01f000); /*@AC-2SS, ARFR0, rate_id = 0x9*/
  1780. }
  1781. }
  1782. void phydm_update_rate_id(
  1783. void *dm_void,
  1784. u8 rate,
  1785. u8 platform_macid)
  1786. {
  1787. #if 0
  1788. struct dm_struct *dm = (struct dm_struct *)dm_void;
  1789. struct ra_table *ra_tab = &dm->dm_ra_table;
  1790. u8 current_tx_ss;
  1791. u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/
  1792. u8 wireless_mode;
  1793. u8 phydm_macid;
  1794. struct sta_info *entry;
  1795. struct cmn_sta_info *sta;
  1796. #if 0
  1797. if (rate_idx >= ODM_RATEVHTSS2MCS0) {
  1798. PHYDM_DBG(dm, DBG_RA, "rate[%d]: (( VHT2SS-MCS%d ))\n",
  1799. platform_macid, (rate_idx - ODM_RATEVHTSS2MCS0));
  1800. /*@dummy for SD4 check patch*/
  1801. } else if (rate_idx >= ODM_RATEVHTSS1MCS0) {
  1802. PHYDM_DBG(dm, DBG_RA, "rate[%d]: (( VHT1SS-MCS%d ))\n",
  1803. platform_macid, (rate_idx - ODM_RATEVHTSS1MCS0));
  1804. /*@dummy for SD4 check patch*/
  1805. } else if (rate_idx >= ODM_RATEMCS0) {
  1806. PHYDM_DBG(dm, DBG_RA, "rate[%d]: (( HT-MCS%d ))\n",
  1807. platform_macid, (rate_idx - ODM_RATEMCS0));
  1808. /*@dummy for SD4 check patch*/
  1809. } else {
  1810. PHYDM_DBG(dm, DBG_RA, "rate[%d]: (( HT-MCS%d ))\n",
  1811. platform_macid, rate_idx);
  1812. /*@dummy for SD4 check patch*/
  1813. }
  1814. #endif
  1815. phydm_macid = dm->phydm_macid_table[platform_macid];
  1816. entry = dm->odm_sta_info[phydm_macid];
  1817. sta = dm->phydm_sta_info[phydm_macid];
  1818. if (is_sta_active(sta)) {
  1819. wireless_mode = entry->wireless_mode;
  1820. if (dm->rf_type == RF_2T2R || dm->rf_type == RF_2T3R || dm->rf_type == RF_2T4R) {
  1821. if (wireless_mode & (ODM_WM_N24G | ODM_WM_N5G)) { /*N mode*/
  1822. if (rate_idx >= ODM_RATEMCS8 && rate_idx <= ODM_RATEMCS15) { /*@2SS mode*/
  1823. sta->ra_info.rate_id = ARFR_5_RATE_ID;
  1824. PHYDM_DBG(dm, DBG_RA, "ARFR_5\n");
  1825. }
  1826. } else if (wireless_mode & (ODM_WM_AC_5G | ODM_WM_AC_24G | ODM_WM_AC_ONLY)) {/*@AC mode*/
  1827. if (rate_idx >= ODM_RATEVHTSS2MCS0 && rate_idx <= ODM_RATEVHTSS2MCS9) {/*@2SS mode*/
  1828. sta->ra_info.rate_id = ARFR_0_RATE_ID;
  1829. PHYDM_DBG(dm, DBG_RA, "ARFR_0\n");
  1830. }
  1831. } else
  1832. sta->ra_info.rate_id = ARFR_0_RATE_ID;
  1833. PHYDM_DBG(dm, DBG_RA, "UPdate_RateID[%d]: (( 0x%x ))\n",
  1834. platform_macid, sta->ra_info.rate_id);
  1835. }
  1836. }
  1837. #endif
  1838. }
  1839. #endif